coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2019-08-12	soc/sifive/fu540: add code for spi and map flash to memory spaces	Xiang Wang
	SiFive's ZSBL has initialized flash, but only 16MB of space is available. 1. add code for spi 2. add code to map flash to memory spaces Change-Id: I106688c65ac7dd70be7479dc4691797b700682d9 Signed-off-by: Xiang Wang <merle@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-03	soc/sifive/fu540: Simplify UART refclk calculation	Jonathan Neuschäfer
	clock_get_coreclk_khz() already detects whether the PLL or the input clock (hfclk) is used. Tested on HiFive Unleashed. Change-Id: I264977b0de0b81ef74a014984b6d33638ab33f4b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/29334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-05	riscv: add support smp_pause / smp_resume	Xiang Wang
	See https://doc.coreboot.org/arch/riscv/ we know that we need to execute smp_pause at the start of each stage and smp_resume at the end of each stage. Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/29023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-09-15	sifive/hifive-unleashed: enable CBMEM support	Philipp Hug
	Change-Id: I3eacba9c1c20bbfa270dd7a9afabe48ed9092bcc Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28622 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-14	soc/sifive/fu540: Switch clock to 1GHz in romstage	Philipp Hug
	Invoke clock_init in romstage for SiFive Unleashed. Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-09-10	soc/sifive/fu540: Makefile: include mtime_init in ramstage	Philipp Hug
	Fix compilation issue clint.c/mtime.c is needed as well in ramstage due to CR 28372 and 28355 Change-Id: I7c7768744a165b97978bb8f7f95acf7b32ca4aa4 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28551 Tested-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-09-10	soc/sifive/fu540: Add driver for OTP memory	Philipp Hug
	Provides minimal functionality to read the SOC s/n from the NeoFuse one time programmable memory. Change-Id: I14b010ad9958931e0a98a76f76090fd7c66f19a0 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-10	soc/sifive/fu540: add CLINT support	Xiang Wang
	Change-Id: Ibc3a8644dcb83d5697d9d6e551c7682377285116 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-10	riscv: update mtime initialization	Xiang Wang
	Add a interface, which is implemented by SoC. Change-Id: I5524732f6eb3841e43afd176644119b03b5e5e27 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-07-18	sifive/fu540: add empty sdram init and size functions	Philipp Hug
	Change-Id: I65f900a3277bc8a4a83ebc8883d4a325bd690bf8 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-26	src/sifive: Add the SiFive Freedom Unleashed 540 SoC	Jonathan Neuschäfer
	The FU540 is the first RISC-V SoC with the necessary resources to run Linux (an external memory interface, MMU, etc). More information is available on SiFive's website: https://www.sifive.com/products/hifive-unleashed/ Change-Id: Ic2a3c7b1dfa56b67cc0571969cc9cf67a770ae43 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>