coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-05-18	src: Remove leading blank lines from SPDX header	Elyes HAOUAS
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-09	src/: Replace GPL boilerplate with SPDX headers	Patrick Georgi
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2019-08-12	soc/sifive/fu540: add code for spi and map flash to memory spaces	Xiang Wang
2018-12-03	soc/sifive/fu540: Simplify UART refclk calculation	Jonathan Neuschäfer
2018-11-05	riscv: add support smp_pause / smp_resume	Xiang Wang
2018-09-15	sifive/hifive-unleashed: enable CBMEM support	Philipp Hug
2018-09-14	soc/sifive/fu540: Switch clock to 1GHz in romstage	Philipp Hug
2018-09-10	soc/sifive/fu540: Makefile: include mtime_init in ramstage	Philipp Hug
2018-09-10	soc/sifive/fu540: Add driver for OTP memory	Philipp Hug
2018-09-10	soc/sifive/fu540: add CLINT support	Xiang Wang
2018-09-10	riscv: update mtime initialization	Xiang Wang
2018-07-18	sifive/fu540: add empty sdram init and size functions	Philipp Hug
2018-04-26	src/sifive: Add the SiFive Freedom Unleashed 540 SoC	Jonathan Neuschäfer