| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-11-05 | riscv: add support smp_pause / smp_resume | Xiang Wang |
| 2018-09-14 | arch/riscv: provide a monotonic timer | Philipp Hug |
| 2018-09-13 | uart/sifive: make divisor configurable | Philipp Hug |
| 2018-07-17 | riscv: add support for modifying compiler options | Xiang Wang |
| 2018-04-26 | src/sifive: Add the SiFive Freedom Unleashed 540 SoC | Jonathan Neuschäfer |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |