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2015-04-10gpio: Extend common GPIO header, simplify function namesJulius Werner
We've had gpiolib.h which defines a few common GPIO access functions for a while, but it wasn't really complete. This patch adds the missing gpio_output() function, and also renames the unwieldy gpio_get_in_value() and gpio_set_out_value() to the much easier to handle gpio_get() and gpio_set(). The header is renamed to the simpler gpio.h while we're at it (there was never really anything "lib" about it, and it was presumably just chosen due to the IPQ806x include/ conflict problem that is now resolved). It also moves the definition of gpio_t into SoC-specific code, so that different implementations are free to encode their platform-specific GPIO parameters in those 4 bytes in the most convenient way (such as the rk3288 with a bitfield struct). Every SoC intending to use this common API should supply a <soc/gpio.h> that typedefs gpio_t to a type at most 4 bytes in length. Files accessing the API only need to include <gpio.h> which may pull in additional things (like a gpio_t creation macro) from <soc/gpio.h> on its own. For now the API is still only used on non-x86 SoCs. Whether it makes sense to expand it to x86 as well should be separately evaluated at a later point (by someone who understands those systems better). Also, Exynos retains its old, incompatible GPIO API even though it would be a prime candidate, because it's currently just not worth the effort. BUG=None TEST=Compiled on Daisy, Peach_Pit, Nyan_Blaze, Rush_Ryu, Storm and Veyron_Pinky. Change-Id: Ieee77373c2bd13d07ece26fa7f8b08be324842fe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9e04902ada56b929e3829f2c3b4aeb618682096e Original-Change-Id: I6c1e7d1e154d9b02288aabedb397e21e1aadfa15 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220975 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9400 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-08timer: Add generic udelay() implementationAaron Durbin
Add GENERIC_UDELAY Kconfig option so that a generic udelay() implementation is provided utilizing the monotonic timer. That way each board/chipset doesn't need to duplicate the same udelay(). Additionally, assume that GENERIC_UDELAY implies init_timer() is not required. BUG=None BRANCH=None TEST=Built nyan, ryu, and rambi. May need help testing. Change-Id: I7f511a2324b5aa5d1b2959f4519be85a6a7360e8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1a85fbcad778933d13eaef545135abe7e4de46ed Original-Change-Id: Idd26de19eefc91ee3b0ceddfb1bc2152e19fd8ab Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219719 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9334 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-07exynos5420: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns exynos5420 to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Peach_Pit. Change-Id: If97b40101d3541a81bca302a9bd64b84a04ff24a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 570ca9ed6337d622781f37184b2cd7209de0083f Original-Change-Id: I338559564e57bdc5202d34c7173ce0d075ad2afc Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224501 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9324 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-07exynos5250: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns exynos5250 to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Daisy. Change-Id: I39805c0346e117a0f9b2667763ecaa428f0f55a8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: db6762f0c8425371d9860f908a5cefdeee8d1abc Original-Change-Id: Ic358061ddcbbe7d83a95ca11247b8b505b20491d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224500 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9323 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-07kconfig: drop intermittend forwarder filesStefan Reinauer
With kconfig understanding wildcards, we don't need Kconfig files that just include other Kconfig files anymore. Change-Id: I7584e675f78fcb4ff1fdb0731e340533c5bc040d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9298 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-06New mechanism to define SRAM/memory map with automatic bounds checkingJulius Werner
This patch creates a new mechanism to define the static memory layout (primarily in SRAM) for a given board, superseding the brittle mass of Kconfigs that we were using before. The core part is a memlayout.ld file in the mainboard directory (although boards are expected to just include the SoC default in most cases), which is the primary linker script for all stages (though not rmodules for now). It uses preprocessor macros from <memlayout.h> to form a different valid linker script for all stages while looking like a declarative, boilerplate-free map of memory addresses to the programmer. Linker asserts will automatically guarantee that the defined regions cannot overlap. Stages are defined with a maximum size that will be enforced by the linker. The file serves to both define and document the memory layout, so that the documentation cannot go missing or out of date. The mechanism is implemented for all boards in the ARM, ARM64 and MIPS architectures, and should be extended onto all systems using SRAM in the future. The CAR/XIP environment on x86 has very different requirements and the layout is generally not as static, so it will stay like it is and be unaffected by this patch (save for aligning some symbol names for consistency and sharing the new common ramstage linker script include). BUG=None TEST=Booted normally and in recovery mode, checked suspend/resume and the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies with ToT and looked for red flags. Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614 Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213370 Reviewed-on: http://review.coreboot.org/9283 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-06Add predefined __ROMSTAGE__ and __RAMSTAGE__ macrosJulius Werner
This patch adds the macros __ROMSTAGE__ and __RAMSTAGE__ which get predefined in their respective stages by make, so that we have one specific macro for every stage. It also renames __BOOT_BLOCK__ and __VER_STAGE__ to __BOOTBLOCK__ and __VERSTAGE__ for consistency. This change is intended to provide finer control and clearer communication of intent after we added a new (optional) stage that falls under __PRE_RAM__, and will hopefully provide some robustness for the future (we don't want to end up always checking for romstage with #if defined(__PRE_RAM__) && !defined(__BOOT_BLOCK__) && !defined(__VER_STAGE__) && !defined(__YET_ANOTHER_PRERAM_STAGE__)). The __PRE_RAM__ macro stays as it is since many features do in fact need to differentiate on whether RAM is available. (Some also depend on whether RAM is available at the end of a stage, in which case #if !defined(__PRE_RAM__) || defined(__ROMSTAGE__) should now be authoritative.) It's unfeasable to change all existing occurences of __PRE_RAM__ that would be better described with __ROMSTAGE__, so this patch only demonstratively changes a few obvious ones in core code. BUG=None TEST=None (tested together with dependent patch). Change-Id: I6a06d0f42c27a2feeb778a4acd35dd14bb53f744 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a4ad042746c1d3a7a3bfda422d26e0d3b9f9ae42 Original-Change-Id: I6a1f25f7077328a8b5201a79b18fc4c2e22d0b06 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219172 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9304 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-04-04build system: rename __BOOT_BLOCK__ and __VER_STAGE__Patrick Georgi
Drop the inner underscore for consistency. Follows the commit stated below. Change-Id: I75cde6e2cd55d2c0fbb5a2d125c359d91e14cf6d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-on-Change-Id: I6a1f25f7077328a8b5201a79b18fc4c2e22d0b06 Based-on-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-on-Reviewed-on: https://chromium-review.googlesource.com/219172 Reviewed-on: http://review.coreboot.org/9290 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-03-21exynos: convert to stopwatch APIAaron Durbin
Instead of open coding monotonic timer usage, use the stopwatch API. BUG=None BRANCH=None TEST=None Change-Id: I1c541c1c9f3fde0dec9163ad6cc94322538ac7f7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 46ede0897687da6bcf730a8904f25e5a4485d6cd Original-Change-Id: Ia63a05850a1b6afdc42c2422332f77af516d27e3 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219716 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8825 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17coreboot classes: Add dynamic classes to corebootFurquan Shaikh
Provide functionality to create dynamic classes based on program name and the architecture for which the program needs to be compiled/linked. define_class takes program_name and arch as its arguments and adds the program_name to classes-y to create dynamic class and compiler toolset is created for the specified arch. All the files for this program can then be added to program_name-y += .. Ensure that define_class is called before any files are added to the class. Check subdirs-y for order of directory inclusion. One such example of dynamic class is rmodules. Multiple rmodules can be used which need to be compiled for different architectures. With dynamic classes, this is possible. BUG=chrome-os-partner:30784 BRANCH=None TEST=Compiles successfully for nyan, rush and link. Original-Change-Id: I3e3aadbe723d432b9b3500c44bcff578c98f5643 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209379 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 242bb90d7476c2ee47d60c50ee18785edeb1a295) Some of this cherry-pick had already been committed here: commit 133096b6dc31163f59f658e15f2eb342a0de2ac6 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9f5868d704c4b3251ca6f54afa634588108a788c Reviewed-on: http://review.coreboot.org/8672 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-27CBMEM: Always use DYNAMIC_CBMEMKyösti Mälkki
Drop the implementation of statically allocated high memory region for CBMEM. There is no longer the need to explicitly select DYNAMIC_CBMEM, it is the only remaining choice. Change-Id: Iadf6f27a134e05daa1038646d0b4e0b8f9f0587a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7851 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27vboot2: add verstageStefan Reinauer
This reverts the revert commit 5780d6f3876723b94fbe3653c9d87dad6330862e and fixes the build issue that cuased it to be reverted. Verstage will host vboot2 for firmware verification. It's a stage in the sense that it has its own set of toolchains, compiler flags, and includes. This allows us to easily add object files as needed. But it's directly linked to bootblock. This allows us to avoid code duplication for stage loading and jumping (e.g. cbfs driver) for the boards where bootblock has to run in a different architecture (e.g. Tegra124). To avoid name space conflict, verstage symbols are prefixed with verstage_. TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Iad57741157ec70426c676e46c5855e6797ac1dac Original-Reviewed-on: https://chromium-review.googlesource.com/204376 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 27940f891678dae975b68f2fc729ad7348192af3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2a83b87c29d98d97ae316091cf3ed7b024e21daf Reviewed-on: http://review.coreboot.org/8224 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-06doxygen fixes: change @var to @param varMartin Roth
These files were trying to document the parameters, but didn't have the syntax quite right. Change the comments from @varname to @param varname as required by doxygen. Change-Id: I63662094d3f1686e3e35b61925b580eb06e72e28 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8100 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06doxygen fixes: fix parameter names to match the functionsMartin Roth
The doxygen parameter names in the comments no longer matched the functions they were attached to. Doxygen complains about extra parameter comments and uncommented parameters in the functions. Change-Id: I21b8a951f8d8d04b07c3779000eeaf1e69fed463 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8101 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-30i2c: Add software_i2c driver for I2C debugging and emulationJulius Werner
This patch adds I2C emulation in software through raw toggling of the SDA/SCL lines. Platforms need to provide bindings to toggle their respective I2C busses for this to work (e.g. by pinmuxing them as GPIOs, currently only enabled for Tegra). This is mostly useful as a debugging feature, to drive unusual states on a bus and closely monitor the device output without the need of a bus analyzer. It provides a few functions to "wedge" an I2C bus by aborting a transaction at certain points, which can be used to test if a system can correctly recover from an ill-timed reboot. However, it can also dynamically replace the existing I2C transfer functions and drive some/all I2C transfers on the system, which might be useful if a driver for the actual I2C controller hardware is not (yet) available. Based on original code by Doug Anderson <dianders@chromium.org> and Hung-ying Tyan <tyanh@chromium.org> for the ChromeOS embedded controller project. BRANCH=None BUG=chrome-os-partner:28323 TEST=Spread tegra_software_i2c_init()/tegra_software_i2c_disable() through the code and see that everything still works. Original-Change-Id: I9ee7ccbd1efb38206669a35d0c3318af16f8be63 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/198791 Original-Reviewed-by: Doug Anderson <dianders@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 8f71503dbbd74c5298e90e2163b67d4efe3e89db) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id6c5f75bb5baaabd62b6b1fc26c2c71d9f1ce682 Reviewed-on: http://review.coreboot.org/7947 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-30ipq/arm: Redesign hooks for bootblockVadim Bendebury
The following patches had to be squashed to properly build all the different ARM boards. ipq8064: storm: re-arrange bootblock initialization The recent addition of the storm bootblock initialization broke compilation of Exynos platforms. The SOC specific code needs to be kept in the respective source files, not in the common CPU code. As of now coreboot does not provide a separate SOC initialization API. In general it makes sense to invoke SOC initialization from the board initialization code, as the board knows what SOC it is running on. Presently all what's need initialization on 8064 is the timer. This patch adds the SOC initialization framework for 8064 and moves there the related code. BUG=chrome-os-partner:27784 TEST=manual . nyan_big, peach_pit, and storm targets build fine now. Original-Change-Id: Iae9a021f8cbf7d009770b02d798147a3e08420e8 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197835 (cherry picked from commit 3ea7307b531b1a78c692e4f71a0d81b32108ebf0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> arm: Redesign mainboard and SoC hooks for bootblock This patch makes some slight changes to the way bootblock_cpu_init() and bootblock_mainboard_init() are used on ARM. Experience has shown that nearly every board needs either one or both of these hooks, so having explicit Kconfigs for them has become unwieldy. Instead, this patch implements them as a weak symbol that can be overridden by mainboard/SoC code, as the more recent arm64_soc_init() is also doing. Since the whole concept of a single "CPU" on ARM systems has kinda died out, rename bootblock_cpu_init() to bootblock_soc_init(). (This had already been done on Storm/ipq806x, which is now adjusted to directly use the generic hook.) Also add a proper license header to bootblock_common.h that was somehow missing. Leaving non-ARM32 architectures out for now, since they are still using the really old and weird x86 model of directly including a file. These architectures should also eventually be aligned with the cleaner ARM32 model as they mature. BRANCH=None BUG=chrome-os-partner:32123 TEST=Booted on Pinky. Compiled for Storm and confirmed in the disassembly that bootblock_soc_init() is still compiled in and called right before the (now no-op) bootblock_mainboard_init(). Original-Change-Id: I57013b99c3af455cc3d7e78f344888d27ffb8d79 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/231940 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 257aaee9e3aeeffe50ed54de7342dd2bc9baae76) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id055fe60a8caf63a9787138811dc69ac04dfba57 Reviewed-on: http://review.coreboot.org/7879 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-27samsung/exynos*/Makefile.inc: Simplify unnecessary ifeqEdward O'Callaghan
It's not needed, as we can use a simpler macro instead. Change-Id: Ib96f5cfa434d0383ee3bfe49995a8f8830987f20 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7925 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-12-26soc/samsung/exynos5250/clk.h: Trivial, fix spelling in commentsEdward O'Callaghan
Change-Id: Iaacd4d7977ddeff4204acdc32d4d13fd88b6660b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7928 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-26soc/samsung/exynos5250/clock.c: Trivial whitespace fixesEdward O'Callaghan
Reduce difference with exynos5420/clock.c by fixing some whitespace and an include directive. Change-Id: Ifbdd61c8300f3988f5f729fe7d6124ac8a9b7821 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7926 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-26soc/samsung/exynos: Sync 'power.c' between chip variantsEdward O'Callaghan
Change-Id: I06d83be840b49ee7523b34e1dba5ec038256b3f4 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7918 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-25soc/samsung/exynos: Make 'ps_hold_setup()' staticEdward O'Callaghan
Change-Id: I272fea9c2767c341e8a545bf7a9ac18eefa2bda5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7917 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-16i2c: Replace the i2c API.Gabe Black
The new API is in use in depthcharge and is based around the "i2c_transfer" function instead of i2c_read and i2c_write. The new function takes an array of i2c_seg structures which represent each portion of the transfer after a start bit and before the stop bit. If there's more than one segment, they're seperated by repeated starts. Some wrapper functions have also been added which make certain common operations easy. These include reading or writing a byte from a register or reading or writing a blob of raw data. The i2c device drivers generally use these wrappers but can call the i2c_transfer function directly if the need something different. The tegra i2c driver was very similar to the one in depthcharge and was simple to convert. The Exynos 5250 and 5420 drivers were ported from depthcharge and replace the ones in coreboot. The Exynos 5420 driver was ported from the high speed portion of the one in coreboot and was straightforward to port back. The low speed portion and the Exynos 5250 drivers had been transplanted from U-Boot and were replaced with the depthcharge implementation. BUG=None TEST=Built and booted on nyan with and without EFS. Built and booted on, pit and daisy. BRANCH=None Original-Change-Id: I1e98c3fa2560be25444ab3d0394bb214b9d56e93 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193561 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 00c423fb2c06c69d580ee3ec0a3892ebf164a5fe) This cherry-pick required additional changes to the following: src/cpu/allwinner/a10/twi.c src/drivers/xpowers/axp209/axp209.c Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I691959c66308eeeec219b1bec463b8b365a246d7 Reviewed-on: http://review.coreboot.org/7751 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-09spi: Eliminate the spi_cs_activate and spi_cs_deactivate functions.Gabe Black
They were only used internal to the SPI drivers and, according to the comment next to their prototypes, were for when the SPI controller doesn't control the chip select line directly and needs some help. BUG=None TEST=Built for link, falco, and rambi. Built and booted on peach_pit and nyan. BRANCH=None Original-Change-Id: If4622819a4437490797d305786e2436e2e70c42b Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/192048 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 1e2deecd9d8c6fd690c54f24e902cc7d2bab0521) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ida08cbc2be5ad09b929ca16e483c36c49ac12627 Reviewed-on: http://review.coreboot.org/7708 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-12-09spi: Remove the spi_set_speed and spi_cs_is_valid functions.Gabe Black
spi_set_speed was never implemented, and spi_cs_is_valid was only implemented as a stub and never called. BUG=None TEST=Built for rambi, falco, and peach_pit. BRANCH=None Original-Change-Id: If30c2339f5e0360a5099eb540fab73fb23582905 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/192045 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 98c1f6014c512e75e989df36b48622a7b56d0582) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iebdb2704ee81aee432c83ab182246d31ef52a6b6 Reviewed-on: http://review.coreboot.org/7707 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-12-09spi: Factor EC protocol details out of the SPI drivers.Gabe Black
The SPI drivers for tegra and exynos5420 have code in them which waits for a frame header and leaves filler data out. The SPI driver shouldn't have support for frame headers directly. If a device uses them, it should support them itself. That makes the SPI drivers simpler and easier to write. When moving the frame handling logic into the EC support code, EC communication continued to work on tegra but no longer worked on exynos5420. That suggested the SPI driver on the 5420 wasn't working correctly, so I replaced that with the implementation in depthcharge. Unfortunately that implementation doesn't support waiting for a frame header for the EC, so these changes are combined into one. BUG=None TEST=Built and booted on pit. Built and booted on nyan. In both cases, verified that there were no error messages from the SPI drivers or the EC code. BRANCH=None Original-Change-Id: I62a68820c632f154acece94f54276ddcd1442c09 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/191192 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 4fcfed280ad70f14a013d5353aa0bee0af540630) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id8824523abc7afcbc214845901628833e135d142 Reviewed-on: http://review.coreboot.org/7706 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-12-08samsung/exynos5420: Spelling FixesMartin Roth
Change-Id: I966645c83ae78943a7dbb9dc05af4fded6f4e5b5 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7703 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-02Replace hlt with halt()Patrick Georgi
There were instances of unneeded arch/hlt.h includes, various hlt() calls that weren't supposed to exit (but might have) and various forms of endless loops around hlt() calls. All these are sorted out now: unnecessary includes are dropped, hlt() is uniformly replaced with halt() (except in assembly, obviously). Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7608 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-10arm: Redesign, clarify and clean up cache related codeJulius Werner
This patch changes several cache-related pieces to be cleaner, faster or more correct. The largest point is removing the old arm_invalidate_caches() function and surrounding bootblock code to initialize SCTLR and replace it with an all-assembly function that takes care of cache and SCTLR initialization to bring the system to a known state. It runs without stack and before coreboot makes any write accesses to be as compatible as possible with whatever state the system was left in by preceeding code. This also finally fixes the dreaded icache bug that wasted hundreds of milliseconds during boot. Old-Change-Id: I7bb4995af8184f6383f8e3b1b870b0662bde8bd4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183890 (cherry picked from commit 07a35925dc957919bf88dfc90515971a36e81b97) nyan_big: apply cache-related changes from nyan This applies the same changes from 07a3592 that were applied to nyan. Old-Change-Id: Idcbe85436d7a2f65fcd751954012eb5f4bec0b6c Reviewed-on: https://chromium-review.googlesource.com/184551 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 4af27f02614da41c611aee2c6d175b1b948428ea) Squashed the followup patch for nyan_big into the original patch. Change-Id: Id14aef7846355ea2da496e55da227b635aca409e Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> (cherry picked from commit 4cbf25f8eca3a12bbfec5b015953c0fc2b69c877) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/6993 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-01{cpu,soc}: Use DEVICE_NOOP macro over dummy symbolEdward O'Callaghan
Change-Id: Iaf2b2873bd1c52d7f936bd9b483e194a0872a626 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7285 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-10-16uarts: 32/64 cleanupRonald G. Minnich
We had lots of casts that caused warnings when compiling on RISCV. Clean them up. Change-Id: I46fcb33147ad6bf75e49ebfdfa05990e8c7ae4eb Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7066 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-22Add check_member macro to allow clean and easy struct offset checkingJulius Werner
This patch adds a new static assertion macro that can be used to check the offsets in structures that overlay register sets at compile time. It uses the _Static_assert() declaration from the new ISO C11 standard, which is supported (even without -std=c11) by GCC after version 4.6. (There is supposedly also support in clang, although I haven't tried it... let's deal with compiler issues when/if they turn up.) I've added it to all structures for our current ARM SoCs for now, and I think every new register overlay we add going forward should use them (at least for the last member, but feel free to add more if you think it's useful). Change-Id: If32510e7049739ad05618d363a854dc372d64386 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179412 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit cef5fa13c31375a316ca4556c0039b17c8ea7900) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6905 Tested-by: build bot (Jenkins)
2014-09-19exynos5250: remove unused ret variable in cpu.cIsaac Christensen
Showed up as an error when '--gc-sections' was added as a flag to the compiler. Change-Id: I214d3e16a72fca0becc677d7af66097464d64247 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6926 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-15exynos5250: Fix PMU register address mapJulius Werner
Patch 12b121f3fef61d introduced an off-by-one error in the offsets of the PMU register struct, which put both the newly added register and the PSHOLD that comes after it in the wrong place. This patch corrects the offsets (5420 had already been correct). Change-Id: I1d9d31a6a73ee91890824e94fbd247d5feb4f6ae Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179411 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 5fdc74bc18bcb1066a0ce3ba94829af1b175173b) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6892 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-10Exynos5420: Fix up the i2c driver for use with the TPM driverGabe Black
The TPM driver expects to call i2c_read with zero address length. The i2c driver wasn't prepared to handle that particularly in the case of reads because it expected to send an address before switching over to read mode for the data. This change also fixes up the read and write calls to consistently be read32 and write32 instead of readl and writel. Change-Id: I33dee89b83d4cd9d3e1b90e84b40e761bb8d4de4 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/175966 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit cf686269424ea938d6f953d0f76103182eb71297) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6857 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-09exynos: Install the BL1 and set the checksum in the Makefile.Gabe Black
Install the BL1 and set up the checksum in the Makefile instead of relying on post processing. Import the exynos checksum script, split it in two and simplify it significantly. Stop putting the CBFS header in the midst of the bootblock so that it can be checksummed before CBFS is put together. Stop saving space for it and leaving an anchor in the bootblock which nobody looks for. Change-Id: Icbb5a5914ece60b2827433b6dc29d80db996ea6c Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/179229 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit aa3a416705517c0a6ddfdeb19905ac8cafb33df1) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6834 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-29exynos: Fix the name of the chip_operations structures.Gabe Black
The exynos directories had been moved from src/cpu to src/soc, but the name of the chip_operations structure wasn't updated properly. That meant that the SOCs never installed their memory resources and the ram stage would fail to load the payload. Change-Id: Ib60489b6d3434e3ebd13827a804452f762747f1b Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172400 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 9100d475ebcc4dae23184583a6cc0162577e70d1) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6781 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-29arm: libpayload: Make cache invalidation take pointers instead of integersJulius Werner
This minor refactoring patch changes the signature of all limited cache invalidation functions in coreboot and libpayload from unsigned long to void * for the address argument, since that's really what you have in 95% of the cases and I think it's ugly to have casting boilerplate all over the place. Change-Id: Ic9d3b2ea70b6aa8aea6647adae43ee2183b4e065 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167338 (cherry picked from commit d550bec944736dfa29fcf109e30f17a94af03576) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6623 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-26armv7: Move Exynos from 'cpu' to 'soc'.Hung-Te Lin
The Exynos family and most ARM products are SoC, not just CPU. We used to put ARM code in src/cpu to avoid polluting the code base for what was essentially an experiment at the time. Now that it's past the experimental phase and we're going to see more SoCs (including intel/baytrail) in coreboot. Change-Id: I5ea1f822664244edf5f77087bc8018d7c535f81c Reviewed-on: https://chromium-review.googlesource.com/170891 Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit c8bb8fe0b20be37465f93c738d80e7e43033670a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6739 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>