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2018-04-03spi: Add helper functions for bit-bangingJulius Werner
Sometimes when bringing up a new board it can take a while until you have all the peripheral drivers ready. For those cases it is nice to be able to bitbang certain protocols so that you can already get further in the boot flow while those drivers are still being worked on. We already have this support for I2C, but it would be nice to have something for SPI as well, since without SPI you're not going to boot very far. This patch adds a couple of helper functions that platforms can use to implement bit-banging SPI with minimal effort. It also adds a proof of concept implementation using the RK3399. Change-Id: Ie3551f51cc9a9f8bf3a47fd5cea6d9c064da8a62 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-03rockchip: Add gpio_set() functionJulius Werner
The <gpio.h> API is supposed to include a gpio_set() function that just toggles the state of a GPIO already configured as an output, even though we rarely need it since gpio_output() can already be used to initialze a GPIO to a default value while configuring it as an output. This function was forgotten on Rockchip, so this patch adds it now. Change-Id: I201288139a2870e71f55a7af0d79d4a460b30a0c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-02rockchip/rk3399: Pass coreboot table pointer to ARM TFJulius Werner
This patch passes the coreboot table base address to ARM TF on RK3399 devices to be able to use the new coreboot table parsing support. Change-Id: I5cb2f13ce71e374207d0fa7a71c38852d680dc56 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/23557 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-02rockchip: Correct UART reference clock valueJulius Werner
The Rockchip UARTs are tied directly to the 24MHz oscillator and are thus clocked with exactly 24MHz. The reasons why our code instead uses some 23.xxMHz value have long been lost in time. For the current shared 8250 implementation, the baud rate divisor for 115200 would be the same. Correcting this does make the information in the coreboot table more accurate and help payloads chose a better divisor, though. Change-Id: Ieceb07760178f8ddbb5936f8742b78f8def4072d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/23556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-02rockchip/rk3288: Fix includes for <soc/clock.h>Julius Werner
This header uses common types and macros so it needs to include the headers that provide those itself. Change-Id: Ieceb0deadbeef8ddbbb00b13542b78f8def4072d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/23559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-02-02rockchip/rk3399: extend delay between saradc power up and start commandLin Huang
We found when ambient temperature low, with now saradc frequency and delay between saradc power up and start command, there may get wrong adc value, then get the wrong ramid or boardid, so lower the saradc frequency and add the delay time between power up and start command. BUG=b:70692504 BRANCH=gru TEST=test on Dru in 0C temperature, always get right adc value Change-Id: I42e49ca63299479912fa05e2a62cba6f2de4b337 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/23515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-29rockchip/rk3399: Support LONG_WRITE type in MIPI DSILin Huang
Some panels need to transfer initial code, and some of them will be over 3 bytes, so support LONG_WRITE type in driver. Refactor mipi dsi transfer function to support it. Change-Id: I212c14165e074c40a4a1a25140d9e8dfdfba465f Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/23299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-01-10soc/rockchip/rk3399: Ensure full eDP init sequenceEge Mihmanli
This patch fixes 2 edp display issues: 1. When rk_edp_prepare fails >3 times, edp_init isn't run because while-condition is not satisfied. Then, only a partial init sequence is ran. This causes all aux transactions to fail. 2. If rk_edp_prepare never succeeds, coreboot never leaves link training stage due to infinite loop. Boot process is stuck. TEST=Boot past eDP initialization stage and make sure AP logs don't have show aux transaction fails. Change-Id: I44c3f53e8786558c43078d4afe9acde4d64796e7 Signed-off-by: Ege Mihmanli <egemih@google.com> Reviewed-on: https://review.coreboot.org/23152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-12-11google/gru: Stop mucking with unused I2S0 pins in codec configJulius Werner
Due to a schematic error, our code was written to configure more I2S0 pins than are actually used. We're also pinmuxing the whole bank of pins over to the I2S controller even though we don't need them all. Restrict the GPIO initialization and pinmuxing to the pins we really need so the other ones can be correctly used as SKU ID pins on Scarlet. Also, move the "audio" IO voltage domain selection to the other such selections in the bootblock, since that covers two whole banks of GPIOs and there's no guarantee that they're all used for audio (and thus not needed before ramstage). BUG=b:69373077 TEST=Booted Scarlet, confirmed correct SKU ID (7) was detected on rev2. Change-Id: I9314617e725fe83d254984529f269d4442e736f1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Schneider <dnschneid@chromium.org>
2017-12-07rockchip/rk3399: Select GENERIC_GPIO_LIB KconfigJulius Werner
This option should've been selected by RK3399 the whole time since the SoC supports the <soc/gpio.h> interface. It wasn't really a big deal until now where I'm trying to use a the base2 read helper, though. Change-Id: Ib7a5f00a6680163105fc0598ce77d03f3645f05a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22744 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-28google/scarlet: support kd097d04 panelLin Huang
Support kd097d04 dual mipi panel on Scarlet. Change-Id: Ie8bc0cbb79840f1924a8cc111f2511292203731f Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28rockchip/rk3399: support dual mipi dsiLin Huang
Refactor the mipi driver, so we can support dual mipi panel. And pass the panel data from mainboard.c, that we can support different panel with different board. Change-Id: Id1286c0ccbe50c89514c8daee66439116d3f1ca4 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28rockchip/rk3399: mipi: properly configure PHY timingLin Huang
These values are specified as constant time periods but the PHY configuration is in terms of the current lane byte clock so using constant values guarantees that the timings will be outside the specification with some display configurations. Derive the necessary configuration from the byte clock in order to ensure that the PHY configuration is correct. Change-Id: I396029956730907a33babe39c6a171f2fcea9dcd Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28rockchip/rk3399: improve mipi transfer flowLin Huang
check GEN_CMD_FULL status before transfer, check GEN_CMD_EMPTY and GEN_PLD_W_EMPTY status after transfer. Change-Id: I936c0d888b10f13141519f95ac7bcae3e15e95d9 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28rockchip/rk3399: mipi: correct Feedback divider settingLin Huang
This patch correct Feedback divider setting: 1. Due to the use of a "by 2 pre-scaler," the range of the feedback multiplication Feedback divider is limited to even division numbers, and Feedback divider must be greater than 12, less than 1000. 2. Make the previously configured Feedback divider(LSB) factors effective Change-Id: Ic7c5c59be1d00c65c3b17cb3c4bfba8d7459e960 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28rockchip/rk3399: mipi: correct phy parameter settingLin Huang
As MIPI PHY document show, icpctrl<3..0> and lpfctrl<5..0> should depend on frequency, so fix it. Change-Id: Ic4a90767bd1f22d5d784d4013dc7afb3149115c1 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28rockchip/rk3399: mipi: Fix LOOP_DIV_HIGH_SEL to be 4 bits wideLin Huang
Accroding to datasheet, feedback divider register high value is only 4 bit, it currently uses 5 bit, so correct it. Change-Id: I1fe9fc076b712f27407c5f2735b15e64fb55e72e Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-10-23soc: Add Kconfig for each soc vendorChris Ching
Allows explicit ordering for vendors that share a common configuration that must be sourced last. The issue is that chips in soc/{amd,intel}/[ab].* will be able to override defaults set in this file, but Kconfig files that get sourced later (soc/amd/[d-z].*) will NOT be able to override these defaults. Note: intel and amd soc chips now need to be added manually to the new Kconfig file BUG=b:62235314 TEST=make lint-stable Change-Id: Ida82ef184712e092aec1381a47aa1b54b74ed6b6 Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/22123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-18include/device: Split i2c.h into threeNico Huber
Split `i2c.h` into three pieces to ease reuse of the generic defi- nitions. No code is changed. * `i2c.h` - keeps the generic definitions * `i2c_simple.h` - holds the current, limited to one controller driver per board, devicetree independent I2C interface * `i2c_bus.h` - will become the devicetree compatible interface for native I2C (e.g. non-SMBus) controllers Change-Id: I382d45c70f9314588663e1284f264f877469c74d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-14i2c: Move to Linux like `struct i2c_msg`Nico Huber
Our current struct for I2C segments `i2c_seg` was close to being compa- tible to the Linux version `i2c_msg`, close to being compatible to SMBus and close to being readable (e.g. what was `chip` supposed to mean?) but turned out to be hard to fix. Instead of extending it in a backwards compatible way (and not touching current controller drivers), replace it with a Linux source compatible `struct i2c_msg` and patch all the drivers and users with Coccinelle. The new `struct i2c_msg` should ease porting drivers from Linux and help to write SMBus compatible controller drivers. Beside integer type changes, the field `read` is replaced with a generic field `flags` and `chip` is renamed to `slave`. Patched with Coccinelle using the clumsy spatch below and some manual changes: * Nested struct initializers and one field access skipped by Coccinelle. * Removed assumption in the code that I2C_M_RD is 1. * In `i2c.h`, changed all occurences of `chip` to `slave`. @@ @@ -struct i2c_seg +struct i2c_msg @@ identifier msg; expression e; @@ ( struct i2c_msg msg = { - .read = 0, + .flags = 0, }; | struct i2c_msg msg = { - .read = 1, + .flags = I2C_M_RD, }; | struct i2c_msg msg = { - .chip = e, + .slave = e, }; ) @@ struct i2c_msg msg; statement S1, S2; @@ ( -if (msg.read) +if (msg.flags & I2C_M_RD) S1 else S2 | -if (msg.read) +if (msg.flags & I2C_M_RD) S1 ) @@ struct i2c_msg *msg; statement S1, S2; @@ ( -if (msg->read) +if (msg->flags & I2C_M_RD) S1 else S2 | -if (msg->read) +if (msg->flags & I2C_M_RD) S1 ) @@ struct i2c_msg msg; expression e; @@ ( -msg.read = 0; +msg.flags = 0; | -msg.read = 1; +msg.flags = I2C_M_RD; | -msg.read = e; +msg.flags = e ? I2C_M_RD : 0; | -!!(msg.read) +(msg.flags & I2C_M_RD) | -(msg.read) +(msg.flags & I2C_M_RD) ) @@ struct i2c_msg *msg; expression e; @@ ( -msg->read = 0; +msg->flags = 0; | -msg->read = 1; +msg->flags = I2C_M_RD; | -msg->read = e; +msg->flags = e ? I2C_M_RD : 0; | -!!(msg->read) +(msg->flags & I2C_M_RD) | -(msg->read) +(msg->flags & I2C_M_RD) ) @@ struct i2c_msg msg; @@ -msg.chip +msg.slave @@ struct i2c_msg *msg; expression e; @@ -msg[e].chip +msg[e].slave @ slave disable ptr_to_array @ struct i2c_msg *msg; @@ -msg->chip +msg->slave Change-Id: Ifd7cabf0a18ffd7a1def25d1d7059b713d0b7ea9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-06rockchip: gpio: Correct rk3399 pmu gpio pull settingLin Huang
Starting with RK3399, PMUGPIO pull registers use the same write mask format as normal GRF registers, so they need to use RK_CLRSETBITS() rather than clrsetbits_le32(). BRANCH=None BUG=None TEST=boot from scarlet Change-Id: Ibe391273d58ab35df993e149187d67497fcf2acc Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/20871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-06rockchip: gpio: add gpio_pull argument in gpio_input_irq() functionLin Huang
some gpio irq need to set input pull initialization status to guarantee to get the right irq trigger. let's add this argument in gpio_input_irq() function BRANCH=None BUG=None TEST=boot from bob Change-Id: I9b8e6497f07146dafdb447a6ea10d039a2a2fa33 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/20866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-07-19rockchip/rk3399: Adjust gpio_t format to match ARM TFJulius Werner
Our structure packing for Rockchip's gpio_t was chosen arbitrarily. ARM Trusted Firmware has since become a thing and chosen a slightly different way to represent GPIOs in a 32-bit word. Let's align our format to them so we don't need to remember to convert the values every time we pass them through. CQ-DEPEND=CL:572228 Change-Id: I9ce33da28ee8a34d2d944bee010d8bfc06fe879b Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/20586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-26rockchip/rk3399: update the ddr 200MHz frequency configurationCaesar Wang
This patch updates the coreboot DDR Settings to match the configuration used by ARM-Trusted-Firmware. Change-Id: I34bc2950a9708ac89a5637bf682551e03d993fcc Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://review.coreboot.org/20304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-06-19rockchip/rk3399: fix DRAM gate training issueLin Huang
The differential signal of DQS needs to keep low level before gate training. RPULL will connect 4Kn from PADP to VSS and a 4Kn from PADN to VDDQ to ensure it. But if it has PHY side ODT connected at this time, it will change the DQS signal level. So it needs to disable PHY side ODT when doing gate training. BRANCH=None BUG=None TEST=boot from bob Change-Id: I56ace8375067aa0bb54d558bc28172b431b92ca5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: cb024042c7297a6b17c41cf650990cd342b1376f Original-Change-Id: I33cf743c3793a2765a21e5121ce7351410b9e19d Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/448278 Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com> Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://review.coreboot.org/18582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-08device/Kconfig: Introduce MAINBOARD_FORCE_NATIVE_VGA_INITNico Huber
MAINBOARD_FORCE_NATIVE_VGA_INIT is to be selected instead of the user option MAINBOARD_DO_NATIVE_VGA_INIT. The distinction is necessary to use the latter in a choice. Change-Id: I689aa5cadea9e1091180fd38b1dc093c6938d69c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-02Kconfig: Introduce HAVE_(VBE_)LINEAR_FRAMEBUFFERNico Huber
Like HAVE_VGA_TEXT_FRAMEBUFFER, these are selected by graphics drivers that support a linear framebuffer. Some related settings moved to the drivers (i.e. for rockchip/rk3288 and nvidia/tegra124) since they are hardcoded. Change-Id: Iff6dac5a5f61af49456bc6312e7a376def02ab00 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-26rockchip/rk3399: fix rk_mipi_dsi_phy_init errNickey Yang
This patch fix rk_mipi_dsi_phy_init error return. Change-Id: Ie260975ad6ed26c37aa8bb65dfcef4db2407a2da Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> Reviewed-on: https://review.coreboot.org/19903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-24rk3399: Reshuffle memlayout to move PRERAM_CBMEM_CONSOLE further backJulius Werner
It seems that the BootROM on the RK3399 overwrites some of the earlier parts of SRAM, including the PRERAM_CBMEM_CONSOLE area. Now that we have a persistent CBMEM console we want that area to survive in case of an early (pre-CBMEM) reboot, so shuffle the layout around a bit to move it further back. (This reduces the stack size to 12KB which should still be way more than enough.) Change-Id: Ifc1e568cda334394134bba9eba75088032d2ff13 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-24soc/rockchip: Move spi driver to use spi_bus_mapFurquan Shaikh
This is in preparation to get rid of the strong spi_setup_slave implemented by different platforms. BUG=b:38430839 Change-Id: I66b1b9635ece2381f62f2a9d6f5744d639d59163 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-18rockchip/rk3399: soc: resize reserve memoryXing Zheng
Reserve the whole TZRAM area because it will be marked as secure-only by BL31 and can not be accessed by the non-secure kernel. CQ-DEPEND=CL:452659 BUG=chrome-os-partner:57361 BRANCH=firmware-gru-8785.B TEST=the reserve memory is resized Change-Id: Ie3ab39598f3f7cb96feb0c574e230e7fcb53a1a4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f34d254e1dfc9ae95a784aba22503e75a2fa65f1 Original-Change-Id: I39c4cb530f41a7b0f7f3064125072dd85b62276f Original-Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/418102 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-(cherry picked from commit ea9fe064a9b1e1ce81fca74f829a0fb6e78ce426) Original-Reviewed-on: https://chromium-review.googlesource.com/452640 Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-18rockchip/rk3399: Add MIPI driverNickey Yang
This patch configures clock for mipi and then adds mipi driver for support innolux-p079zca mipi panel in rk3399 scarlet. Change-Id: I02475eefb187c619c614b1cd20e97074bc8d917f Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> Reviewed-on: https://review.coreboot.org/19477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-18rockchip/rk3399: remove the delay for enabling SSCCaesar Wang
The hang was caused by deasserting the reset before, it had been delayed 20us fixing the hang issue. So we can remove this delay for now. Change-Id: I5545377b72eb20b59ceaaca25c78965854bfb919 Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://review.coreboot.org/19699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-11rockchip/rk3399: enable DPLL SSC for DDR EMI test on bobCaesar Wang
Spread Spectrum Modulator (SSMOD) is a fully-digital circuit used to modulate the frequency of the Silicon Creations’ Fractional PLL in order to reduce EMI. We need to turn the DPLL spread spectrum feature on to reduce the EMI noise for DDR on bob. Change-Id: I75461d4235bcf55324e6664a1220754e770b4786 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://review.coreboot.org/19557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-05drivers/spi: Re-factor spi_crop_chunkFurquan Shaikh
spi_crop_chunk is a property of the SPI controller since it depends upon the maximum transfer size that is supported by the controller. Also, it is possible to implement this within spi-generic layer by obtaining following parameters from the controller: 1. max_xfer_size: Maximum transfer size supported by the controller (Size of 0 indicates invalid size, and unlimited transfer size is indicated by UINT32_MAX.) 2. deduct_cmd_len: Whether cmd_len needs to be deducted from the max_xfer_size to determine max data size that can be transferred. (This is used by the amd boards.) Change-Id: I81c199413f879c664682088e93bfa3f91c6a46e5 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19386 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: coreboot org <coreboot.org@gmail.com>
2017-05-03google/gru: skip usbphy1 setup for Scarletphilipchen
Board Scarlet doesn't use usbphy1. BUG=b:37685249 TEST=boot Scarlet, check the firmware log, and confirm no errors about USB1 Change-Id: I66e0d8a235cc9057964f7abca32bc692d41e88fd Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/19489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-03lib/edid.c: Differentiate between absent and non-conformant EDIDArthur Heymans
Change-Id: Id90aa210ff72092c4ab638a7bafb82bd11889bdc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-04-28rockchip: gpio: add gpio_input_irq & gpio_irq_statusJeffy Chen
BUG=b:35647967 TEST=boot from bob Change-Id: I5de902ab26fe768b641f69d85a5294baf6d916e3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 223257d486b026c06a1f3a7a830b829efb9932dc Original-Change-Id: I055ad5f59285cee3110d1e7cb1a53a60144712e4 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/452285 Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com> Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19433 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-03-28Remove libverstage as separate library and source file classJulius Werner
In builds without CONFIG_VBOOT_SEPARATE_VERSTAGE, verstage files are linked directly into the bootblock or the romstage. However, they're still compiled with a separate "libverstage" source file class, linked into an intermediate library and then linked into the final destination stage. There is no obvious benefit to doing it this way and it's unclear why it was chosen in the first place... there are, however, obvious disadvantages: it can result in code that is used by both libverstage and the host stage to occur twice in the output binary. It also means that libverstage files have their separate compiler flags that are not necessarily aligned with the host stage, which can lead to weird effects like <rules.h> macros not being set the way you would expect. In fact, VBOOT_STARTS_IN_ROMSTAGE configurations are currently broken on x86 because their libverstage code that gets compiled into the romstage sets ENV_VERSTAGE, but CAR migration code expects all ENV_VERSTAGE code to run pre-migration. This patch resolves these problems by removing the separate library. There is no more difference between the 'verstage' and 'libverstage' classes, and the source files added to them are just treated the same way a bootblock or romstage source files in configurations where the verstage is linked into either of these respective stages (allowing for the normal object code deduplication and causing those files to be compiled with the same flags as the host stage's files). Tested this whole series by booting a Kevin, an Elm (both with and without SEPARATE_VERSTAGE) and a Falco in normal and recovery mode. Change-Id: I6bb84a9bf1cd54f2e02ca1f665740a9c88d88df4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18302 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28vboot: Move remaining features out of vendorcode/google/chromeosJulius Werner
This patch attempts to finish the separation between CONFIG_VBOOT and CONFIG_CHROMEOS by moving the remaining options and code (including image generation code for things like FWID and GBB flags, which are intrinsic to vboot itself) from src/vendorcode/google/chromeos to src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig options, and clean up menuconfig visibility for them (i.e. some options were visible even though they were tied to the hardware while others were invisible even though it might make sense to change them). CQ-DEPEND=CL:459088 Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18984 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-24rockchip/rk3399: set edp pclk to 25MHzLin Huang
It may cause an edp aux transfer error if the edp pclk is set too high, so reduce it to 25MHz. BUG=chrome-os-partner:60130 BRANCH=None TEST=Build and Boot Change-Id: Id1063baa5a82637b03c0f1f754181df074ab17cc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8f7ce31a7483e765ae0c86f8e62ef51413ee1596 Original-Change-Id: Ibb86c12c1d7c00dc3b4cc7a6bdf3bd6e895cd9f3 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/429410 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18178 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-13rockchip/rk3288: rtc-rk808: fix rtc time reading issueJeffy Chen
After we set the GET_TIME bit, the rtc time can't be read immediately. We should wait up to 31.25 us, about one cycle of 32khz. Otherwise reading RTC time will return a old time. BUG=chrome-os-partner:61078 BRANCH=veyron TEST=Build and Boot Original-Change-Id: I6ec07fc6c4d6d8b27b12031423b86b8ab15da6f6 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/423272 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Change-Id: I9806b624d6e968e51d52aab8c052ae3fa77f247d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b4b708e29fbae0d8f5a2cece79711aa6b1887727 Original-Change-Id: I8c168c14437bb932a59ac0e91a01062df0cf11dc Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/427522 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18127 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-123rdparty: update arm-trusted-firmware submoduleMartin Roth
Updated to arm-trusted-firmware TOT: 236c27d2 (Merge pull request #805 from Xilinx/zynqmp/addr_space_size) 183 commits between Sep 20, 2016 and January 10, 2017 - Also add associated change to src/soc/rockship/rk3399 Makefile.inc that is required to build the M0 Firmware. Change-Id: I49695f3287a742cd1fb603b890d124f60788f88f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18024 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-03rockchip/common: Loosen I2C frequency target requirementsJulius Werner
I've recently added an assertion to ensure that the effective I2C frequency on Rockchip SoCs is not too far off the 400KHz target due to divisor rounding errors. A 10KHz margin worked fine for RK3399, but it turns out that RK3288 actually only ever hit 387KHz since its I2C clocks are based off the already pretty low 75MHz PCLKs. While we could probably change the PCLKs to make this closer, that seems like a too intrusive change for something that has already worked just fine for years, so just loosen the restriction a little more instead. BRANCH=None BUG=chromium:675043 TEST=None Change-Id: I7e96a1a75b38f8ad3971dd33046699cceb17b80d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/421095 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://review.coreboot.org/18007 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-13rockchip: rk3399: change emmc clk to 148.5MHzZiyuan Xu
Set aclk_emmc and clk_emmc to 148.5MHz under hs400es mode, which could improve stability like kernel. CQ-DEPEND=CL:386527 BUG=chrome-os-partner:54377 BRANCH=none TEST=build and boot on kevin Change-Id: Iaa76d3ec1ab999eb317a9ab6c7e3525594b15b57 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e6eb1f56371aea51f2584a97bf817189d61090b2 Original-Change-Id: If4754d22e83a0f9a029fedca12f26ff5ae8d44e1 Original-Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/386865 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17790 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-06rockchip/rk3399: sdram: use register to calculate sdram sizesLin Huang
We may support different sdram sizes on one board in future, so we need to calculate sdram sizes from sdram drvier. BRANCH=None BUG=None TEST=boot kevin Change-Id: I43e8f164ecdb768c051464b4dbc7d890df8055d0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3c4d8b3cb647b2f9cebc416c298817c16d49330e Original-Change-Id: I95d5ef34de9d79ebca3600dc7a4b9e14449606ff Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/411600 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17629 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-05rockchip/rk3399: display: Update edp initialization retryMartin Roth
Follow on patch to clean up the previous retry code. Previous patches: coreboot commit 079b5c65 (rockchip/rk3399: display: Retry edp initialization if it fails) cros commit 28c57a6e (rockchip/rk3399: display: retry edp initialization if edp initial fail) - Reduce the jumping around via goto statements - Break the retry code out into a separate function that also prints the error messages. BRANCH=gru BUG=chrome-os-partner:60150 TEST=Rebuild Kevin and Gru Change-Id: I3b6cf572073e4dcac83da09621bafde179af2613 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17642 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-12-05spi: Define and use spi_ctrlr structureFurquan Shaikh
1. Define a new structure spi_ctrlr that allows platforms to define callbacks for spi operations (claim bus, release bus, transfer). 2. Add a new member (pointer to spi_ctrlr structure) in spi_slave structure which will be initialized by call to spi_setup_slave. 3. Define spi_claim_bus, spi_release_bus and spi_xfer in spi-generic.c which will make appropriate calls to ctrlr functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Icb2326e3aab1e8f4bef53f553f82b3836358c55e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17684 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05spi: Pass pointer to spi_slave structure in spi_setup_slaveFurquan Shaikh
For spi_setup_slave, instead of making the platform driver return a pointer to spi_slave structure, pass in a structure pointer that can be filled in by the driver as required. This removes the need for platform drivers to maintain a slave structure in data/CAR section. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ia15a4f88ef4dcfdf616bb1c22261e7cb642a7573 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17683 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05spi: Fix parameter types for spi functionsFurquan Shaikh
1. Use size_t instead of unsigned int for bytes_out and bytes_in. 2. Use const attribute for spi_slave structure passed into xfer, claim bus and release bus functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ie70b3520b51c42d750f907892545510c6058f85a Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17682 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-03rockchip/rk3399: Fix typoPatrick Georgi
TRAINING, not TARINING. BUG=none BRANCH=none TEST=still builds Change-Id: I8b7ffd0f0544a58865865a8b09d9c153db9c2674 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b1ea846ce1ffd654d7d34c2a1d43b0fddbd4ae32 Original-Change-Id: I4940279ed7217cc20fe29c8b3603d1853acbfc5e Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/411801 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17677 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-29rockchip/rk3399: display: Retry edp initialization if it failsLin Huang
We found that sometimes the edp doesn't get the edid or that video config fails on kevin after a reboot. Now we will retry 3 times to initialize it if there are errors. BRANCH=gru BUG=chrome-os-partner:60150 TEST=reboot kevin, the edp initialization error is no longer seen. Change-Id: I96e20e526294fbc856fbdffcbd63accdc7371ef6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 28c57a6e5b89c7b3a96204ec19a080067460544a Original-Change-Id: I1382cdf4119fc4eeae5c2b36485030e3a38c2d91 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/412622 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17626 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-22spi: Clean up SPI flash driver interfaceFurquan Shaikh
RW flag was added to spi_slave structure to get around a requirement on some AMD flash controllers that need to group together all spi volatile operations (write/erase). This rw flag is not a property or attribute of the SPI slave or controller. Thus, instead of saving it in spi_slave structure, clean up the SPI flash driver interface. This allows chipsets/mainboards (that require volatile operations to be grouped) to indicate beginning and end of such grouped operations. New user APIs are added to allow users to perform probe, read, write, erase, volatile group begin and end operations. Callbacks defined in spi_flash structure are expected to be used only by the SPI flash driver. Any chipset that requires grouping of volatile operations can select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and define callbacks for chipset_volatile_group_{begin,end}. spi_claim_bus/spi_release_bus calls have been removed from the SPI flash chip drivers which end up calling do_spi_flash_cmd since it already has required calls for claiming and releasing SPI bus before performing a read/write operation. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17462 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-17rockchip/rk3399: Change 933 DPLL to low jitter rateDerek Basehore
This changes the 933 DPLL rate to 928 which has low jitter. BRANCH=none BUG=chrome-os-partner:57845 TEST=boot kevin and run while true; do sleep 0.1; memtester 500K 1 > /dev/null; done for several hours Change-Id: I4d2a8871aaabe3b0a1a165c788af265c5f9e892c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 54ebf8763bb8193c4b36a5e86f0c625b176d31a6 Original-Change-Id: Iaa12bf67527b6d0e809657c513b8d1c66af25174 Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/404550 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17379 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-17rockchip/rk3399: Change PLL configuration to match Linux kernelJulius Werner
The Kevin project has been too smooth and boring for our tastes in the last last few weeks, so we've decided to stir the pot a little bit and reshuffle all our PLL settings at the last minute. The new settings match exactly what the Linux kernel expects on boot, so it doesn't need to reinitialize anything and risk a glitch. Naturally, changing PLL rates will affect child clocks, so this patch changes vop_aclk (192MHz -> 200MHz, 400MHz in the kernel), pmu_pclk (99MHz -> 96.57MHz) and i2c0_src (198MHz -> 338MHz, leading to an effective I2C0 change 399193Hz -> 398584Hz). BRANCH=gru BUG=chrome-os-partner:59139 TEST=Booted Kevin, sanity checking display and beep. Instrumented rockchip_rk3399_pll_set_params() in the kernel and confirmed that GPLL, PPLL and CPLL do not get reinitialized anymore (with additional kernel patch to ignore frac divider when it's not used). Also confirmed that /sys/kernel/debug/clk_summary now shows pclk_pmu_src 96571429 because the kernel doesn't even bother to reinitialize the divisor. Change-Id: Ib44d872a7b7f177fb2e60ccc6992f888835365eb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9b82056037be5a5aebf146784ffb246780013c96 Original-Change-Id: Ie112104035b01166217a8c5b5586972b4d7ca6ec Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/405785 Original-Commit-Ready: Xing Zheng <zhengxing@rock-chips.com> Original-Tested-by: Xing Zheng <zhengxing@rock-chips.com> Original-Reviewed-by: Xing Zheng <zhengxing@rock-chips.com> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/17378 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-14soc/rockchip: split edp_enable() functionLin Huang
To avoid garbage display in firmware on warm reset, we need to enable eDP display in depthcharge instead when the framebuffer is cleared. Therefore limit edp_enable() in coreboot to just configure eDP, and leave enabling the display to depthcharge. CQ-DEPEND=CL:402071 BUG=chrome-os-partner:58675 BRANCH=none TEST=Boot from kevin, and display work Change-Id: I9d937ead33ebba58e33e02fd73b80d6e11bb69aa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 38b0d18c3fae37dfccb18fe809f763b98703167c Original-Change-Id: Ibbc283a5892b98f4922f02fd67465fe2e1d01b71 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/402095 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17207 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-03rockchip/rk3399: sdram.c: Fix msch ddrconfig register errorLin Huang
Fix msch ddrconfig register write error. Also make sure that the row number configured in msch is equal to the row number configured in the DDR controller. This would not affect systems with 4GB of memory, but is needed for 2GB configurations. BUG=None BRANCH=None TEST=Boot from kevin Change-Id: Ic95b3371faec5b31c32b011c50e55e83d949e74d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dfa43d3d44839d9685b6393157f51b646e9996de Original-Change-Id: I0c95378bf937a245b7cdc0583c5d2ed1347f2a3e Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/399563 Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17208 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02rockchip/rk3399: display: Do not allocate framebuffer in corebootLin Huang
framebuffer address is dynamically chosen by libpayload now, so there's no need to configure it in coreboot. CQ-DEPEND=CL:401402 BUG=chrome-os-partner:58675 BRANCH=none TEST=Boot from kevin, dev screen is visible Change-Id: I9f1e581d5c63b3579b26be22ce5c8d1e71679f6f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b3b6675420592c30e1e0abc8f8e9dd6ed5abd04c Original-Change-Id: I7e3162f24a4dc426fe4e10d74865cf0042c80db5 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/401401 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17109 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02rockchip/rk3399: sdram: Reset system if switch to index1 failsLin Huang
Near the end of DDR initialization, the system switches to the index1 configuration. Sometimes this failed and a status bit that coreboot was waiting for was never set, hanging the system. Instead, give the system 100ms to reach the new configuration or reboot it, which generally fixes the issue. Also reset when training the index1 configuration fails. BUG=chrome-os-partner:57988 BRANCH=None TEST=The error condition now leads to a reboot of coreboot which recovers the system, instead of hanging. Change-Id: Icb4270369102ff7a4ce91b0677e04b4eb10f1204 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ca250d0628ea3b6b39d5131246eaba68637c5140 Original-Change-Id: Id6e8936d90e54b733ac327f8476d744b45639232 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/399681 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17106 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02rockchip/rk3399: sdram: Fix data training functionLin Huang
1. Update write leveling value to 0x200. When the wrdqs slave delay is changed to 0x200, the phase between the dqs and the clock is 0 degrees. The pcb layout can make sure the tDQSS timing is smaller than 0.25tck, so this value is useful for both higher and lower frequencies. 2. Disable read leveling for LPDDR3. The read leveling result is unreliable - the value is not in the middle of the read eye. To fix this, disable read leveling and fix the read DQSn slave delay setting for DQn to 0x080 (1/4 cycle delay of the input signal). BUG=None BRANCH=None TEST=Boot from kevin; Check by shmoo read eye and stability test, that the updated value of 0x80 is better. Change-Id: Ia72b601d9bf4e34ba1b0b4584b2c5c3ce9dafbd4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 37e8dfe783db3ce71aa026b4609ed0bfa16db06f Original-Change-Id: I2a5d40c0348449b2a7c609c1db65da4ed5f1c09f Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Jeff Chen <cym@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/396598 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://review.coreboot.org/17105 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02rockchip/rk3399: sdram: also prepare the index1 configurationLin Huang
To enable DDR Dynamic Voltage and Frequency Scaling (DVFS) we need to train alternative configurations first, so do the training and store the values. BUG=None BRANCH=None TEST=Boot from kevin Change-Id: I944a4b297a4ed6966893aa09553da88171307a42 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 94533ff3ba21bcb0ace00bedcf0cebb89a341be2 Original-Change-Id: I4a98bc0db5553d154fedb657e35b926a92aa80c7 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/386596 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17104 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02rockchip/rk3399: Reserve enough framebuffer memory for 32bpp hires panelsJulius Werner
Some of our RK3399 devices have panel resolutions as high as 2400x1600. With 16bpp that barely still fit into an 8MB framebuffer, but then we changed it to 32bpp for better image quality... Note that this is a band-aid. Coreboot-allocated framebuffers shouldn't be used at all on ARM64 devices, since libpayload is perfectly capable to dynamically allocate it with the right size based on EDID-information on this architecture. That will require some more elaborate work to be fixed with later patches. BRANCH=gru BUG=chrome-os-partner:58044 TEST=Warm-reboot Kevin on the dev screen, confirm that you don't see the lower half of the screen that overflowed our allocated framebuffer preserved from the last boot as soon as the backlight turns on. Change-Id: I00a63cfef35a8ee734543abbdb298344fb529283 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d2718efcacb50371624d9f6a3b586c298e8c2fec Original-Change-Id: Ia1fa28971c65d7d0639966e715f742309245172b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/399966 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/17108 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-25rockchip/rk3399: reset system if DDR init failsLin Huang
We found sdram may fail in pctl_cfg(), so we check the status in this function. If it exceeds 100ms still in this function, we will restart the system. We also found there are rare chances DDR training fails, so also restart system in that case. BUG=chrome-os-partner:57988 BRANCH=None TEST=coreboot resets on failure and eventually the system comes up Change-Id: Icc0688da028a8f4f81eafe36bbaa79fdf2bcea74 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 89e45f8352f62e19a203316330aba14ccc5c8b11 Original-Change-Id: If4e78983abcfdfe1e0e26847448d86169e598700 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/397439 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17045 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-18rk3399: display: Use edid_set_framebuffer_bits_per_pixel() helperJulius Werner
This refactoring was already carried into RK3288 with commit 6911219 (edid: Add helper function to calculate bits-per-pixel dependent values) but it seems that the code for RK3399 was copy&pasted from it too early to pick this up. Fix that so that future Rockchip SoCs can copy&paste the right thing. Change-Id: I5050c58d18db38fffabc7666e67a622d4a828590 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17050 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-10-08rockchip/rk3399: Add Type-C PHY initWilliam wu
Though we don't use Type-C PHY to support USB3 in firmware, we still need to initialize the Type-C PHY, and make sure the power state of pipe is always fixed to U2/P2. After this, we can force USB3 controller to work in USB2 only mode. BRANCH=none BUG=chrome-os-partner:56425 TEST=Go to recovery mode, plug a Type-C USB drive containing chrome OS image into both ports in all orientations, check if system can boot from USB. Change-Id: I95bb96ff27d4fecafb7b2b9e9dc2839b5c132654 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8ec98507845276119d8a9d5626934dedcb35f2dd Original-Change-Id: Ie3654cd1c1cb76b62aa9b247879b60cbecee0155 Original-Signed-off-by: William wu <wulf@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/391412 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16910 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07rockchip/rk3399: Actually remove big CPU initialization from bootblockJulius Werner
CL:377541 was supposed to remove the big CPU cluster initialization from rkclk_init() in the bootblock and move it to a more suitable place in ramstage. Except that next to all the code cleanup I did in that patch, I seem to have forgotten to actually remove that old code. Big thanks to Nico for spotting that in the upstream coreboot review. BRANCH=gru BUG=chrome-os-partner:54906 TEST=Booted Kevin. Change-Id: I09fe948b4587536802b42329b813177439e0804f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 77f9eaf0446b22adfca79d0adf8a0ecfd93c0040 Original-Change-Id: I13dab208225b7e43ad864f2f3cf51b3c104acd4b Original-Reported-by: Nico Huber <nico.h@gmx.de> Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/389236 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16769 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07rockchip/rk3399: select rank before triggering trainingDerek Basehore
This selects the rank to train before training is triggered. This is to prevent any race conditions with the hardware. BRANCH=none BUG=chrome-os-partner:56940 TEST=stressapptest -M 1536 -s 1000 Change-Id: I892bace414cf4495619d41bdaea0c4e91c1e29b3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8f2dd6f52978a9e54ddd2688eb68fd237aabfe2d Original-Change-Id: I4e7118d8509b59e391d0a254477b5390dfdd43a5 Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/387907 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Tested-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: 云平 汤 <typ@rock-chips.com> Reviewed-on: https://review.coreboot.org/16768 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07rockchip/rk3399: Improve dram stability when run at high frequencyLin Huang
There are two modifications in the driver: 1. Correctly set speeds based on DDR frequency. Control the speeds in the predriver circuits to reduce power. SPEED[1:0] 2'b00:less than 800Mbps(400MHz) 2b01 : 800Mbps(400MHz) to 1600Mbps(800MHz) 2b10 : 1600Mbsp(800MHz) to 2400Mbps(1200MHz) 2b11 : 3200Mbps and greater 2. Configure the number of cycles for the phy clock pll wait time after locking, based on the DDR config file. BRANCH=none BUG=chrome-os-partner:56940 TEST=do memtester on kevin board, and pass Change-Id: Iaf6da59c6c5c290867e0922a2a99de272f4c7bde Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 125cf8afac3a682d33896fe74a20ba1d498a3bd2 Original-Change-Id: Iabc17df37a701c4f052540c3c259f209a1db3c59 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/387428 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16722 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-10-06rockchip/rk3399: Configure USB3 controller to work in USB2 only modeLiangfeng Wu
In USB2 only mode, the Type-C PHY will be held in reset and only the USB2 logic of the USB3 OTG controller and PHY will be used over the USB2 pins on the Type-C connector to support Low, Full and High-speed USB operation. BRANCH=none BUG=chrome-os-partner:56425 TEST=Go to recovery mode, plug a Type-C USB drive containing chrome OS image into both ports in all orientations, check if system can boot from USB. Change-Id: Ic265c0c91c24f63b2f9c3106eb2bb277a589233b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a37ccc5b6019967483eac6b5a360d67bc3326e93 Original-Change-Id: I582f04f84eef447ff0ba691ce60e9461ed31cfad Original-Signed-off-by: Liangfeng Wu <wulf@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/385837 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16717 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06rockchip: rk3399: improve write leveling flowJianqun Xu
To improve sdram 800MHz and 933MHz stability, we need to modify write leveling flow to get the proper write leveling value. BUG=chrome-os-partner:56940 BRANCH=none TEST=Boot from kevin on 933MHz, and do stressapptest Change-Id: I5b24c93d4a57917fb9af7e5e2a95d8423ccbaa7e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d84bf25b3e5de373c7913e6d534a810cb984b3fd Original-Change-Id: I87efddf628c3683fcb85d6875e029cf3cbc482be Original-Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Original-Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/384292 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16716 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06rockchip/rk3399: Move TTB to the end of SRAMJulius Werner
We found that we may want to load some components of BL31 on the RK3399 into SRAM. As usual, these components may not overlap any coreboot regions still in use at that time, as is already statically checked by the check-ramstage-overlaps rule in Makefile.inc. On RK3399, the only such regions are TTB and STACK. This patch moves the TTB region back to the end of SRAM (right before STACK), so that a large contiguous region of SRAM before that remains usable for BL31. BRANCH=gru BUG=None TEST=Booted Kevin. Change-Id: I1689d0280d79bad805fea5fc3759c2ae3ba24915 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1d4c6c6f6cc0efe97d6962a81e309a1c040d1def Original-Change-Id: I37c94f2460ef63aec4526caabe58f35ae851bab0 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/384635 Original-Reviewed-by: Simon Glass <sjg@google.com> Reviewed-on: https://review.coreboot.org/16714 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06rockchip: spi: Add support for 16-bit APB readsSimon Glass
With a SPI clock above about 24MHz the APB cannot keep up when doing individual byte transfers. Adjust the driver to use 16-bit reads when it can, to remove this bottleneck. Any transaction which involves writing bytes still uses 8-bit transfers, to simplify the code. These are the transfers that are not time-critical since they tend to be small. The case that really matters is reading from SPI flash. In general we can use 16-bit reads anytime we are transferring an even number of bytes. If the code detects an odd number of bytes, it tries to perform the operation in two steps: once in 16-bit mode with an even number of bytes, and once in 8-bit mode for the final byte. This allow us to use 16-bit reads even if asked to transfer (for example) 0xf423 bytes. The limit on in_now and out_now is adjusted to 0xfffe to avoid an extra transfer when transferring ~>=64KB. CQ-DEPEND=CL:383232 BUG=chrome-os-partner:56556 BRANCH=none TEST=boot on gru and see that things still work correctly. I tested (with extra debugging) that the 16-bit case is being picked when it should be. Change-Id: If5effae9a84e4de06537fd594bedf7f01d6a9c88 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ec250b4931c7d99cc014e32ab597fca948299d08 Original-Change-Id: Idc5b7e5d82cdbdc1e8fe8b2d6da819edf2d5570c Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381312 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16712 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06rockchip: Correct and standardize clock divisor range assertionsJulius Werner
Some of the asserts for valid clock divisor ranges were off by one. This patch corrects them and writes them all in a consistent way. BRANCH=None BUG=None TEST=Booted Kevin. Change-Id: I81749408a40822100797f1734f3b88987d12d8d5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e09cdfde26700496aaa1fc41489f63a355e8a89d Original-Change-Id: I429edb99e2d5ff2302d9750e6569b3d21f5686fa Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381574 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/16704 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06rockchip/rk3399: Move big CPU cluster initialization into ramstageJulius Werner
This patch moves the big CPU cluster initialization on the RK3399 from the clock init bootblock function into ramstage. We're only really doing this to put the cluster into a sane state for the OS, we're never actually taking it out of reset ourselves... so there's no reason to do this so early. Also cleaned up the interface for rkclk_configure_cpu() a bit to make it more readable. BRANCH=None BUG=chrome-os-partner:54906 TEST=Booted Kevin. Change-Id: I568b891da0abb404760d120cef847737c1f9e3ec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bd7aa7ec3e6d211b17ed61419f80a818cee78919 Original-Change-Id: Ic3d01a51531683b53e17addf1942441663a8ea40 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/377541 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16698 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04rockchip: spi: Set rxd sample delay when using high speedSimon Glass
At higher SPI bus speeds the SPI RX value is not available in time for sampling at the normal time. Add a delay to ensure that we read the correct data. The value of 40ns is chosen arbitrarily. In my testing I can use a sample delay of 1 even at 24MHz. But since it is not necessary, I have left that case alone. It kicks in at 25MHz and up. BUG=chrome-os-partner:56556 BRANCH=none TEST=boot on gru and see no change at current speed Change-Id: I3ef335d9a532eaef1e76034bd02e185acf11176a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e9b620c47fc3e39211487507fadb8657afdebee7 Original-Change-Id: I65d66d752cbbbee4d02f475de23a52069a0e9782 Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381311 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Simon Glass <sjg@google.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16707 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-10-04rockchip/rk3399: Fix rkclk_init() to actually use PERILP1_PCLK_HZJulius Werner
This patch fixes a typo in the clock initialization code that caused the PERILP1_PCLK_HZ constant to be ignored and the clock to always run at the same speed as its parent (PERILP1_HCLK_HZ). Since we've done all our previous tests and validation with this bug, we should probably increase the value of the constant (that had not actually been used) to the value that we had been incorrectly using instead (which also makes effective SPI read times faster). BRANCH=None BUG=chrome-os-partner:56556 TEST=Booted Kevin. Change-Id: Ibeb08f5fe5e984a74e3f57e60c62d4bfb644b6ca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 06e605a5fcb9bdf13a3d301112380633b892fd4e Original-Change-Id: Icb5e079f53eb22b0dbf0ea4d1c2ff08688e3fa8e Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381031 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/16703 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04rockchip: Remove pulls for gpio_output(), clean up codeJulius Werner
Output GPIOs should never have a pull-up or pull-down resistor attached since they're actively driven. Since some GPIOs get initialized with a pull at power-on reset, we should explicitly overwrite that setting. Most other platforms do this on gpio_output, but Rockchip hadn't yet. Also, shuffle some code around to make things cleaner and allow for easier code reuse. BRANCH=None BUG=chrome-os-partner:52526 TEST=Booted Kevin. Change-Id: I1425d074ea1e90f4484e1e84a8002b057192c5f7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: df5b236bfd58b172435043c1cb792b917a4ec4ab Original-Change-Id: I044266d71ef8bd0518316ff72d829d1ca1e30f35 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/382531 Original-Reviewed-by: Simon Glass <sjg@google.com> Reviewed-on: https://review.coreboot.org/16710 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04rockchip/rk3399: Remove CONFIG_ARM64_A53_ERRATUM_843419Julius Werner
As far as I know, the Cortex-A53 cores in RK3399 are of a newer revision that is not affected by ARM erratum 843419. If it was, the workaround would also need to be enabled in libpayload and Chrome OS userspace, which it currently isn't. I assume this was just incorrectly copied over from another SoC and we can safely remove it. BRANCH=None BUG=chrome-os-partner:56700 TEST=Booted Kevin. Change-Id: I5b1534c954a6d985499b481738723cabbdc07253 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4891cc866583532ee3dcb1a5ad5b81670eb0743d Original-Change-Id: Iadb57428f8727ce0e563204723644e2c79e3007c Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376363 Original-Commit-Queue: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16702 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-20rockchip: spi: Improve SPI read efficiencySimon Glass
The SPI driver is quite slow at reading data. For example, with a 24MHz clock on gru it achieves a read speed of only 13.9Mbps. We can correct this by reading the status registers once, then reading as many bytes as are available before checking the status registers again. It seems likely that a status register read requires synchronizing with the SPI FIFO clock domain, which takes a while. BUG=chrome-os-partner:56556 BRANCH=none TEST=run on gru and see the speed increase from 13.920 Mbps to 24.712 Mbps Change-Id: I24aed0c9c6c5445634c4e056922afaee4e9a7b33 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 49c2fc20d7d7d703763e9b0a6f68313a349a84b9 Original-Change-Id: I42745f01f0fe069f6ae26d866004d36bb257e6b2 Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376945 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16582 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20gru: Add watchdog reset supportJulius Werner
This patch adds support to reboot the whole board after a hardware watchdog reset, to avoid the usual TPM issues. Work 100% equivalent to Veyron. From my tests it looks like both SRAM and PMUSRAM get preserved across warm reboots. I'm putting the WATCHDOG_TOMBSTONE into PMUSRAM since that makes it easier to deal with in coreboot (PMUSRAM is currently not mapped as cached, so we don't need to worry about flushing the results back before reboot). BRANCH=None BUG=chrome-os-partner:56600 TEST='stop daisydog; cat > /dev/watchdog', press CTRL+D, wait 30 seconds. Confirm that system reboots correctly without entering recovery and we get a HW watchdog event in the eventlog. Change-Id: I317266df40bbb221910017d1a6bdec6a1660a511 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3b8f3d064ad56d181191c1e1c98a73196cb8d098 Original-Change-Id: I17c5a801bef200d7592a315a955234bca11cf7a3 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/375562 Original-Commit-Queue: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16578 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20gru: Add USB 2.0 PHY tuning for KevinJulius Werner
This patch sets some magic number in magic undocumented registers that are rumored to make USB 2.0 signal integrity better on Kevin. I don't see any difference (unfortunately it doesn't solve the problems with long cables on my board), but I guess it doesn't hurt either way. BRANCH=None BUG=chrome-os-partner:56108,chrome-os-partner:54788 TEST=Booted Kevin with USB connected through Servo. Seems to have roughly the same failure rate as before. Change-Id: If31fb49f1ed7218b50f24e251e54c9400db72720 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 0c5c8f0f80ea1ebb042bcb91506a6100833e7e84 Original-Change-Id: Ifbd47bf6adb63a2ca5371c0b05c5ec27a0fe3195 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/370900 Original-Reviewed-by: Guenter Roeck <groeck@chromium.org> Original-Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-on: https://review.coreboot.org/16265 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-31rockchip/rk3399: Add pwm_regulator.c for pwm then ramp boot up cpuEric Gao
Before, we calculate the pwm duties for cpu cores and centerlogic by hand, adding pwm_regulator.c to handle this. The default pwm design min/max voltage may be different between revs. With the pwm regulator, this patch changes the little cpu frequency from 600M to 1512M, and raises CPU voltage to 1.2V correspondingly. This also means we decide to drop the ES1 because it may fail to bootup with 1.5G ~ 1.2v. BRANCH=none BUG=chrome-os-partner:54376,chrome-os-partner:54862 TEST=Bootup on kevin board Change-Id: Id04c176bddfb9cdf3d25b65736e40249a85f6aa1 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: ee4365c787ec523b7ee1028ea100dcfbb331b3a9 Original-Change-Id: Ide75bbd92d1cbb14f934baeec0e38862bc08402b Original-Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/364410 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16368 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-31rockchip/rk3399: Move romstage.c to mainboard/gruShunqian Zheng
The romstage.c is more board related than soc specific, like setting the pwm regulators, so moving it to mainboard/gru. BRANCH=none BUG=chrome-os-partner:54819 TEST=Bootup on kevin board Change-Id: I83c6cde9f451480e47e2b4b549cedf65b345134c Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 35feeb07131a6a9de4adde035236987391833474 Original-Change-Id: If2bf245302eb4fb20bb089c1b3ffa03909722443 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/375398 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16367 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-27rockchip/rk3399: Enable ramstage compression, shuffle around memlayoutJulius Werner
Since we now have so much more room for activities in our romstage SRAM section, we can easily fit the LZMA decompressor to enable ramstage compression. Also shuffle around memlayout sections a little more to make use of unused space, and balance out leftover memory so that all sections that might need future expansion have a reasonable amount. Change-Id: I47f2d03e520fc3103ef04257b4ba7e93874b8956 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16334 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-27gru: Make SDRAM parameters individual struct files in CBFSJulius Werner
This patch changes Gru SDRAM parameters from structures that just get compiled into the romstage to individual CBFS files. This allows us to only load the parameter set we need for the board we're booting from flash, which reduces our boot time and the SRAM memory footprint required to hold the romstage. TEST=Booted Kevin. Change-Id: Ie88a515cbdb19a794ca0a230a56bcc82bed1e550 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16274 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-19rockchip/rk3399 & gru/kevin: support sdram 933MHz on kevinLin Huang
We should be running faster. Faster = better. BRANCH=None BUG=chrome-os-partner:54873 TEST=Boot; stressapptest -M 1028 -s 10000 Change-Id: I7f855960af3142efb71cf9c15edd1da66084e9d8 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 51bfd2abb1aba839bd0b5b85e9e918f3cc4fd94d Original-Change-Id: Iec9343763c1a5a5344959b6e8c4dee8079cf8a20 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/362822 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16241 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-17google/gru: Add new PWM regulator duty numbers for revision 6Julius Werner
We're changing the PWM regulator bounds on Kevin from rev6 onwards, so we'll need to use different duty cycle values for them. We really want a proper PWM regulator driver that can calculate these values automatically from voltages, but until we have that this patch just hardcodes the new numbers in. (Yes, this is a patch for the mainboard/google/gru board family that only touches a file from the rockchip/rk3399 SoC. That too is something that'll be fixed up in a later CL.) BRANCH=None BUG=chrome-os-partner:54888 TEST=Booted Kevin rev4 (for whatever that's worth...). Change-Id: Ibb6ab5c6517d83ffb5e32cb17d0de33e8ec10293 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 4cb2a939295e2b6443c5dbd3374982224322304b Original-Change-Id: I8757cc54f2478d20bb948a1a0a7398b0404a7b1f Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/368410 Original-Commit-Ready: Dan Shi <dshi@chromium.org> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16235 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-16Revert "rockchip: rk3399: enable sdhci clk for emmc"Shunqian Zheng
This reverts commit 462e1413 ("rockchip: rk3399: enable sdhci clk for emmc") Enabling this clock in coreboot is no longer needed as it's handled in the kernel driver now. BUG=chrome-os-partner:52873 TEST=boot from usb/sdcard and check there is /dev/mmcblk0 BRANCH=none Change-Id: I92cf51f175fe56a09ab9329b29a27c77ef4328e1 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 5707d1269a253dabf825be120d1f9348ffaab6d0 Original-Change-Id: I8bca870c663d8ce8fac5daaaaf8225489f22ed13 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/367421 Original-Commit-Ready: Brian Norris <briannorris@chromium.org> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16152 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-11rockchip/rk3399: Add code to neuter Type-C PHY for firmware USBJulius Werner
The Rockchip RK3399 integrates a USB Type-C PHY in charge of things like SuperSpeed line muxing for rotated cable orientations in the SoC. While fancy, this is very complicated and we don't want to implement support for the whole thing in firmware. The USB Type-C standard has intentionally been designed in a way that the USB 2.0 (HighSpeed) lines always "just work" in any orientation (by just shorting different pins in the connector together) so that simple use cases like ours can get basic USB functionality without much hassle. However, a semi-configured Type-C PHY can confuse USB 3.0 capable devices into thinking we're actually supporting SuperSpeed, and fail at that rather than establishing a reliable HighSpeed connection. This patch sets enough bits in the Type-C PHY to electrically isolate the SuperSpeed lines from the connector so that the connected device isn't going to get any fancy ideas and reliably falls back to USB 2.0. Also clean up the rest of the USB code while we're at it: avoid writing a few bits that are already in the right state from their reset values anyway, or reading values whose content we already know for this SoC. Rename the USB controllers to the name actually used in the Rockchip documentation (USB OTGx) rather than the name blindly copied from Exynos code (USB DRDx). BRANCH=None BUG=chrome-os-partner:54621 TEST=Plug a USB 3.0 Patriot Memory stick into both ports in all orientations, observe how it gets reliably detected now (safe for some known hardware issues on my board). Change-Id: Ifce6bcddd69f2e8f2e2a2f48faf65551e084da1e Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: c526906f998bf66067d3addb8b3d3a126c188b1e Original-Change-Id: Ie80a201a58764c4d851fe4a5098a5acfc4bcebdf Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/366160 Original-Reviewed-by: liangfeng wu <wulf@rock-chips.com> Original-Reviewed-by: Shelley Chen <shchen@chromium.org> Original-Reviewed-by: <515506667@qq.com> Reviewed-on: https://review.coreboot.org/16125 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-10rockchip/common: Set weekday to unknown in rtc_get()Martin Roth
Prior to this patch, time->wday was not being initialized in rtc_get(), but was still being used by rtc_display() to print a day. Set to -1 which gets printed as "unknown ". Fixes coverity issue 1357459 - Uninitialized scalar variable Change-Id: Idecb7968f854df997b58a342e1a06a879f299394 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15899 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-08-09rockchip/rk3399: sdram: correct read obs and set DQS driver registerLin Huang
We were using the wrong register when reading the obs value and setting the DQS driver. This did not affect LPDDR3 performance, but still needs to be fixed. BUG=none BRANCH=none TEST=boot from kevin Change-Id: I144f575e27fba11872a8c5463ab1e2986f385ede Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 98221e6b03fc09cbf62af29a270e7a8aa8dfb986 Original-Change-Id: Ie179f9a2955c5712951d40b3ada9c14a51c09c8d Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/363170 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16052 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-03google/gru: Add code to support I2C TPM for KevinJulius Werner
Coming Kevin revisions will switch back to an I2C TPM. This patch adds the required configuration options and code to support that. Since the TPM type can currently only be changed at compile time, we can no longer support older Kevins with the same image. In order to build for Kevin revisions < 5, you have to explicitly override the CONFIG_GRU_HAS_TPM2. BRANCH=None BUG=chrome-os-partner:55523 TEST=Compiled both Kevin and Gru, confirmed that bootblock and verstage binary had the appropriate code differences. Change-Id: I1b2abe0f331eb103eb0a84f773ee7521d31ae5d8 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3245bff937154f0f9f39894de9c98a75631d59d9 Original-Change-Id: I81a15c9fb037a7ca2d69818e46cbb4f9a5ae1989 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/364222 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16029 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-07-28rockchip/rk3399: sdram: correct controller vref settingLin Huang
When enabling the controller ODT, the controller vref needs to correspond with the ODT value and DQ drive strength. BRANCH=none BUG=chrome-os-partner:54871 TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass Original-Commit-Id: a7251c72b87d9f149b68d086c3252f1c668e0e80 Original-Change-Id: I7e54b3473f68a382208a0fb0b0600552fe6390ad Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/358762 Original-Commit-Ready: Dan Shi <dshi@chromium.org> Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Squashed with: rockchip/rk3399: Halt if we get an invalid odt or drv value When we were pushing the updated sdram.c to coreboot.org, the compiler there found that we were not initializing vref_value_dq in all code possible code paths. This patch updates those code paths to halt the system. Branch=none Bug=none Test=Built with coreboot.org toolchain and verified that the compile errors were gone. Change-Id: I0ad4207dc976236d64b6cdda58d10bcfbe1fde11 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362726 Reviewed-by: Julius Werner <jwerner@chromium.org> Change-Id: I22a0cef6f12d9aae2ea4dcb99e7ebdd788f2cdd1 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/15812 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-07-25rockchip/rk3399: set CA drive strength to 48ohmsLin Huang
As shown in testing, if CA use 34.3ohms drive strength, it leads to an overshoot. To fix this, change the drive strength to 48 ohms. BRANCH=none BUG=chrome-os-partner:54871 TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass Change-Id: I8666474fc18391da14a3338611f962f2f08f36d0 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: fbc1c13f9ab808fc907b2e3f9bde1d09f92980f1 Original-Change-Id: I231f5b1bd45ff262686fbacbaf119a8a57fad27b Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/358761 Original-Commit-Ready: Dan Shi <dshi@chromium.org> Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15811 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19rockchip/rk3399: Remove unused variableMartin Roth
The 'speed' variable isn't being used after refactoring. Change-Id: Id27a920c61b2bba18d391a7bfefe570235402dec Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/15749 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-18gru: implement hw reset functionVadim Bendebury
Asserting this GPIO will send a signal to the EC to trigger a reset for the AP and the CR50. BRANCH=none BUG=chrome-os-partner:55252 TEST=the device now reboots when it needs to switch between different boot modes instead of hanging with "failed to reboot" message. Change-Id: I8d168e313b6983c96c80f7ad6d70bb84c1ec1d9c Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 83a4c8ff68ab24a103f2166e948eb23624ea97f7 Original-Change-Id: Idfd20977cf3682bd8933f89e8eec53005e55864e Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/360238 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15718 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-15rockchip/rk3399: extend romstage rangeLin Huang
rk3399 sdram size is 192K, and there still some unused space. We need more romstage space to include the sdram config, so extend the romstage range. BRANCH=none BUG=chrome-os-partner:54871 TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass Change-Id: Ib827345fe646e985773e6ce3e98ac3f64317fffb Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 626ab15bb4ebb004d5294b948bbdecc77a72a484 Original-Change-Id: Ib5aa1e1b942cde8d9476773f5a84ac70bb830c80 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/359092 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15660 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15rockchip/rk3399: set kevin rev3 pwm regulator initial value to 0.95vLin Huang
kevin rev3 pwm regulator ripple is still not great, especially for center logic. To make sdram at 800MHz stable, raise it to 0.95v. BRANCH=none BUG=chrome-os-partner:54871 TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass Change-Id: If4a15eb7398eea8214cb58422bca7cfb5f4a051a Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: d29bc581effb0008eb196685aa22dd65b5d478a5 Original-Change-Id: Ideec9c3ab2f919af732719ed2f6a702068d99c8f Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/359130 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15659 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15rockchip/rk3399: Remove empty function in sdram.cDerek Basehore
This removes an empty function for sdram training. If it's needed later, we can always add it back. BRANCH=none BUG=none TEST=build and boot firmware for kevin/gru Change-Id: Id526ef86cf5044894a1a736cc39f10d32f49c072 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3e93461b96bfadc08bf0b46cf99052d9cdffa422 Original-Change-Id: I6bf77d2f81719c68cd78722c3fe9ae547ea1e79c Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/354164 Original-Reviewed-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/15657 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15rockchip/rk3399: Change copy_to_reg arg typeDerek Basehore
This changes the src arg for copy_to_reg to a const u32 * instead of a u32 * in sdram.c. BRANCH=none BUG=none TEST=emerge-gru coreboot Change-Id: I80f49258b2f8102f0d988fec85b8038a00e18a34 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: e0342e5c0181bf65ae78aa9518b0d6bd6cb1d5ec Original-Change-Id: I362727f1dbe6726bf3240f9219c394786162a1a0 Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/354163 Original-Reviewed-by: Martin Roth <martinroth@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15656 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 04:25:29 +0000