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2020-04-06soc/rockchip: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I773cc57197b29fd3f4522aece4c83b3dc9e646e0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-05Drop explicit NULL initializations from `device_operations`Elyes HAOUAS
Unmentioned fields are initialized with 0 (or NULL) implicitly. Beside that, the struct has grown over the years. There are too many optional fields to list them all. Change-Id: Icb9e14c58153d7c14817bcde148e86e977666e4b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40126 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-03-10src: Remove unneeded 'include <arch/cache.h>'Elyes HAOUAS
Change-Id: I6374bc2d397800d574c7a0cc44079c09394a0673 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37984 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24soc/rockchip: Fix typosElyes HAOUAS
Change-Id: I85ccb9e1458340bd5bc2a0eb9abed8d0eeb2fe65 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-12-20src: Replace min/max() with MIN/MAX()Elyes HAOUAS
Change-Id: I63b95144f2022685c60a1bd6de5af3c1f059992e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37828 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19src/soc/rockchip: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: Ifdfd37a59273c3647802bc7cb9774e61f90fe441 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37381 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-04Change all clrsetbits_leXX() to clrsetbitsXX()Julius Werner
This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-11-19lib/fmap: Disable pre-RAM cache for FSP 1.0Julius Werner
Due to the way CAR teardown is handled in FSP 1.0, the results of car_get_var_ptr() aren't always reliable, which can break things when running with FMAP cache. It might be possible to fix this but would make the code rather complicated, so let's just disable the feature on these platforms and hope they die out soon. Also allow this option to be used by platforms that don't have space for the cache and want to save a little more code. Change-Id: I7ffb1b8b08a7ca3fe8d53dc827e2c8521da064c7 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-14rockchip/rk3288: Split free SRAM more evenly between stagesJulius Werner
When CB:33068 disabled the bootblock console on RK3288, it saved a whooping 7K of SRAM, but it didn't readjust the stage boundaries to spread that bounty evenly. This patch moves 4K of free space from the bootblock to verstage/romstage to allow for future expansion. Change-Id: I68a09ba80bde0d4f17fba1f7b38c63b7cf2a4672 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-14lib/fmap: Add optional pre-RAM cacheJulius Werner
This patch adds an optional pre-RAM cache for the FMAP which most platforms should be able to use, complementing the recently added post-RAM FMAP cache in CBMEM. vboot systems currently read the FMAP about half a dozen times from flash in verstage, which will all be coalesced into a single read with this patch. It will also help future vboot improvements since when FMAP reads become "free" vboot doesn't need to keep track of so much information separately. In order to make sure we have a single, well-defined point where the new cache is first initialized, eliminate the build-time hardcoding of the CBFS section offsets, so that all CBFS accesses explicitly read the FMAP. Add FMAP_CACHEs to all platforms that can afford it (other than the RISC-V things where I have no idea how they work), trying to take the space from things that look like they were oversized anyway (pre-RAM consoles and CBFS caches). Change-Id: I2820436776ef620bdc4481b5cd4b6957764248ea Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Joel Kitching <kitching@google.com>
2019-11-11rockchip/rk3288: Bump verstage size a little moreJulius Werner
RK3288 is running out of space again. I believe reducing the CBFS cache size this much should be safe. I don't really care to test it either though. We should probably just deprecate that SoC at some point, it's just causing too much pain. Change-Id: Id8f971606a7a183d3e9af8bbb1b353e518ec24c8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Joel Kitching <kitching@google.com>
2019-11-03arch/arm64: Pass cbmem_top to ramstage via calling argumentArthur Heymans
This solution is very generic and can in principle be implemented on all arch/soc. Currently the old infrastructure to pass on information from romstage to ramstage is left in place and will be removed in a follow-up commit. Nvidia Tegra will be handled in a separate patch because it has a custom ramstage entry. Instead trying to figure out which files can be removed from stages and which cbmem_top implementations need with preprocessor, rename all cbmem_top implementation to cbmem_top_romstage. Mechanisms set in place to pass on information from rom- to ram-stage will be replaced in a followup commit. Change-Id: I86cdc5c2fac76797732a3a3398f50c4d1ff6647a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-03arch/arm: Pass cbmem_top to ramstage via calling argumentArthur Heymans
This solution is very generic and can in principle be implemented on all arch/soc. Instead trying to figure out which files can be removed from stages and which cbmem_top implementations need with preprocessor, rename all cbmem_top implementation to cbmem_top_romstage. Mechanisms set in place to pass on information from rom- to ram-stage will be placed in a followup commit. Change-Id: If31f0f1de17ffc92c9397f32b26db25aff4b7cab Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-01lib/cbmem_top: Add a common cbmem_top implementationArthur Heymans
This adds a common cbmem_top implementation to all coreboot target. In romstage a static variable will be used to cache the result of cbmem_top_romstage. In ramstage if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is set a global variable needs to be populated by the stage entry with the value passed via the calling arguments. if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is not set the same implementation as will be used as in romstage. Change-Id: Ie767542ee25483acc9a56785ce20a885e9a63098 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-27src/soc: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I9c1228d3f9e7a12fe30c48e3b1f143520fed875c Reviewed-on: https://review.coreboot.org/c/coreboot/+/36332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-14arm64: Uprev Arm TF and adjust to BL31 parameter changesJulius Werner
This patch uprevs the Arm Trusted Firmware submodule to the new upstream master (commit 42cdeb930). Arm Trusted Firmware unified a bunch of stuff related to BL31 handoff parameters across platforms which involved changing a few names around. This patch syncs coreboot back up with that. They also made header changes that now allow us to directly include all the headers we need (in a safer and cleaner way than before), so we can get rid of some structure definitions that were duplicated. Since the version of entry point info parameters we have been using has been deprecated in Trusted Firmware, this patch switches to the new version 2 parameter format. NOTE: This may or may not stop Cavium from booting with the current pinned Trusted Firmware blob. Cavium maintainers are still evaluating whether to fix that later or drop the platform entirely. Tested on GOOGLE_KEVIN (rk3399). Change-Id: I0ed32bce5585ce191736f0ff2e5a94a9d2b2cc28 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-30arm64: Rename arm_tf.c/h to bl31.c/hJulius Werner
This patch renames arm_tf.c and arm_tf.h to bl31.c and bl31.h, respectively. That name is closer to the terminology used in most functions related to Trusted Firmware, and it removes the annoying auto-completion clash between arm64/arm_tf.c and arm64/armv8. Change-Id: I2741e2bce9d079b1025f82ecb3bb78a02fe39ed5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-22rockchip: Use new buffer_to/from_fifo32(_prefix) helpersJulius Werner
This patch changes the Rockchip SPI and I2C drivers to use the new buffer_from_fifo32()/buffer_to_fifo32_prefix() helpers when accessing their FIFOs (mostly just to demonstrate that/how the helpers work). Change-Id: Ifcf37c6d56f949f620c347df05439b05c3b8d77d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-21vboot: update vboot2 functions to use new vb2_error_tJoel Kitching
To make explicit when vboot2 error codes should be returned, use the new vb2_error_t type on all functions which return VB2_ERROR_* constants. Additionally, add required vboot submodule commit id e6700f4c: 2019-07-31 14:12:30 +0800 - (vboot: update vboot2 functions to use new vb2_error_t) NOTE: This patch was merged separately on the Chromium tree: https://chromium-review.googlesource.com/c/1728499 BUG=b:124141368, chromium:988410 TEST=make clean && make test-abuild BRANCH=none Change-Id: I804c2b407e496d0c8eb9833be629b7c40118415c Signed-off-by: Joel Kitching <kitching@google.com> Cq-Depend: chromium:1728292 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-10src: Include <stdint.h> instead of <inttypes.h>Jacob Garber
The <inttypes.h> header currently does nothing but include the definitions from <stdint.h>, so let's #include that directly instead. Change-Id: I9d83ad37d0d7300a093001596ce3f0b3830c5701 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-25soc/{qualcomm,rockchip}: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Also including <types.h>, is supposed to provide stdint and stddef. Change-Id: Iab605f6be4a48c10fa5aae7a1222520149ad1392 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-25soc/rockchip/rk3399: Use 64 bits in multiplicationJacob Garber
This multiplication is of the form u64 = u32 * u32. Despite being stored in a 64 bit variable, the intermediate value is still calculated using 32 bit math, which could possibly overflow. Cast one of the variables to a u64 to ensure it uses 64 bit math instead to avoid this. Change-Id: Ib08624812e933fdca5a51150ab36d3be49383326 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1375443 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-19src: Make implicit fall throughs explicitJacob Garber
Implicit fall throughs are a perpetual source of bugs and Coverity Scan issues, so let's squash them once and for all. GCC can flag implicit fall throughs using the -Wimplicit-fallthrough warning, and this should ensure no more enter the code base. However, many fall throughs are intentional, and we can use the following comment style to have GCC suppress the warning. switch (x) { case 1: y += 1; /* fall through */ case 2: y += 2; /* fall through - but this time with an explanation */ default: y += 3; } This patch adds comments for all remaining intentional fall throughs, and tweaks some existing fall through comments to fit the syntax that GCC expects. Change-Id: I1d75637a434a955a58d166ad203e49620d7395ed Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-17soc/rockchip/rk3288: Add fall through commentJacob Garber
Judging from the state machine on page 281 of the Rockchip RK3288 Technical Reference Manual (Rev 1.0 - Jun 2015), the fall through from the INIT_MEM -> CONF states is intentional, since that is the only way to get to the ACCESS state. Add a comment to explain this. Change-Id: I1d0cfea07211c54d6a906f5a7481c2c760f8ef0d Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1291959 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-13soc/rockchip/rk3288/include/soc: Add missing include <types.h>Elyes HAOUAS
Change-Id: Ibde48d7cff582c91f55ad5f1328aac64d018b3c5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34235 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-09arch/non-x86: Flip HAVE_MONOTONIC_TIMER defaultKyösti Mälkki
Also remove allwinner/a10 dummy monotonic_timer implementation. Change-Id: I9dfa9b92dc63375465e3bb87b73eeefad601c810 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-03vboot: Use CONFIG_VBOOT_MIGRATE_WORKING_DATA on all platformsJulius Werner
When we added CONFIG_VBOOT_MIGRATE_WORKING_DATA, the idea was that on some Arm platforms the original working data buffer was in SRAM, which stays accessbile for the whole runtime of the system. There is no reason to migrate it into CBMEM on those platforms because ramstage and the payload could continue to access it in SRAM. Now that we've had a couple of months of experience with this option, we found that most of our Arm platforms have some issue that requires migrating anyway, because BL31 often claims SRAM for itself and makes it inaccessible to the payload. On the remaining platforms, accessing SRAM from the payload is possible but still an issue, because libpayload doesn't have enough memory layout information to set up proper page tables for it, so we're accessing it uncached and at risk of alignment errors. Rather than having to figure out how to map the right SRAM range for every platform in the payload, let's just get rid of the option. memcpy()ing 12KB isn't worth this much hassle. Change-Id: I1b94e01c998f723c8950be4d12cc8f02b363a1bf Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-05-30soc/rockchip/rk3288: Disable bootblock consolePatrick Georgi
Bootblock space is tight on this SoC and recent changes increased it ever so slightly to make this a problem. Since the bootblock is well-tested, we can get by without console. Change-Id: I7496a3e313b2c6ee6fb3c4671eac64376d84e0dc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33068 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29src/soc: Add missing 'include <types.h>'Elyes HAOUAS
<types.h> is supposed to provide <stdint.h> and <stddef.h>. When <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: I2db0a647bc657a3626cb5e78f23e9198e290261a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-06Fix code that would trip -Wtype-limitsJulius Werner
This patch fixes up all code that would throw a -Wtype-limits warning. This sometimes involves eliminating unnecessary checks, adding a few odd but harmless casts or just pragma'ing out the warning for a whole file -- I tried to find the path of least resistance. I think the overall benefit of the warning outweighs the occasional weirdness. Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32537 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-30rockchip: rk3399: increase memory for fit payload.Marty E. Plummer
Increase ramstage to 2M, required to actually embed the 7.2mb uImage into the coreboot.rom, increase the postram cbfs cache in order for the fit image to be loadable (without this increase the fit payload is found but not loaded) Change-Id: Iee0ed9f7958588ceda54bb32253c84cac68abea2 Signed-off-by: Marty E. Plummer <hanetzer@startmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-30vboot: refactor OPROM codeJoel Kitching
The name OPROM is somewhat inaccurate, since other steps to bring up display and graphics are needed depending on mainboard/SoC. This patch cleans up OPROM code nomenclature, and works towards the goal of deprecating vboot1: * Rename CONFIG_VBOOT_OPROM_MATTERS to CONFIG_VBOOT_MUST_REQUEST_DISPLAY and clarify Kconfig description * Remove function vboot_handoff_skip_display_init * Remove use of the VbInit oflag VB_INIT_OUT_ENABLE_DISPLAY * Add |flags| field to vboot_working_data struct * Create VBOOT_FLAG_DISPLAY_REQUESTED and set in vboot_handoff BUG=b:124141368, b:124192753, chromium:948529 TEST=make clean && make test-abuild TEST=build and flash eve device; attempt loading dev/rec modes BRANCH=none Change-Id: Idf111a533c3953448b4b9084885a9a65a2432a8b Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-29rockchip/rk3399: Select VBOOT_MIGRATE_WORKING_DATAJulius Werner
Trusted Firmware places some components in SRAM on RK3399 and therefore restricts accesses to SRAM to the secure world. This makes the vboot working data inaccessible to normal world payloads, so we need to migrate it into CBMEM. Change-Id: Ic7c95790f2f118ccbdd897550f13b5f987bdd831 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2019-04-23src: include <assert.h> when appropriateElyes HAOUAS
Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Guckian
2019-04-23src: Add missing include 'console.h'Elyes HAOUAS
Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-06src: Use include <delay.h> when appropriateElyes HAOUAS
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-19rockchip/rk3399: Remove obsolete BL31 resource reservationJulius Werner
RK3399 SoC code still manually excludes the BL31 region from the memory map, even though that is now automatically done with the BL31() memlayout region. CB:31123 and CB:31538 just forgot to remove this line. The resulting memory map stays the same. Change-Id: I87458fa09f437b038af10e0fd9d76ef6d9394bc5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ting Shen <phoenixshen@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-07src: Drop unused include <timestamp.h>Elyes HAOUAS
Change-Id: I7e181111cd1b837382929071a350b94c3afc1aaa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-22symbols.h: Add macro to define memlayout region symbolsJulius Werner
When <symbols.h> was first introduced, it only declared a handful of regions and we didn't expect that too many architectures and platforms would need to add their own later. However, our amount of platforms has greatly expanded since, and with them the need for more special memory regions. The amount of code duplication is starting to get unsightly, and platforms keep defining their own <soc/symbols.h> files that need this as well. This patch adds another macro to cut down the definition boilerplate. Unfortunately, macros cannot define other macros when they're called, so referring to region sizes as _name_size doesn't work anymore. This patch replaces the scheme with REGION_SIZE(name). Not touching the regions in the x86-specific <arch/symbols.h> yet since they don't follow the standard _region/_eregion naming scheme. They can be converted later if desired. Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/31539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-02-22rockchip/rk3399: Fix BL31 bootmem regionsJulius Werner
The BL31 on RK3399 is split into multiple segments... the majority goes into DRAM, but small parts must be put into SRAM and PMUSRAM. With CB:31123 only the DRAM part was added to memlayout, so the SRAM parts will not be correctly marked in bootmem and BL31 loading fails the selfload check. This patch adds the remaining regions to fix the problem. Change-Id: Ia0597216c08512c47361a1dc0beb34d022a8994f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/31538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ting Shen <phoenixshen@google.com>
2019-02-05bootmem: add new memory type for BL31Ting Shen
After CL:31122, we can finally define a memory type specific for BL31, to make sure BL31 is not loaded on other reserved area. Change-Id: Idbd9a7fe4b12af23de1519892936d8d88a000e2c Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://review.coreboot.org/c/31123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-28src: Don't use a #defines like Kconfig symbolsElyes HAOUAS
This is spotted using ./util/lint/kconfig_lint To work around the issue, rename the prefix from `CONFIG_` to `CONF_`. Change-Id: Ia31aed366bf768ab167ed5f8595bee8234aac46b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-14console: Change BOOTBLOCK_CONSOLE default to `y`Nico Huber
Invert the default instead of selecting it everywhere. Restores the ability to use its Kconfig prompt. Beside Qemu targets, the only platforms that didn't select it seem to be samsung/exynos5420, intel/cannonlake, and intel/icelake. The latter two were about to be patched anyway. Change-Id: I7c5b671b7dddb5c6535c97c2cbb5f5053909dc64 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30891 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30security/vboot: Fix remaining measured boot issuesPhilipp Deppenwiese
Makes vboot measured boot mode available for all boards. * Increase Tegra210 and Rockchip3228 SRAM for romstage/verstage. * Add missing files for Intel apollolake and AMD stoneyridge as TPM driver target. Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/29840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-29src: Remove duplicated round up functionElyes HAOUAS
This removes CEIL_DIV and div_round_up() altogether and replace it by DIV_ROUND_UP defined in commonlib/helpers.h. Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-21(console,drivers/uart)/Kconfig: Fix dependenciesNico Huber
The dependencies of CONSOLE_SERIAL and DRIVERS_UART were somehow backwards. Fix that. Now, CONSOLE_SERIAL depends on DRIVERS_UART, because it's using its interface. The individual UART drivers select DRIVERS_UART, because they implement the interface and depend on the common UART code. Some guards had to be fixed (using CONSOLE_SERIAL now instead of DRIVERS_UART). Some other guards that were only about compilation of units were removed. We want to build test as much as possible, right? Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-16src: Remove unneeded include <cbmem.h>Elyes HAOUAS
Change-Id: I89e03b6def5c78415bf73baba55941953a70d8de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29302 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16src: Remove unneeded include <cbfs.h>Elyes HAOUAS
Change-Id: Iab0bd1c5482331a0c048a05ab806bf5c4dbda780 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29303 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16src: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-30src: Add missing include <stdint.h>Elyes HAOUAS
Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29312 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-22soc/rockchip/rk3399: Convert to `board_reset()`Nico Huber
Change-Id: Id07e1c7fbd35393ffafda53fc7a15ec0e157d075 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-10drivers/i2c: Add i2c TPM support for different stagesPhilipp Deppenwiese
Change-Id: Ib0839933f8b59f0c87cdda4e5374828bd6f1099f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/23759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-08-10src: Fix typoElyes HAOUAS
Change-Id: I689c5663ef59861f79b68220abd146144f7618de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/soc: Fix typoElyes HAOUAS
Change-Id: I8053d0f0863aa4d93692487f1ca802195c2d475f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09rk3288: Dig up two more KB of SRAM from under the couch cushionsJulius Werner
RK3288 has always been notoriously low on SRAM, to the point where its boards have less than 100 bytes left in both their bootblock/verstage sections. This becomes a problem every time we try to add a tiny amount of code to common coreboot interfaces that are included in them. This patch manages to add another KB to each, one from the CBMEM console (which now might get cut off a bit, but that's life) and one by moving the TTB_SUBTABLES to PMUSRAM. PMUSRAM is a weird world where write accesses must always be exactly 4 bytes long or they hang the CPU, so we mostly ignore it... but thankfully, page table entries are exactly 4 bytes long and that's the only thing we write to this region, so it works out in this case. Change-Id: I5aecd66db40b3f52299b270322b8c8784dbe7e6f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-04src/soc: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Ia024fb418f02d90c38b9a35ff819c607b9ac4965 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04soc/rockchip: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Idf47ea3b29c3fab7256d7a6722c7978594001d8d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-22src: Remove non-ascii charactersMartin Roth
Change-Id: Iedb78e24a286a51830c85724af0179995ed553be Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-22rk3399: Enable bootblock compressionJulius Werner
This patch enables the new bootblock compression feature on RK3399, which requires moving MMU initialization into the decompressor stage and linking the decompressor (rather than the bootblock) into the entry point jumped to by the masked ROM. RK3399's masked ROM seems to be using a bitbang SPI driver to load us (very long pauses between clocking in each byte), with an effective data rate of about 1Mbit. Bootblock loading time (as measured on a SPI analyzer) is reduced by almost 100ms (about a third), while the decompression time is trivial (under 1ms). Change-Id: I48967ca5bb51cc4481d69dbacb4ca3c6b96cccea Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-03spi: Add helper functions for bit-bangingJulius Werner
Sometimes when bringing up a new board it can take a while until you have all the peripheral drivers ready. For those cases it is nice to be able to bitbang certain protocols so that you can already get further in the boot flow while those drivers are still being worked on. We already have this support for I2C, but it would be nice to have something for SPI as well, since without SPI you're not going to boot very far. This patch adds a couple of helper functions that platforms can use to implement bit-banging SPI with minimal effort. It also adds a proof of concept implementation using the RK3399. Change-Id: Ie3551f51cc9a9f8bf3a47fd5cea6d9c064da8a62 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-03rockchip: Add gpio_set() functionJulius Werner
The <gpio.h> API is supposed to include a gpio_set() function that just toggles the state of a GPIO already configured as an output, even though we rarely need it since gpio_output() can already be used to initialze a GPIO to a default value while configuring it as an output. This function was forgotten on Rockchip, so this patch adds it now. Change-Id: I201288139a2870e71f55a7af0d79d4a460b30a0c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-02rockchip/rk3399: Pass coreboot table pointer to ARM TFJulius Werner
This patch passes the coreboot table base address to ARM TF on RK3399 devices to be able to use the new coreboot table parsing support. Change-Id: I5cb2f13ce71e374207d0fa7a71c38852d680dc56 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/23557 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-02rockchip: Correct UART reference clock valueJulius Werner
The Rockchip UARTs are tied directly to the 24MHz oscillator and are thus clocked with exactly 24MHz. The reasons why our code instead uses some 23.xxMHz value have long been lost in time. For the current shared 8250 implementation, the baud rate divisor for 115200 would be the same. Correcting this does make the information in the coreboot table more accurate and help payloads chose a better divisor, though. Change-Id: Ieceb07760178f8ddbb5936f8742b78f8def4072d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/23556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-02rockchip/rk3288: Fix includes for <soc/clock.h>Julius Werner
This header uses common types and macros so it needs to include the headers that provide those itself. Change-Id: Ieceb0deadbeef8ddbbb00b13542b78f8def4072d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/23559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-02-02rockchip/rk3399: extend delay between saradc power up and start commandLin Huang
We found when ambient temperature low, with now saradc frequency and delay between saradc power up and start command, there may get wrong adc value, then get the wrong ramid or boardid, so lower the saradc frequency and add the delay time between power up and start command. BUG=b:70692504 BRANCH=gru TEST=test on Dru in 0C temperature, always get right adc value Change-Id: I42e49ca63299479912fa05e2a62cba6f2de4b337 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/23515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-29rockchip/rk3399: Support LONG_WRITE type in MIPI DSILin Huang
Some panels need to transfer initial code, and some of them will be over 3 bytes, so support LONG_WRITE type in driver. Refactor mipi dsi transfer function to support it. Change-Id: I212c14165e074c40a4a1a25140d9e8dfdfba465f Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/23299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-01-10soc/rockchip/rk3399: Ensure full eDP init sequenceEge Mihmanli
This patch fixes 2 edp display issues: 1. When rk_edp_prepare fails >3 times, edp_init isn't run because while-condition is not satisfied. Then, only a partial init sequence is ran. This causes all aux transactions to fail. 2. If rk_edp_prepare never succeeds, coreboot never leaves link training stage due to infinite loop. Boot process is stuck. TEST=Boot past eDP initialization stage and make sure AP logs don't have show aux transaction fails. Change-Id: I44c3f53e8786558c43078d4afe9acde4d64796e7 Signed-off-by: Ege Mihmanli <egemih@google.com> Reviewed-on: https://review.coreboot.org/23152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-12-11google/gru: Stop mucking with unused I2S0 pins in codec configJulius Werner
Due to a schematic error, our code was written to configure more I2S0 pins than are actually used. We're also pinmuxing the whole bank of pins over to the I2S controller even though we don't need them all. Restrict the GPIO initialization and pinmuxing to the pins we really need so the other ones can be correctly used as SKU ID pins on Scarlet. Also, move the "audio" IO voltage domain selection to the other such selections in the bootblock, since that covers two whole banks of GPIOs and there's no guarantee that they're all used for audio (and thus not needed before ramstage). BUG=b:69373077 TEST=Booted Scarlet, confirmed correct SKU ID (7) was detected on rev2. Change-Id: I9314617e725fe83d254984529f269d4442e736f1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Schneider <dnschneid@chromium.org>
2017-12-07rockchip/rk3399: Select GENERIC_GPIO_LIB KconfigJulius Werner
This option should've been selected by RK3399 the whole time since the SoC supports the <soc/gpio.h> interface. It wasn't really a big deal until now where I'm trying to use a the base2 read helper, though. Change-Id: Ib7a5f00a6680163105fc0598ce77d03f3645f05a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22744 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-28google/scarlet: support kd097d04 panelLin Huang
Support kd097d04 dual mipi panel on Scarlet. Change-Id: Ie8bc0cbb79840f1924a8cc111f2511292203731f Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28rockchip/rk3399: support dual mipi dsiLin Huang
Refactor the mipi driver, so we can support dual mipi panel. And pass the panel data from mainboard.c, that we can support different panel with different board. Change-Id: Id1286c0ccbe50c89514c8daee66439116d3f1ca4 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28rockchip/rk3399: mipi: properly configure PHY timingLin Huang
These values are specified as constant time periods but the PHY configuration is in terms of the current lane byte clock so using constant values guarantees that the timings will be outside the specification with some display configurations. Derive the necessary configuration from the byte clock in order to ensure that the PHY configuration is correct. Change-Id: I396029956730907a33babe39c6a171f2fcea9dcd Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28rockchip/rk3399: improve mipi transfer flowLin Huang
check GEN_CMD_FULL status before transfer, check GEN_CMD_EMPTY and GEN_PLD_W_EMPTY status after transfer. Change-Id: I936c0d888b10f13141519f95ac7bcae3e15e95d9 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28rockchip/rk3399: mipi: correct Feedback divider settingLin Huang
This patch correct Feedback divider setting: 1. Due to the use of a "by 2 pre-scaler," the range of the feedback multiplication Feedback divider is limited to even division numbers, and Feedback divider must be greater than 12, less than 1000. 2. Make the previously configured Feedback divider(LSB) factors effective Change-Id: Ic7c5c59be1d00c65c3b17cb3c4bfba8d7459e960 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28rockchip/rk3399: mipi: correct phy parameter settingLin Huang
As MIPI PHY document show, icpctrl<3..0> and lpfctrl<5..0> should depend on frequency, so fix it. Change-Id: Ic4a90767bd1f22d5d784d4013dc7afb3149115c1 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-28rockchip/rk3399: mipi: Fix LOOP_DIV_HIGH_SEL to be 4 bits wideLin Huang
Accroding to datasheet, feedback divider register high value is only 4 bit, it currently uses 5 bit, so correct it. Change-Id: I1fe9fc076b712f27407c5f2735b15e64fb55e72e Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-10-23soc: Add Kconfig for each soc vendorChris Ching
Allows explicit ordering for vendors that share a common configuration that must be sourced last. The issue is that chips in soc/{amd,intel}/[ab].* will be able to override defaults set in this file, but Kconfig files that get sourced later (soc/amd/[d-z].*) will NOT be able to override these defaults. Note: intel and amd soc chips now need to be added manually to the new Kconfig file BUG=b:62235314 TEST=make lint-stable Change-Id: Ida82ef184712e092aec1381a47aa1b54b74ed6b6 Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/22123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-18include/device: Split i2c.h into threeNico Huber
Split `i2c.h` into three pieces to ease reuse of the generic defi- nitions. No code is changed. * `i2c.h` - keeps the generic definitions * `i2c_simple.h` - holds the current, limited to one controller driver per board, devicetree independent I2C interface * `i2c_bus.h` - will become the devicetree compatible interface for native I2C (e.g. non-SMBus) controllers Change-Id: I382d45c70f9314588663e1284f264f877469c74d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-14i2c: Move to Linux like `struct i2c_msg`Nico Huber
Our current struct for I2C segments `i2c_seg` was close to being compa- tible to the Linux version `i2c_msg`, close to being compatible to SMBus and close to being readable (e.g. what was `chip` supposed to mean?) but turned out to be hard to fix. Instead of extending it in a backwards compatible way (and not touching current controller drivers), replace it with a Linux source compatible `struct i2c_msg` and patch all the drivers and users with Coccinelle. The new `struct i2c_msg` should ease porting drivers from Linux and help to write SMBus compatible controller drivers. Beside integer type changes, the field `read` is replaced with a generic field `flags` and `chip` is renamed to `slave`. Patched with Coccinelle using the clumsy spatch below and some manual changes: * Nested struct initializers and one field access skipped by Coccinelle. * Removed assumption in the code that I2C_M_RD is 1. * In `i2c.h`, changed all occurences of `chip` to `slave`. @@ @@ -struct i2c_seg +struct i2c_msg @@ identifier msg; expression e; @@ ( struct i2c_msg msg = { - .read = 0, + .flags = 0, }; | struct i2c_msg msg = { - .read = 1, + .flags = I2C_M_RD, }; | struct i2c_msg msg = { - .chip = e, + .slave = e, }; ) @@ struct i2c_msg msg; statement S1, S2; @@ ( -if (msg.read) +if (msg.flags & I2C_M_RD) S1 else S2 | -if (msg.read) +if (msg.flags & I2C_M_RD) S1 ) @@ struct i2c_msg *msg; statement S1, S2; @@ ( -if (msg->read) +if (msg->flags & I2C_M_RD) S1 else S2 | -if (msg->read) +if (msg->flags & I2C_M_RD) S1 ) @@ struct i2c_msg msg; expression e; @@ ( -msg.read = 0; +msg.flags = 0; | -msg.read = 1; +msg.flags = I2C_M_RD; | -msg.read = e; +msg.flags = e ? I2C_M_RD : 0; | -!!(msg.read) +(msg.flags & I2C_M_RD) | -(msg.read) +(msg.flags & I2C_M_RD) ) @@ struct i2c_msg *msg; expression e; @@ ( -msg->read = 0; +msg->flags = 0; | -msg->read = 1; +msg->flags = I2C_M_RD; | -msg->read = e; +msg->flags = e ? I2C_M_RD : 0; | -!!(msg->read) +(msg->flags & I2C_M_RD) | -(msg->read) +(msg->flags & I2C_M_RD) ) @@ struct i2c_msg msg; @@ -msg.chip +msg.slave @@ struct i2c_msg *msg; expression e; @@ -msg[e].chip +msg[e].slave @ slave disable ptr_to_array @ struct i2c_msg *msg; @@ -msg->chip +msg->slave Change-Id: Ifd7cabf0a18ffd7a1def25d1d7059b713d0b7ea9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-06rockchip: gpio: Correct rk3399 pmu gpio pull settingLin Huang
Starting with RK3399, PMUGPIO pull registers use the same write mask format as normal GRF registers, so they need to use RK_CLRSETBITS() rather than clrsetbits_le32(). BRANCH=None BUG=None TEST=boot from scarlet Change-Id: Ibe391273d58ab35df993e149187d67497fcf2acc Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/20871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-06rockchip: gpio: add gpio_pull argument in gpio_input_irq() functionLin Huang
some gpio irq need to set input pull initialization status to guarantee to get the right irq trigger. let's add this argument in gpio_input_irq() function BRANCH=None BUG=None TEST=boot from bob Change-Id: I9b8e6497f07146dafdb447a6ea10d039a2a2fa33 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/20866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-07-19rockchip/rk3399: Adjust gpio_t format to match ARM TFJulius Werner
Our structure packing for Rockchip's gpio_t was chosen arbitrarily. ARM Trusted Firmware has since become a thing and chosen a slightly different way to represent GPIOs in a 32-bit word. Let's align our format to them so we don't need to remember to convert the values every time we pass them through. CQ-DEPEND=CL:572228 Change-Id: I9ce33da28ee8a34d2d944bee010d8bfc06fe879b Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/20586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-26rockchip/rk3399: update the ddr 200MHz frequency configurationCaesar Wang
This patch updates the coreboot DDR Settings to match the configuration used by ARM-Trusted-Firmware. Change-Id: I34bc2950a9708ac89a5637bf682551e03d993fcc Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://review.coreboot.org/20304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-06-19rockchip/rk3399: fix DRAM gate training issueLin Huang
The differential signal of DQS needs to keep low level before gate training. RPULL will connect 4Kn from PADP to VSS and a 4Kn from PADN to VDDQ to ensure it. But if it has PHY side ODT connected at this time, it will change the DQS signal level. So it needs to disable PHY side ODT when doing gate training. BRANCH=None BUG=None TEST=boot from bob Change-Id: I56ace8375067aa0bb54d558bc28172b431b92ca5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: cb024042c7297a6b17c41cf650990cd342b1376f Original-Change-Id: I33cf743c3793a2765a21e5121ce7351410b9e19d Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/448278 Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com> Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://review.coreboot.org/18582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-08device/Kconfig: Introduce MAINBOARD_FORCE_NATIVE_VGA_INITNico Huber
MAINBOARD_FORCE_NATIVE_VGA_INIT is to be selected instead of the user option MAINBOARD_DO_NATIVE_VGA_INIT. The distinction is necessary to use the latter in a choice. Change-Id: I689aa5cadea9e1091180fd38b1dc093c6938d69c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-02Kconfig: Introduce HAVE_(VBE_)LINEAR_FRAMEBUFFERNico Huber
Like HAVE_VGA_TEXT_FRAMEBUFFER, these are selected by graphics drivers that support a linear framebuffer. Some related settings moved to the drivers (i.e. for rockchip/rk3288 and nvidia/tegra124) since they are hardcoded. Change-Id: Iff6dac5a5f61af49456bc6312e7a376def02ab00 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-26rockchip/rk3399: fix rk_mipi_dsi_phy_init errNickey Yang
This patch fix rk_mipi_dsi_phy_init error return. Change-Id: Ie260975ad6ed26c37aa8bb65dfcef4db2407a2da Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> Reviewed-on: https://review.coreboot.org/19903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-24rk3399: Reshuffle memlayout to move PRERAM_CBMEM_CONSOLE further backJulius Werner
It seems that the BootROM on the RK3399 overwrites some of the earlier parts of SRAM, including the PRERAM_CBMEM_CONSOLE area. Now that we have a persistent CBMEM console we want that area to survive in case of an early (pre-CBMEM) reboot, so shuffle the layout around a bit to move it further back. (This reduces the stack size to 12KB which should still be way more than enough.) Change-Id: Ifc1e568cda334394134bba9eba75088032d2ff13 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-24soc/rockchip: Move spi driver to use spi_bus_mapFurquan Shaikh
This is in preparation to get rid of the strong spi_setup_slave implemented by different platforms. BUG=b:38430839 Change-Id: I66b1b9635ece2381f62f2a9d6f5744d639d59163 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-18rockchip/rk3399: soc: resize reserve memoryXing Zheng
Reserve the whole TZRAM area because it will be marked as secure-only by BL31 and can not be accessed by the non-secure kernel. CQ-DEPEND=CL:452659 BUG=chrome-os-partner:57361 BRANCH=firmware-gru-8785.B TEST=the reserve memory is resized Change-Id: Ie3ab39598f3f7cb96feb0c574e230e7fcb53a1a4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f34d254e1dfc9ae95a784aba22503e75a2fa65f1 Original-Change-Id: I39c4cb530f41a7b0f7f3064125072dd85b62276f Original-Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/418102 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-(cherry picked from commit ea9fe064a9b1e1ce81fca74f829a0fb6e78ce426) Original-Reviewed-on: https://chromium-review.googlesource.com/452640 Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-18rockchip/rk3399: Add MIPI driverNickey Yang
This patch configures clock for mipi and then adds mipi driver for support innolux-p079zca mipi panel in rk3399 scarlet. Change-Id: I02475eefb187c619c614b1cd20e97074bc8d917f Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> Reviewed-on: https://review.coreboot.org/19477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-18rockchip/rk3399: remove the delay for enabling SSCCaesar Wang
The hang was caused by deasserting the reset before, it had been delayed 20us fixing the hang issue. So we can remove this delay for now. Change-Id: I5545377b72eb20b59ceaaca25c78965854bfb919 Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://review.coreboot.org/19699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-11rockchip/rk3399: enable DPLL SSC for DDR EMI test on bobCaesar Wang
Spread Spectrum Modulator (SSMOD) is a fully-digital circuit used to modulate the frequency of the Silicon Creations’ Fractional PLL in order to reduce EMI. We need to turn the DPLL spread spectrum feature on to reduce the EMI noise for DDR on bob. Change-Id: I75461d4235bcf55324e6664a1220754e770b4786 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://review.coreboot.org/19557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
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