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path: root/src/soc/rockchip/rk3399/clock.c
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2016-07-12rockchip/rk3399: initialize apll_bLin Huang
coreboot boots from the little core, and doesn't use the big core for now, but if apll_b is set to the default 24MHz, it will take a long time to enable the big core. This will cause a watchdog crash, so apll_b initialization to 600MHz needs to be done in coreboot. BRANCH=none BUG=chrome-os-partner:54817 TEST=Pick CL:353762 and see big CPU clocks look right TEST=Boot from Gru and see no cpufreq warnings Change-Id: Ie45cd2271555942e4321e9a9e523dc10f63d8107 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: Original-Change-Id: I20b8b591db3171e27740d85edce11f9e8797d849 Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Original-Commit-Id: 16bc916174042620bebe19ae73d241002491aecc Original-Original-Change-Id: Id3487138b383b6643ba7e3ce1eae501a6622da10 Original-Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Original-Reviewed-on: https://chromium-review.googlesource.com/356399 Original-Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15583 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-12rockchip/rk3399: Use apll instead of apll_l defineLin Huang
Use the apll define instead of the apll_l define so it can be reused when setting apll_b. BRANCH=None BUG=None TEST=Boot from Gru Change-Id: Iebc4ce3b66a86c33653292340b9855265ac4fc07 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: eb578110d19a35ef04f8749fdc202055abd50fd1 Original-Change-Id: I63966e98af48eaf49837eb0b781eea001a376ef4 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/356398 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Tested-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/15582 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-12rockchip/rk3399: calculate clocks based on parent clock speedLin Huang
Currently aclkm pclkdbg atclk clocks use apll_l as a parent, but the apll_l frequency may change in firmware, so we need to caculate the div value based on the apll_l frequency. BRANCH=None BUG=chrome-os-partner:54376 TEST=Boot from Gru Change-Id: I2bd8886168453ce98efec58b5490c2430762769b Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 116ae863a504630e2aff056564836d84198fcae2 Original-Change-Id: I7e3a5d9e3f608ddf15592d893117c92767fcd015 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/356397 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15581 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08rockchip: rk3399: Add support i2sXing Zheng
This patch enable and configure the clocks and IOMUX for i2s audio path, and the i2s0 clock is from CPLL. Please refer to TRM V0.3 Part 1 Chapter 3 CRU, P126/P128/P144/P154/P155 for the i2s clock div and gate setting. BRANCH=none BUG=chrome-os-partner:52172 TEST=boot kevin rev1, press ctrl+u and hear the beep voice. Change-Id: Id00baac965c8b9213270ba5516e1ca684e4304a6 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 9c58fa7 Original-Change-Id: I130a874a0400712317e5e7a8b3b10a6f04586f68 Original-Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/347526 Original-Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15034 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-07rockchip: gru: update the hynix lpddr3 config to run at 928MHzShunqian Zheng
Update the DDR config and DRAM driver to allow running at up to 928MHz. Kevin config/clock rate are not being changed, but Gru now runs at 928 MHz. BRANCH=none BUG=chrome-os-partner:51537 TEST=booted Kevin and Gru to Linux prompt. Ran stressapptest for 10 min on Gru, Change-Id: I66c1a171d5c7d05b2878c7bc5eaa0d436c7a1be2 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 8baf0d82816a7ea1c4428e15caeefa2795d001f9 Original-Change-Id: I5e1d6d1025f10203da8f11afc3bbdf95f133c586 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/343984 Original-Reviewed-by: Stephen Barber <smbarber@chromium.org> Reviewed-on: https://review.coreboot.org/15027 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-18rockchip: rk3399: configure emmc clkLin Huang
Select aclk_emmc and clk_emmc source from GPLL, and both to 198MHz, that is GPLL(594MHz) divided by 3. BRANCH=none BUG=chrome-os-partner:51537 TEST=boot kevin rev1 to chromeos prompt from both emmc and sdcard TEST=LoadKernel faster, more than twice as I measured manually. Change-Id: I2580c43b8c79049c3fe16bbf60bfa1a8e0559948 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 5fd37b66dcce77354e1cafab0d6e806d832c08d2 Original-Change-Id: Id22815b302af3204e0e5537af99c1577b09b0877 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/339152 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14855 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18rockchip: rk3399: add tsadc driverShunqian Zheng
This patch configures clock for tsadc and then makes it in automatic mode to generate TSHUT when CPU temperature is higer than 120 degree Celsius. BRANCH=none BUG=chrome-os-partner:52382,chrome-os-partner:51537 TEST=Set a lower tshut threshold(45C), run coreboot and check that coreboot reboot again and again. Change-Id: I0b070a059d2941f12d31fc3002e78ea083e70b13 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 05107bd6a3430e31db216c247ff0213e12373390 Original-Change-Id: Iffe54d3b09080d0f1ff31e8b3020d69510f07c95 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/342797 Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/14848 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18rockchip: rk3399: add routines to set vop clocksShunqian Zheng
Let vop aclk sources from CPLL, and vop dclk from NPLL. The dclk freq is decided by the edid mode pixel_clock which may require high accuracy like 252750KHz. The pll_para_config() can calculate the dividers for PLL to output desired clock. BRANCH=none BUG=chrome-os-partner:51537 TEST=check display with the other patches Change-Id: I12cf27d3d1177a8b1c4cfbd7c0be10204e3d3142 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 0f019b055fffebe9ea3928aae1e25b0ad4feef81 Original-Change-Id: Icef58f87041905961772b69c6b8170d5a866a531 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/342335 Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@google.com> Reviewed-on: https://review.coreboot.org/14846 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-09rockchip: rk3399: support saradcLin Huang
This patch add functions to configure saradc clk and get saradc's raw value for each channel. Currently add saradc to ramstage. Please refer to TRM V0.3 Part 2 Chapter 18 for this IP. BRANCH=none BUG=chrome-os-partner:51537 TEST=on kevin board, get the raw value 61 for channel 0, measure the ADC_IN0 as 0.109V, 61.0/1024 = 0.05957 0.109V/1.8V = 0.06056 Change-Id: Ic198b2a964ccf8bb687441f0e2702665402fff6e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc400316de2d75eccad3990a4187bf2dc49a844a Original-Change-Id: I542430ed97bd27f9bfcec89b1d703d9fa390d4e0 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/334177 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14720 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add i2c clock driverhuang lin
This patch add i2c clock driver and reuse the common rockchip i2c driver. The i2c0,4,8 src clock from ppll, while i2c1,2,3,5,6,7 from gpll. Please refer to TRM V0.3 Part1 Page 142 for i2c clock setting. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I91822e483244d71798a1c68f14ba0a84f405a665 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 270118e44d159f6a27812fa234b34fe7ac54cbe4 Original-Change-Id: Iea5f4a93cf173e1278166dcb04e19a4ef6c4af04 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/338948 Reviewed-on: https://review.coreboot.org/14711 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add spi clock driverShunqian Zheng
This patch implements spi clock driver and initialize SPI flash rom for the baseboard gru. There are 6 on-chip SPI controllers inside RK3399. For SPI3, it's source clk from ppll, while the others from gpll. Please refer to CRU session of TRM for detail. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I597ae2cc8ba1bfaefdfbf6116027d009daa8e049 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c6a9b0aedd427727ed4f4a821c5c54fb3a174b9 Original-Change-Id: I68ad859bf4fc5dacaaee5a2cd33418c729cf39b8 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/338946 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14710 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add functions to configure ddrc freqShunqian Zheng
This patch list four frequencies for ddr controller, 200MHz, 300MHz, 666MHz and 800MHz and configure each freq by setting the DPLL dividers. By default, the clk_ddrc is from DPLL and equals to DPLL, so here we only need to set the DPLL clock. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: Ifabe85b5dc95e3c8e3e9cbf946e12e8b06b881cf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 18ec4f7d8738472fbadd60fa3c8f810f5347ffa2 Original-Change-Id: I448057542c3885068ddffa5b37d0341ee3ec04b1 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/340184 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14707 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: support basic clock driverLin Huang
This patch initialize the PLL clocks and add function to configure cpu freq. Right now, we set the little cpu freq to 600MHz. In coreboot, we currently care about these four PLLs, o. APLL for cpu clk, where A stands for AXI, o. CPLL and GPLL are the generic PLL mainly for peripheral clk, o. PPLL is only PMU clk. For the peripheral clocks, there are thress clocks named as, aclk_perihp, aclk_perilp0, hclk_perilp1, where the 'h' and 'l' letters refer to High and Low speed. As the diagram below, the aclk_perihp always be the parent of more higher speed peripheral devices like pcie, and hclk_perilp1 for spi, i2c, aclk_perilp0 for crypto. These three clocks can choose parent from GPLL or CPLL freely, in this patch, they are all sourced from GPLL. GPLL(594M)/CPLL(384M) APLL(600M for little core) | | `-- aclk_perihp `-- clk_core(600M == APLL) | | | | `-- periph_aclk(148.5M) `-- atclk_core(300M) | `-- periph_hclk(148.5M) `-- aclkm_core(300M) | `-- periph_pclk(37.125M) `-- pclk_dbg_core(100M) | `-- hclk_perilp1 | | | `-- periph_hclk(99M) PPLL(594M) | `-- periph_pclk(49.5M) | | `-- pmu_pclk(99M) `-- aclk_perilp0 | `-- periph_aclk(99M) `-- periph_hclk(99M) `-- periph_pclk(49.5M) BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I1c46ff17e6b466529244afb41d7fd4abbcfd3da4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9f0d31177336a3450577950426f9cc9d56e2254c Original-Change-Id: I4ad00df3e406bd0a7576287d6e62b8993a8c2d02 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332386 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14706 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: use static pointers to regs as they compile to faster codeVadim Bendebury
Quoting an earlier review comment, using static structures pointers in the include file "should allow the compiler to optimize accesses better than defining it in a separate compilation unit (by being able to constant fold stuff like &rk3399_pmusgrf->field into a single address, rather than loading the symbol, loading an offset constant and adding)". Any decent compiler linker system nowadays would consolidate this definition in any case. BRANCH=none BUG=chrome-os-partner:51537 TEST=with the rest of the patches applied Kevin successfully boots Linux kernel. Change-Id: Ibb576c7691a30f2f429651fcca133bd72710c13b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 89b6f22e37f733667156f15afb8c27d8a9f07512 Original-Change-Id: Ice8d6d766a91e7f4fce553378a23b9ca593d12dd Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/339869 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14705 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add the GRF header fileLin Huang
The GRF(general register file) of rk3399 is divided into two sections, o. GRF, used for general non-secure system o. PMUGRF, used for always-on syosyem This patch defines the registers used for iomux/gpio/system control. BRANCH=none BUG=none TEST=emerge-kevin coreboot Change-Id: I3239793523e0f55f6661ef029c3dac9970990fb8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 897d01573ea2bbe2b3091358ec3c9728ee82f8ec Original-Change-Id: I4c228ddb60c9c4056de50312dc269227fac9a7fa Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332388 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14704 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-13rockchip/rk3399: Add a stub implementation of the rk3399 SOChuang lin
Most things still need to be filled in, but this will allow us to build boards which use this SOC. BRANCH=none BUG=chrome-os-partner:51537 TEST=with the rest of the patches applied Kevin board can be booted to Linux login propmt. Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 27dfc39efe95025be2271e2e00e9df93b7907840 Original-Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/332385 Reviewed-on: https://review.coreboot.org/13915 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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