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path: root/src/soc/rockchip/rk3399/bootblock.c
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2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06soc/rockchip: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I773cc57197b29fd3f4522aece4c83b3dc9e646e0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22rk3399: Enable bootblock compressionJulius Werner
This patch enables the new bootblock compression feature on RK3399, which requires moving MMU initialization into the decompressor stage and linking the decompressor (rather than the bootblock) into the entry point jumped to by the masked ROM. RK3399's masked ROM seems to be using a bitbang SPI driver to load us (very long pauses between clocking in each byte), with an effective data rate of about 1Mbit. Bootblock loading time (as measured on a SPI analyzer) is reduced by almost 100ms (about a third), while the decompression time is trivial (under 1ms). Change-Id: I48967ca5bb51cc4481d69dbacb4ca3c6b96cccea Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-31rockchip/rk3399: Add pwm_regulator.c for pwm then ramp boot up cpuEric Gao
Before, we calculate the pwm duties for cpu cores and centerlogic by hand, adding pwm_regulator.c to handle this. The default pwm design min/max voltage may be different between revs. With the pwm regulator, this patch changes the little cpu frequency from 600M to 1512M, and raises CPU voltage to 1.2V correspondingly. This also means we decide to drop the ES1 because it may fail to bootup with 1.5G ~ 1.2v. BRANCH=none BUG=chrome-os-partner:54376,chrome-os-partner:54862 TEST=Bootup on kevin board Change-Id: Id04c176bddfb9cdf3d25b65736e40249a85f6aa1 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: ee4365c787ec523b7ee1028ea100dcfbb331b3a9 Original-Change-Id: Ide75bbd92d1cbb14f934baeec0e38862bc08402b Original-Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/364410 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16368 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-12rockchip/rk3399: initialize apll_bLin Huang
coreboot boots from the little core, and doesn't use the big core for now, but if apll_b is set to the default 24MHz, it will take a long time to enable the big core. This will cause a watchdog crash, so apll_b initialization to 600MHz needs to be done in coreboot. BRANCH=none BUG=chrome-os-partner:54817 TEST=Pick CL:353762 and see big CPU clocks look right TEST=Boot from Gru and see no cpufreq warnings Change-Id: Ie45cd2271555942e4321e9a9e523dc10f63d8107 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: Original-Change-Id: I20b8b591db3171e27740d85edce11f9e8797d849 Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Original-Commit-Id: 16bc916174042620bebe19ae73d241002491aecc Original-Original-Change-Id: Id3487138b383b6643ba7e3ce1eae501a6622da10 Original-Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Original-Reviewed-on: https://chromium-review.googlesource.com/356399 Original-Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15583 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-12rockchip/rk3399: Use apll instead of apll_l defineLin Huang
Use the apll define instead of the apll_l define so it can be reused when setting apll_b. BRANCH=None BUG=None TEST=Boot from Gru Change-Id: Iebc4ce3b66a86c33653292340b9855265ac4fc07 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: eb578110d19a35ef04f8749fdc202055abd50fd1 Original-Change-Id: I63966e98af48eaf49837eb0b781eea001a376ef4 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/356398 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Tested-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/15582 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-09rockchip: rk3399: init the secure settingShunqian Zheng
set sdram, sram and all device to non-secure status, so we can free to do mmu operation in coreboot. bl31 will care about secure control. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I11e02246550630c6dfe4e0cbad01e8cd5b83ef1e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ae2df532856110c4d87eb162fd3687f8de27c77f Original-Change-Id: Ia026cf685a9d7bdf7b0c7181b1b325c54bc4554f Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/338947 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14715 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: enable mmuLin Huang
This patch initialize MMU and config mmu ranges for rk3399. During the bootblock phase, mark the max dram size supported(4GiB) as device memory because the mmio space start at 0xF8000000, and _sram as secure memory. After ddr setup in romstage, remark whole dram as cached memory except the _dma_coherent range. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I0cd4abb8c30b73d87d8ba6f964edd42bdf4813fb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fc22ab0c16d8107c217db1629286d5ff1c4bc5b3 Original-Change-Id: I66bfde396036d7a66b29517937a28f0767635066 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332387 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14708 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: support basic clock driverLin Huang
This patch initialize the PLL clocks and add function to configure cpu freq. Right now, we set the little cpu freq to 600MHz. In coreboot, we currently care about these four PLLs, o. APLL for cpu clk, where A stands for AXI, o. CPLL and GPLL are the generic PLL mainly for peripheral clk, o. PPLL is only PMU clk. For the peripheral clocks, there are thress clocks named as, aclk_perihp, aclk_perilp0, hclk_perilp1, where the 'h' and 'l' letters refer to High and Low speed. As the diagram below, the aclk_perihp always be the parent of more higher speed peripheral devices like pcie, and hclk_perilp1 for spi, i2c, aclk_perilp0 for crypto. These three clocks can choose parent from GPLL or CPLL freely, in this patch, they are all sourced from GPLL. GPLL(594M)/CPLL(384M) APLL(600M for little core) | | `-- aclk_perihp `-- clk_core(600M == APLL) | | | | `-- periph_aclk(148.5M) `-- atclk_core(300M) | `-- periph_hclk(148.5M) `-- aclkm_core(300M) | `-- periph_pclk(37.125M) `-- pclk_dbg_core(100M) | `-- hclk_perilp1 | | | `-- periph_hclk(99M) PPLL(594M) | `-- periph_pclk(49.5M) | | `-- pmu_pclk(99M) `-- aclk_perilp0 | `-- periph_aclk(99M) `-- periph_hclk(99M) `-- periph_pclk(49.5M) BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I1c46ff17e6b466529244afb41d7fd4abbcfd3da4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9f0d31177336a3450577950426f9cc9d56e2254c Original-Change-Id: I4ad00df3e406bd0a7576287d6e62b8993a8c2d02 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332386 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14706 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-13rockchip/rk3399: Add a stub implementation of the rk3399 SOChuang lin
Most things still need to be filled in, but this will allow us to build boards which use this SOC. BRANCH=none BUG=chrome-os-partner:51537 TEST=with the rest of the patches applied Kevin board can be booted to Linux login propmt. Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 27dfc39efe95025be2271e2e00e9df93b7907840 Original-Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/332385 Reviewed-on: https://review.coreboot.org/13915 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-03 04:07:57 +0000