coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2015-03-24	add make_idb.py & update bootblock	huang lin
	BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: Ica7b2bf2cf649c2731933ce59a263692bb2c0282 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ba9c36daedc749748f45e68a84f8c34c636adb1c Original-Change-Id: Ia0e4e39d4391674f25e630b40913eb99ff3f75c4 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209427 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8862 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-24	rk3288: add clock module	jinkun.hong
	Call rkclk_init() in bootblock stage. apll = 816MHz, gpll = 594MHz, cpll = 384MHz, dpll = 300MHz arm clk = 816MHz, DDR clk = 300MHz, mpclk = 204MHz, m0clk = 408MHz l2ramclk = 408MHz, atclk = 204MHz, pclk_dbg = 204MHz aclk = 148.5MHz, hclk = 148.5MHz, pclk = 74.25MHz BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: Id5967712e25df5be3a90f5d9ebe8671034deff68 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d35d9fe7b5925291e9303e5eb21d20dbbdee99d9 Original-Change-Id: I97d953258039f6caa499cef4462be8f1a05ce2ab Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209428 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8858 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-16	coreboot: rk3288: Add a stub implementation of the rk3288 SOC	jinkun.hong
	Most things still needs to be filled in, but this will allow us to build boards which use this SOC. BUG=chrome-os-partner:29778 TEST=emerge-veyron coreboot Original-Change-Id: If643d620c5fb8951faaf1ccde400a8e9ed7db3bc Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205069 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 2f72473a8c2b3fe21d77b351338e6209035878fb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I53fd0ced42f6ef191d7bf80d8b823bb880344239 Reviewed-on: http://review.coreboot.org/8653 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>