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This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.
This patch was created by running
sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'
across the codebase and cleaning up formatting a bit.
Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Also including <types.h>, is supposed to provide stdint and stddef.
Change-Id: Iab605f6be4a48c10fa5aae7a1222520149ad1392
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Guckian
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MMIO operations are arch-agnostic so the include
path should not be arch/.
Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Id90aa210ff72092c4ab638a7bafb82bd11889bdc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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To avoid garbage display in firmware on warm reset, we need
to enable eDP display in depthcharge instead when the framebuffer is
cleared.
Therefore limit edp_enable() in coreboot to just configure eDP,
and leave enabling the display to depthcharge.
CQ-DEPEND=CL:402071
BUG=chrome-os-partner:58675
BRANCH=none
TEST=Boot from kevin, and display work
Change-Id: I9d937ead33ebba58e33e02fd73b80d6e11bb69aa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 38b0d18c3fae37dfccb18fe809f763b98703167c
Original-Change-Id: Ibbc283a5892b98f4922f02fd67465fe2e1d01b71
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/402095
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17207
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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rk3288 and rk3399 use same edp IP, move soc specific setting to
soc/display, and move edp driver to common, so rk3399 can reuse
this driver.
BUG=chrome-os-partner:52460
BRANCH=none
TEST= test on jerry and mighty, edp panel can work
Change-Id: Ie3f3e8468b2323994af8a002413bf93b3edc8026
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64bb4b2c7ed373d9730c9aa0b0896a32164fc7ee
Original-Change-Id: Ie5c15a81849a02d1c0457e36ed00fbe2d47961fb
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/340504
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14725
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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