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Change-Id: I0ca7cbbf6c4884b58b4ec8a8e3cbc77f118a42f2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Modem uses different memory regions based on LTE/WiFi.
This adds correct carve-out to prevent region being disturbed.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: T Michael Turney <quic_mturney@quicinc.com>
Change-Id: I56bfb210606b08893ff71dd1b6679f1ec102ec95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I61c695fb4fef3ae36ffc5a263236b9d40c299dc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Remove vbp & hbp as the names are misleading and use edid variables
to simplify the video mode active and total calculations.
Change-Id: I9ccafabe226fa53c6f82e32413d4c00a0b4531be
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Found using:
diff <(git grep -l '#include <delay.h>' -- src/) <(git grep -l 'get_timer_fsb(\|init_timer(\|udelay(\|mdelay(\|delay(' -- src/) |grep "<"
Change-Id: Id1e0f4cb9f6181dc2fc45e7b6cb149646111bb3e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Found using:
diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<"
Change-Id: I9097972080499bd61981fe738be93f7b193f5813
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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In order to make SC7180 boards compatbile with some optional Kconfigs,
increase the bootblock size a bit and add room for a TCPA log buffer to
memlayout. The large pre-RAM CBFS cache wasn't really needed anymore
anyway since we switched QcLib to use LZ4 compression.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I7321cca9d7b79368115c57f156b8e71657802a41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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<types.h> already provides <commonlib/bsd/cb_err.h>, <limits.h>,
<stdbool.h>, <stdint.h> and <stddef.h> headers.
Change-Id: I700b3f0e864ecce3f8b3b66f3bf6c8f1040acee1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Adding USB addressmap for sc7280.
Use common USB driver for sc7280.
BUG=b:182963902
TEST=Validated USB enumeration on qcom sc7280 development board
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Change-Id: Ib92b74c8035a8c0148a9aa48e7870b261b832a33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Add common USB driver for qualcomm soc sc7180 and sc7280.
This includes dwc3 controller, qmp ss phy, qusb hs phy and snsp hs phy.
BUG=b:182963902
TEST=Validated USB enumeration on qcom sc7180 and
sc7280 development board
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Change-Id: I1013ded22855286220cfa747cb25418070fe85a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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eGPIO is a scheme which allows special power island domain IOs to be
reused as regular chip GPIOs by muxing regular TLMM functions with
Island Domain functions. Allow the eGPIO to be configured via
gpio_configure API to be used as a TLMM gpio.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: Ib2598a41ba3bb8a8a2acff8253b5bb78633f89f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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CPUCP is CPUSS Control Processor. It refers to the firmware for control
CPUSS active power management.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Avoid indirect <vc/google/chromeos/chromeos.h> as the
files really only need <security/vboot/vboot_common.h>.
Change-Id: Ic02bd5dcdde0bb5c8be0e2c52c20048ed0d4ad94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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AOP firmware support from sc7280.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: Ib7027cdf78a9cdcccc8cfff7eef3cc540fb4093e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Move AOP firmware support from qualcomm/sc7180 into qualcomm/common
BUG=b:182963902
TEST=Validated on qualcomm sc7180 development board
Change-Id: I90b0f48e15df390970e027bff2065b7a89b14cec
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I62044f6fcb301c0ca35c42598f998913f9b94b95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Add GSI Firmware download support for QUP wrappers.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I68c106c942acadc752351f03843d93612cf9c19f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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The SHRM region needs to be 4 byte aligned, which make enabling
compression slightly more complicated. We need to map it to cached
memory before loading it and flushing to memory (in aligned chunks)
then remapping the address space back to device memory before
beginning execution of the SHRM region.
Also, did some cleanup in this file based on comments in CB:49392.
BUG=b:182963902
BRANCH=None
TEST=Make sure we can still boot to kernel on herobrine
Change-Id: Iaad8a8a02abe40bd01766d94ef0b61aac7671936
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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SHRM is a system hardware resource manager. It is used to manage run time
DDRSS activities. DDRSS stands for DDR subsystem.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
by trying DDR clocks which through SHRM RSI command.
Change-Id: I44484573a829eaefbd34907c6fe78d427506a762
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Enable common Uart driver on sc7280
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I015e21081391bfe85edf667685bf117401a9ec00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55963
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables bootblock compression on SC7280. In my tests, that
makes it boot roughly 10ms faster (which isn't much, but... might as
well take it).
Ref link: https://review.coreboot.org/c/coreboot/+/45855
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Change-Id: I3564a7e531d769c8df16a1592ea98133d83b07b0
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:182963902
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -B
Change-Id: I3ec557bdf2286c3f60902d5ac018b536fe99afa3
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57896
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move existing UART driver from sc7180 to common folder.
This implements UART driver for QCOM SoC's
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I7bc2d3765f956e04bae3e45c3a9b9e2ad424c7b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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This implements the SPI driver for the QUP core.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I7e5d3ad07f68255727958d53e6919944d3038260
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56399
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I34a45422e38ea3a47f29e9856fc5679e8aebbcdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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This implements qup spi driver for qualcomm chipsets
Rename header file names for trogdor to prevent breakage.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I2f2b25b6661fcd518f70383da0c7788c5269c97b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55953
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I58c2b79ea2feeab0ad4c2b7cdaa041984160a7ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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copy existing I2C driver from /soc/qualcomm/sc7180 to common folder.
This implements i2c driver for qualcomm chipsets
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I16e6fc2c1c24b9814d1803bffd5cfbb657201cfb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Enable common qup driver in sc7280
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I0e9049557ff63898037210e72333e1739ab62413
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Update the TLMM register values for eMMC and SD card on Trogdor,
Herobrine and Mistral boards.
BUG=b:196936525
TEST=Validated on qualcomm sc7280 and sc7180 development board and checked
basic boot up.
Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Change-Id: Iccdb7757027c6de424a82e4374bad802501ac83c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57450
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updated return type as CB_SUCCESS and aligned indentation.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Ifabe0508a37a841779965f4e38172f680e18d38a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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copy existing QUP driver from /soc/qualcomm/sc7180 to common folder.
This QUP common driver provide QUP configurations, GPI and SE
firmware loading and initializations.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I95a0fcf97b3b3a6ed26e62b3084feb4a2369cdc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Our MIPI panel initialization framework differentiates between DCS and
GENERIC commands, but the exact interpretation of those terms is left to
the platform drivers. In practice, the MIPI DSI transaction codes for
these are standardized and platforms always need to do the same
operation of combining the command length and transfer type into a
correct DSI protocol code. This patch factors out the various
platform-specific DSI protocol definitions into a single global one and
moves the transaction type calculation into the common panel framework.
The Qualcomm SC7180 implementation which previously only supported DCS
commands is enhanced to (hopefully? untested for now...) also support
GENERIC commands. While we're rewriting that whole section also fix some
other issues about how exactly long and short commands need to be passed
to that hardware which we identified in the meantime.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I09ade7857ca04e89d286cf538b1a5ebb1eeb8c04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Refactor Qcom QSPI driver to separate common
and SoC specific driver code.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: Ibe1dc3fe8bd71957ff8604ef4c9d97963100ccfb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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copy existing QSPI driver from /soc/qualcomm/sc7180 to common folder.
This common QSPI driver works in master mode and provides read/write
operation for the slave devices like flash.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I5b3816b823e14db1dd13f1eb4a6761c7a61604b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Introduce DDR One-Time-Training Support
Device reboots without training from second iteration
and also DDR training data is 32kb size, hence update
required in memlayout and to sync with upstream changes
the Fmap size even got bumped up.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: I81038c5c7802c154f4310509c6c64710580b8ce4
Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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It supports the clock consumers for QUP, SDCC, PCIE, Display to be able
to configure & enable the desired clocks.
The clock driver also supports reset of subsystems like AOP and SHRM.
Also add support for Zonda PLL enable for CPU in common clock driver.
Refactor the SC7280 clock driver to use the common clock driver APIs.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: I590a93cda0d6eccb51b54692b620d43ccacede77
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50580
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The clock driver supports configuring the general purpose PLLs,
configuring the root clock generator (RCG), enable clock branch, enable
gdsc and also the block resets.
The common clock driver exposes PLL configuration functions and also
different Agera PLL enable functions for the CPU PLLs.
While at it, the common driver also supports reset of subsystems like
AOP and SHRM.
SC7180 clock driver is also refactored to use the common clock
driver APIs.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Change-Id: I03d1b4a2fb90303c7259ec08f312d78b4e33ec39
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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As we move to use the common clock driver, the sc7180 clock driver,
watchdog and display drivers requires few cleanups, thus update the
impacted drivers.
Earlier the display client is expected to provide 2n divider value,
as the divider value in register is in form "2n-1".
mdss_clk_cfg.div = half_divider ? (half_divider - 1) : 0;
The older convention in the upcoming patches would be replaced with
the common macro of QCOM_CLOCK_DIV, thus need the divider needs to
be updated.
mdss_clk_cfg.div = half_divider ? QCOM_CLOCK_DIV(half_divider) : 0;
To accommodate impacting the functionality, the half_divider is taken
care in the clock driver.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 development board
Change-Id: Ic334fd0d43e5b4b1e43a27d5db7665f0bc151d66
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Sounds like we prefer to have this under drivers/ instead of device/.
Also move all MIPI-related headers out from device/ into their own
directory.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib3e66954b8f0cf85b28d8d186b09d7846707559d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch changes the sc7180 boards to use the new common MIPI panel
framework, which allows more flexible initialization command packing and
sharing panel definitions between boards. (I'm taking the lane count
control back out again for now, since it seems we only ever want 4 for
now anyway, and if we ever have a need for a different lane count it's
not clear whether that should be a property of the board or the panel or
both. Better to leave that decision until we have a real use case.)
Also, the code was not written to deal with DCS commands that were not a
length divisible by 4 (it would read over the end of the command
buffer). The corresponding kernel driver seems to pad the command with
0xff instead, let's do the same here. (Also increase the maximum allowed
command length to 256 bytes, as per Qualcomm's recommendation.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I78f6efbaa9da88a3574d5c6a51061e308412340e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56966
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- configure TROGDOR_HAS_MIPI_PANEL to "n" by default, it can be updated for mipi panels.
- add simple rm69299 panel as an example to append new mipi panels.
- use existing edid struct to update mipi panel parameters.
- add dsi command tx interface for mipi panel on commands.
Change-Id: Id698265a4e2399ad1c26e026e9a5f8ecd305467f
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52662
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The GENMASK is defined in multiple files (with various names such as
MASKBIT), which sets certain consecutive bits to 1 and leaves the others
to 0. To avoid duplicate macros, add GENMASK macro to helpers.h.
GENMASK(high, low) sets bits from `high` to `low` (inclusive) to 1. For
example, GENMASK(39, 21) gives us the 64-bit vector 0x000000ffffe00000.
Remove duplicate macro definitions. Also utilize GENMASK for _BF_MASK in
mmio.h.
BUG=none
TEST=make tests/commonlib/bsd/helpers-test
TEST=emerge-cherry coreboot
BRANCH=none
Change-Id: If2e7c4827d8a7d27688534593b556a72f16f0c2b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I16c41031718e1c3e41d0a128c8b254e2f6f94093
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: Ic6c70f917a59e233f6ea518d9c39f73fe84991c3
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47284
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The common gpio driver can be re-used for SC7180,
thus remove the existing gpio driver support and
also clean up the common macro definitions.
Add GPIO pin details specific to SC7180 chipset
for the consumers to be able to request for the
gpio functionality as per their requirement.
TEST=Validated on qualcomm sc7180 development board
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Ifd206e6bc9a549706e7a2c4bde0b7d5527ca6268
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Use the gpio offset macro instead of a constant value.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Ia9e4b9ca7216092665f0a06ce467da01963c2364
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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As part of GPIO driver cleanup across qcom chipsets,
GPIO_OUTPUT_ENABLE has been renamed to GPIO_OUTPUT.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 development board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I51eedc722a91c5ea8e009fb8468a60667d374b49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Defining a macro for the gpio offset instead of a constant value.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Iefdde8f8331cf1df2e88a2c8915aefb4fa091d65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Add GPIO pin details specific to SC7280 chipset
for the consumers to be able to request for the
gpio functionality as per their requirement.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: I63bcaed78a6eeb0e6fad857b89d40181613e50cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Add common gpio functionalities across qualcomm soc targets.
This common gpio driver would allow the consumers to be able to
configure gpio function, set/get gpio direction as input/output,
configure the gpio as pull-up/pull-down, configure the gpio as an
IRQ and also query the gpio irq status.
The GPIO pin definition would be SoC specific.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Ia672130c6ca938d9284cae5071307637709480d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55076
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I8501e9ce52bb296bb42797d8b43fd38174b80550
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Change-Id: Ic98b5d08a0a7b3f772582bf85d94f901a7c53010
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Change-Id: If5ebcc9a35e0b86321045ef44bb4874144c6402f
Signed-off-by: Sudheer Kumar Amrabadi <samrab@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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* Qclib_Ver: BOOT.MXF.1.0-00745-KODIAKLC-2
* Chipcode_Release_Tag: r00003.1
Change-Id: I2d400f0ad96dbef2e45cc1f11ed17ea95fc60d16
Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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the signal integrity strength to correct voltage level 1.8V
BUG=b:184714790
BRANCH=trogdor
TEST=HW test
Change-Id: Iee7b458b6aa7d701724da87ecdf0f993d0565c0c
Signed-off-by: yolkshih <yolkshih@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wenchao Han <hanwenchao@huaqin.corp-partner.google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Now that qc_sec has landed for sc7280
(https://review.coreboot.org/c/qc_blobs/+/51941), we can start using
it instead of the sc7180 placeholders.
BUG=b:182963902
BRANCH=None
TEST=emerge-herobrine coreboot
Change-Id: I5d1014287238d383ef6cd186888845eba0f69750
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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This commit includes makefile cleanup to exclude common source file
compilation in each stage by using all-y flag.
BUG=b:182963902
TEST=trogdor validated on limozeen
Change-Id: I48464567974a0729c1c6b6157bcce4fac39a8b38
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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This patch removes the prog_locate() call for all instances of loading
payload formats (SELF and FIT), as the previous patch did for stages.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I582b37f36fe6f9f26975490a823e85b130ba49a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49336
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes the prog_locate() step for stages and rmodules.
Instead, the stage and rmodule loading functions will now perform the
locate step directly together with the actual loading. The long-term
goal of this is to eliminate prog_locate() (and the rdev member in
struct prog that it fills) completely in order to make CBFS verification
code safer and its security guarantees easier to follow. prog_locate()
is the main remaining use case where a raw rdev of CBFS file data
"leaks" out of cbfs.c into other code, and that other code needs to
manually make sure that the contents of the rdev get verified during
loading. By eliminating this step and moving all code that directly
deals with file data into cbfs.c, we can concentrate the code that needs
to worry about file data hashing (and needs access to cbfs_private.h
APIs) into one file, making it easier to keep track of and reason about.
This patch is the first step of this move, later patches will do the
same for SELFs and other program types.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia600e55f77c2549a00e2606f09befc1f92594a3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49335
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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making the symbols common accross targets to avoid duplicates for each soc.
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: Ic60f46891dfadc7db5ece02756cb449aacdd63c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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This patch changes the memlayout macro infrastructure so that the size
of a region "xxx" (i.e. the distance between the symbols _xxx and _exxx)
is stored in a separate _xxx_size symbol. This has the advantage that
region sizes can be used inside static initializers, and also saves an
extra subtraction at runtime. Since linker symbols can only be treated
as addresses (not as raw integers) by C, retain the REGION_SIZE()
accessor macro to hide the necessary typecast.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ifd89708ca9bd3937d0db7308959231106a6aa373
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<'
Change-Id: I78f8e115a54f869b990950a1c7d686e0f25033c8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Generated with a variant of
https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci
Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ie71cc6f79db9f2d722f9931e887f309e0bc9ce0b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50533
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Idd93ed91e854c8775cbcf721e4e332aef7b36e42
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50530
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ibb4bf488d9398240bf54f12b5b90d0f2a5a9119b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50196
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I960870fabde1dacfe52a8a35c253b0bd097d3e10
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file()
to cbfs_map() and cbfs_load() respectively. This is supposed to be the
start of a new, better organized CBFS API where the most common
operations have the most simple and straight-forward names. Less
commonly used variants of these operations (e.g. cbfs_ro_load() or
cbfs_region_load()) can be introduced later. It seems unnecessary to
keep carrying around "boot" in the names of most CBFS APIs if the vast
majority of accesses go to the boot CBFS (instead, more unusual
operations should have longer names that describe how they diverge from
the common ones).
cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly
reap mappings when desired. A few new cbfs_unmap() calls are added to
generic code where it makes sense, but it seems unnecessary to introduce
this everywhere in platform or architecture specific code where the boot
medium is known to be memory-mapped anyway. In fact, even for
non-memory-mapped platforms, sometimes leaking a mapping to the CBFS
cache is a much cleaner solution than jumping through hoops to provide
some other storage for some long-lived file object, and it shouldn't be
outright forbidden when it makes sense.
Additionally, remove the type arguments from these function signatures.
The goal is to eventually remove type arguments for lookup from the
whole CBFS API. Filenames already uniquely identify CBFS files. The type
field is just informational, and there should be APIs to allow callers
to check it when desired, but it's not clear what we gain from forcing
this as a parameter into every single CBFS access when the vast majority
of the time it provides no additional value and is just clutter.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is
enabled by default. Some older chipsets with insufficient SRAM/CAR space
still have it explicitly disabled. All others get the new section added
to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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"Die()" needs <console/console.h>.
Change-Id: I250988d77b0b0a093a1d116bea44a0cbb84189dd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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"printk()" needs <console/console.h>.
Change-Id: Iac6b7000bcd8b1335fa3a0ba462a63aed2dc85b8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Currently the decision of whether or not to use mrc_cache in recovery
mode is made within the individual platforms' drivers (ie: fsp2.0,
fsp1.1, etc.). As this is not platform specific, but uses common
vboot infrastructure, the code can be unified and moved into
mrc_cache. The conditions are as follows:
1. If HAS_RECOVERY_MRC_CACHE, use mrc_cache data (unless retrain
switch is true)
2. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_BOOTBLOCK, this
means that memory training will occur after verified boot,
meaning that mrc_cache will be filled with data from executing
RW code. So in this case, we never want to use the training
data in the mrc_cache for recovery mode.
3. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_ROMSTAGE, this
means that memory training happens before verfied boot, meaning
that the mrc_cache data is generated by RO code, so it is safe
to use for a recovery boot.
4. Any platform that does not use vboot should be unaffected.
Additionally, we have removed the
MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config because the
mrc_cache driver takes care of invalidating the mrc_cache data for
normal mode. If the platform:
1. !HAS_RECOVERY_MRC_CACHE, always invalidate mrc_cache data
2. HAS_RECOVERY_MRC_CACHE, only invalidate if retrain switch is set
BUG=b:150502246
BRANCH=None
TEST=1. run dut-control power_state:rec_force_mrc twice on lazor
ensure that memory retraining happens both times
run dut-control power_state:rec twice on lazor
ensure that memory retraining happens only first time
2. remove HAS_RECOVERY_MRC_CACHE from lazor Kconfig
boot twice to ensure caching of memory training occurred
on each boot.
Change-Id: I3875a7b4a4ba3c1aa8a3c1507b3993036a7155fc
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46855
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Work on this SoC was abandoned and never finished. It's not really
usable in its current state, so let's get rid of it.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I23453e3e47ac336ab61687004470e5e79172cafe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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NOC errors detected at runtime in AOP SRAM region
strongly suggested speculative memory accesses were occurring
in memory regions that either don't exist or are device memory
rather than SRAM.
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Change-Id: I6611dc614c80063c7df057b59337417c8f56fd9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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With Innolux panel timings, the fetch_start has evaluated to be more than
v_total which is invalid. Add a check to accommodate the extra h_total addition
in fetch_start calculation. Secondly, made the prefill line requirement
same as Kernel driver.
Change-Id: If7624c0b28421759fdf47dd92f23214a78058199
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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two different modem regions wifi and lte to be handled in QC_SEC and modem
Change-Id: Ib4592ca66d3d0db4c4768be4cd27422fe9f786b8
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Enable caching of memory training data for recovery as well as normal
mode because memory training is taking too long in recovery as well.
This required creating a space in the fmap for RECOVERY_MRC_CACHE.
BUG=b:150502246
BRANCH=None
TEST=Run power_state:rec twice on lazor. Ensure that on first boot,
memory training occurs and on second boot, memory training is
skipped.
Change-Id: Id9059a8edd7527b0fe6cdc0447920d5ecbdf296e
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46651
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds some Kconfig hints to make it clearer that the
USE_QC_BLOBS option is required for SC7180 boards and guide the user in
the right direction through menuconfig. Also add those little arrows to
the Trogdor board options that are there on most other boards.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I973cae8026a229408a1a1817c4808b0266387ea7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philip Chen <philipchen@google.com>
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This patch enables bootblock compression on SC7180. In my tests, that
makes it boot roughly 10ms faster (which isn't much, but... might as
well take it).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ibbe06eeb05347cc77395681969e6eaf1598b4260
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45855
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, trogdor devices have a section RO_DDR_TRAINING that is used
to store memory training data. Changing so that we reuse the same
mrc_cache API as x86 platforms. This requires renaming
RW_DDR_TRAINING to RW_MRC_CACHE and removing RO_DDR_TRAINING in the
fmap table.
BUG=b:150502246
BRANCH=None
TEST=FW_NAME="lazor" emerge-trogdor coreboot chromeos-bootimage
Make sure that first boot after flashing does memory training
and next boot does not.
Boot into recovery two consecutive times and make sure memory
training occurs on both boots.
Change-Id: I16d429119563707123d538738348c7c4985b7b52
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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LIMITS_CFG is not used/required by trogdor. Supporting this requires an FMAP
partition as well as code, removing this support saves space and maintenance
headaches.
Change-Id: I9f57f5b520599ba6d708c91df9851e0e86b4b6c0
Signed-off-by: Manideep Kurumella <mkurumel@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45704
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: If76502ff91896959ef171c192b4fc138dff18fc6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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add WATCHDOG_TOMBSTONE in memlayout.ld
Change-Id: I57ece39ff3d49f2bab259cbd92ab039a49323119
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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As the UART clock frequency is no longer required by the UART
driver, remove the unwated frequency.
Tested: Compile and boot up testing.
Change-Id: I137682b3ca45481ad34ac8ddb5cd308444f752a7
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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To achieve 115200 baudrate QcLib reconfigures UART frequency
with the lowest supported frequency from QUP clock table.
With this console logs were getting corrupted at qclib stage.
In ChromeOS coreboot, baudrate is configuarable using Kconfig.
QcLib should not assume the baudrate and reconfigure any UART
register once after the configuration is done in coreboot.
To fix the issue QcLib done the changes to not to reconfigure
any UART registers. Hence clock_configure_qup() is not required
in coreboot UART driver.
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Change-Id: I2531b64eddfa6e877f769af0d17be61f5e4d0c35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The UART index is never negative, so make it unsigned and drop the
checks for the index to be non-negative.
Change-Id: I64bd60bd2a3b82552cb3ac6524792b9ac6c09a94
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add sc7180 display hardware pipeline programming support
and invoke the display initialization from soc_init.
Changes in V1:
- added display init required check.
- added edid read function using i2c communication.
- added sn65dsi86 bridge driver to init bridge.
- moved display initialization to mainboard file.
Changes in V2:
- moved diplay init sequence to mainboard file
- moved edid read function to bridge driver.
- calculated timing paramters using edid parameters.
- removed command mode config code.
- moved bridge driver to drivers/ti.
- seperated out bridge and soc code with mainboard file as interface.
Changes in V3:
- add GPIO selection at runtime based on boardid.
- add vbif register struct overlay.
Changes in V4:
- update gpio config for lazor board.
Change-Id: I7d5e3f1781c48759553243abeb3d694f76cd008e
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This change adds support for sc7180 dsi interface host programming.
Changes in V1:
- remove dual dsi config code.
- update register access using struct overlays.
- remove dsc config & command mode code.
Changes in V2:
- remove dsi read and write functions.
- remove target and panel related code.
Changes in V3:
- move prototypes to headers.
- define macros for constants.
Changes in V4:
- define register bits instead of hardcoded values.
Change-Id: Ie64354ce8bc2a64b891fb9478fbca38d6ec4c321
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Developer/Reviewer, be aware of this patch from Napali:
https://review.coreboot.org/c/coreboot/+/28014/44
Change-Id: Ia961ee0e30478e21fd786ce464655977449df510
Signed-off-by: Ashwin Kumar <ashk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Adds basic headers as well as source required for display
dsi 10nm phy & pll programming.
Changes in V1:
- add struct overlays to model hardware registers.
- remove typedef structures.
- remove dead code such as dual dsi,split config etc.
Changes in V2:
- remove panel related header files.
- update the bitclock calculation using edid parameters.
- add phy timing calculation function.
- update copyright license.
Changes in V3:
- update the mdss clock structure.
- remove dsi_phy_configinfo_type struct.
- remove unused struct fields.
Changes in V4:
- update clock apis.
- remove unused structures.
Change-Id: I8ff400922ae594f558cf73a5aaa433a3a93347c2
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Add support for display external clock in coreboot for SC7180.
Tested: Display clocks are configured.
Change-Id: Ida222890252b80db738fa1f685b212b3f7c6e689
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: I49008ea9bc6254c745352b2e8ee965ddc2e8e5e4
Signed-off-by: Ashwin Kumar <ashk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Following blobs will includes with SoC makefile:
* AOP
* BOOT
* QTISECLIB
* QCSEC
* QUPV3FW
Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1
Signed-off-by: Ashwin Kumar <ashk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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BOOTBLOCK_CONSOLE is already set to yes in console/Kconfig file.
Change-Id: I2a4ee517795bc7b378afc5eae92e2799ad36111b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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Change-Id: I6afea5c102299e570378a1656d3dcd329a373399
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44093
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4fa03c4576bb0256b73f1d36ca840e120b750a74
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I3037edf89c933f4f136ca61d6a5bce41126ec6b9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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