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path: root/src/soc/qualcomm/sc7280/include
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2023-02-08soc/qualcomm/sc7280: init eMMCShelley Chen
Use common sdhci driver in coreboot to initialize eMMC for sc7280. This should allow us to initialize eMMC earlier in the boot process, taking it out of the critical path. BUG=b:254092907 BRANCH=None TEST=emerge-herobrine coreboot chromeos-bootimage Change-Id: Ifa88da500e82b44d7523f2e68763e01399c89f4d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71829 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21treewide: Remove duplicated includesElyes Haouas
<types.h> provides <commonlib/bsd/cb_err.h>, <stdint.h> and <stddef.h>. Change-Id: I966303336e604b1b945df77e5d4c3cccbf045c56 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-12-13soc/qualcomm/sc7280: Add API to differentiate PRO and NON_PRO SKUsSudheer Kumar Amrabadi
The API socinfo_pro_part() returns 1 for Pro and 0 for NON_PRO SKUs. To reduce the binary footprint for chipinfo structure, change its members range from uint32_t to uint16_t. Add helper functions for reading and matching jtagid. Modified socinfo_modem_supported() API to utilize helper functions. BUG=b:248187555 TEST=Validate boards are detected correctly on PRO and NON_PRO SKUs Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Change-Id: Id9f23696384a6c1a89000292eafebd8a16c273ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/68384 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-14soc/qualcomm/sc7280: Add SocInfo support in corebootTaniya Das
Add support for SocInfo in coreboot. The API socinfo_modem_supported is added to help to differentiate between LTE and WiFi SKUs. BUG=b:232302324 TEST=Validate boards are detected correctly on LTE and Wifi SKUs Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Change-Id: I61047ad49772c3796ba403cafde311ad184a4093 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-08-03qualcomm/sc7280: Add support for edp and mdp driverVinod Polimera
- Add support for edp aux read and write. - Update edp panel properties based on edid read. - Configure edp controller and edp phy. Panel details: Manufacturer: SHP Model 1523 Serial Number 0 Made week 53 of 2020 EDID version: 1.4 Digital display 8 bits per primary color channel DisplayPort interface Maximum image size: 31 cm x 17 cm Gamma: 220% Check DPMS levels Supported color formats: RGB 4:4:4 Default (sRGB) color space is primary color space First detailed timing is preferred timing Supports GTF timings within operating range Established timings supported: Standard timings supported: Detailed timings Hex of detail: 5a8780a070384d403020350035ae10000018 Detailed mode (IN HEX): Clock 346500 KHz, 135 mm x ae mm 0780 07b0 07d0 0820 hborder 0 0438 043b 0440 0485 vborder 0 -hsync -vsync Did detailed timing Hex of detail: 653880a070384d403020350035ae10000018 Detailed mode (IN HEX): Clock 144370 KHz, 135 mm x ae mm 0780 07b0 07d0 0820 hborder 0 0438 043b 0440 0485 vborder 0 -hsync -vsync Hex of detail: 000000fd003090a7a7230100000000000000 Monitor ranges (bare limits): 48-144Hz V, 167-167kHz H, max dotclock 350MHz Hex of detail: 000000fc004c513134304d314a5734390a20 Monitor name: LQ140M1JW49 Changes in V2: - Remove Misc delays in edp code. - Move mdss soc code to disp.c - Update EDID read using I2C write & read. Changes in V3: - Remove unrelated delays. - Misc changes. BUG=b:182963902,b:216687885 TEST=Validated on qualcomm sc7280 development board. Monitor name: LQ140M1JW49 Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Change-Id: If89abb76028766b19450e756889a5d7776106f95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-08-01soc/qualcomm/sc7280: Enable PCIe driverPrasad Malisetty
Enable PCIe functionality on sc7280 and supply all the needed data for PCIe generic platform driver. BUG=b:182963902,b:216686574,b:181098581 TEST=Verified on Qualcomm sc7280 development board with NVMe card (Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is getting detected in response to 'storage init' command in depthcharge CLI prompt. Output logs: ->dpch: storage init Initializing NVMe controller 1e0f:0001 Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0 * 0: NVMe Namespace 1 1 devices total Also verified NVMe boot path, that is depthcharge is able to load the kernel image from NVMe storage. Change-Id: I1f79a0ae2dea594d6026d55a15978eeb92a8ff18 Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com> Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66148 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-02herobrine: fix emmc and sd card clocksShelley Chen
Found an issue where emmc and sd clocks were being misconfigured due to using incorrect integer values when called instead of the defined enums. Fixing by splitting the clock_configure_sdcc() function into two (sdcc1 and sdcc2) as there was no commonality between the two cases anyway. As a result, we can also get rid of the clk_sdcc enum. BUG=b:198627043 BRANCH=None TEST=build herobrine image and test in conjunction with CB:63289 make sure assert is not thrown. Change-Id: I68f9167499ede057922135623a4b04202f4da9b5 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-17qualcomm/sc7280: Add display external clock support in corebootTaniya Das
Add support for EDP (Embedded DisplayPort) clocks in coreboot. This change supports the configuration and enablement of EDP PIXEL, LINK, LINK_INTF and AUX clocks. BUG=b:182963902,b:216687885 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Change-Id: Ia6872ede515401e95ea2dadc9766e3e70fb66144 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59611 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-29sc7280: Add support for USBRavi Kumar Bokka
Adding USB addressmap for sc7280. Use common USB driver for sc7280. BUG=b:182963902 TEST=Validated USB enumeration on qcom sc7280 development board Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Change-Id: Ib92b74c8035a8c0148a9aa48e7870b261b832a33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-15sc7280: Add CPUCP firmware supportRavi Kumar Bokka
CPUCP is CPUSS Control Processor. It refers to the firmware for control CPUSS active power management. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-07sc7280: Add SHRM firmware supportRavi Kumar Bokka
SHRM is a system hardware resource manager. It is used to manage run time DDRSS activities. DDRSS stands for DDR subsystem. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board by trying DDR clocks which through SHRM RSI command. Change-Id: I44484573a829eaefbd34907c6fe78d427506a762 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-21sc7280: Refactor QUP driverRajesh Patil
Enable common qup driver in sc7280 BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I0e9049557ff63898037210e72333e1739ab62413 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-16mainboard/google: Update the TLMM registers for sdhcShaik Sajida Bhanu
Update the TLMM register values for eMMC and SD card on Trogdor, Herobrine and Mistral boards. BUG=b:196936525 TEST=Validated on qualcomm sc7280 and sc7180 development board and checked basic boot up. Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Change-Id: Iccdb7757027c6de424a82e4374bad802501ac83c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57450 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03sc7280: Refactor QSPI driverRoja Rani Yarubandi
Refactor Qcom QSPI driver to separate common and SoC specific driver code. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: Ibe1dc3fe8bd71957ff8604ef4c9d97963100ccfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/55322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03qualcomm/sc7280: Move to use common clock driver for sc7280Taniya Das
It supports the clock consumers for QUP, SDCC, PCIE, Display to be able to configure & enable the desired clocks. The clock driver also supports reset of subsystems like AOP and SHRM. Also add support for Zonda PLL enable for CPU in common clock driver. Refactor the SC7280 clock driver to use the common clock driver APIs. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: I590a93cda0d6eccb51b54692b620d43ccacede77 Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50580 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-22soc/qualcomm: move uart_bitbang UART w/gpio code to commonRavi Kumar Bokka
BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: Ic6c70f917a59e233f6ea518d9c39f73fe84991c3 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47284 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21soc/qualcomm/sc7280: Replace gpio offset value with macroTaniya Das
Use the gpio offset macro instead of a constant value. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Taniya Das <tdas@codeaurora.org> Change-Id: Ia9e4b9ca7216092665f0a06ce467da01963c2364 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-06-11sc7280: Add target specific GPIO pin definitionsTaniya Das
Add GPIO pin details specific to SC7280 chipset for the consumers to be able to request for the gpio functionality as per their requirement. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Taniya Das <tdas@codeaurora.org> Change-Id: I63bcaed78a6eeb0e6fad857b89d40181613e50cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/55077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-04-15sc7280: Provide initial SoC supportRavi Kumar Bokka
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
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