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2024-04-11tree: Drop unused <edid.h>Elyes Haouas
Change-Id: I66265727b68b6ad10722439314b466298dbfff28 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81821 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-03-30soc/qualcomm: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: If2c2138ed3dc437b924297330805caa8c357853d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81460 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18soc: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ie7bc4f3ae00bb9601001dbb71e7c3c84fd4f759a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80596 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-31include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard
Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-24soc/*: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6f502b97864fd7782e514ee2daa902d2081633a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80074 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-17tree: More use accessor functions for struct region fieldsNico Huber
Always use the high-level API region_offset() and region_sz() functions. This excludes the internal `region.c` code as well as unit tests. FIT payload support was also skipped, as it seems it never tried to use the API and would need a bigger overhaul. Change-Id: I18f1e37a06783aecde9024c15876b67bfeed70ee Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-18qualcomm/sc7180: Move QCSDI and increase romstage size by 4KBJulius Werner
We need to increase romstage size a little to make a compiler upgrade fit (CB:70771). Unfortunately the end of the romstage directly touches the QCSDI region in the current memlayout, and there is no other way to reshuffle things to make more space... so we need to move QCSDI out of the way. This means that anyone who is actually building this platform with CONFIG_QC_SDI_ENABLE (which requires a proprietary blob that's not publicly available) will need to recompile their QCSDI binary to match the new start address. Change-Id: Iaf13e4001b3c763e3ec59009779931ec75603d5d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79074 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-17soc/qualcomm/{sc7180,sc7280}: Allow building without QC blobs repoFelix Singer
Building coreboot for the Qualcomm SoCs SC7180 and SC7280 requires to include the Qualcomm blobs, which requires to accept their license. However, for various reasons it makes sense to build without blobs, e.g. static analysis or just build-testing. So in order to do that, run the steps integrating the Qualcomm blobs into the coreboot binary only if USE_QC_BLOBS is enabled and also remove guards which prevent building related mainboards when USE_QC_BLOBS is not enabled. Change-Id: I249ac477b8f10e7fa0848e967c23a3b3b9bbd27d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79026 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-15soc/qualcomm/{sc7180,sc7280}: Use correct return types for functionsZebreus
Some functions in the headers for sc7180 and sc7280 specified the int as their return type when they should have used enum cb_err. Found while testing GCC 13.2.0 Change-Id: I41331fe708a396f7f2f40359e8ba03c8a46a4d4b Signed-off-by: Zebreus <lennarteichhorn@googlemail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-05-12soc/qualcomm/sc7180: Fix set but unused variablesArthur Heymans
This fixes clang warnings. Change-Id: I407da6ec05ef646f61bd81e314fee1b5ea659192 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74557 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-03-17qualcomm/common: Pass FMAX_LIMIT flag for Lazor board to QcLibSudheer Kumar Amrabadi
This patch passes a hint flag to QcLib on Lazor boards to tell it to limit the DDR frequency for certain memory parts (8GB Hynix) to work around a board-specific stability issue. BRANCH=trogdor BUG=b:267387867 TEST=Validated on qualcomm sc7180 development board Change-Id: I45915cf93d2a57ff0c9710f2ac36dfb665eff1c6 Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org> Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2023-02-24Revert "soc/qualcomm: Increase SPI frequency to 75 MHz"Shelley Chen
This reverts commit 363202b43589ec240c4a0c8f5b449fbd5c1333f8. Reason for revert: Seeing some bit flips on the SPI bus, but cannot repro reliably on local builds. Going to downgrade back to 50 MHz to see if builder builds are more stable on each variant as a result. Signed-off-by: Shelley Chen <shchen@google.com> Change-Id: I4fe76bac915e3b3c794821cd160a66824e38ea83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73214 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11treewide: stop calling custom TPM log "TCPA"Sergii Dmytruk
TCPA usually refers to log described by TPM 1.2 specification. Change-Id: I896bd94f18b34d6c4b280f58b011d704df3d4022 Ticket: https://ticket.coreboot.org/issues/423 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-11-18cbmem_top_chipset: Change the return value to uintptr_tElyes Haouas
Get rid of a lot of casts. Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-10-31soc: Add SPDX license headers to MakefilesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic875708697f07b6dae09d27dbd67eb8b960749f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-07-04soc/qualcomm/sc7180: Update hardware watchdog loggingKshitiz Godara
Move watchdog functionality to common folder. BUG=b:221393157 TEST=None Signed-off-by: Kshitiz Godara <quic_kgodara@quicinc.com> Change-Id: Ib2f7f21ce991fd8193329e7b8260e58e47bf39c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-06-30soc/qualcomm: Do resource transitionKyösti Mälkki
For ipq806x this fixes two resources getting declared with same index. The latter previously overwrote former. Change-Id: Ifee321d930d5433c824e2e977f1bb455766582f0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-27soc/qualcomm: Make sc7180 mdss configurations common codeVinod Polimera
This change makes mdss configuration common for both sc7180 & sc7280 to avoid code duplicacy. Changes in v2: - Move soc related mdss changes to soc specific disp.c BUG=b:182963902,b:216687885 TEST=Validated on qualcomm sc7280 development board. Monitor name: LQ140M1JW49 Change-Id: Ibc43ab6ee5ced08e34625e1485febd2f4717d6a0 Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-06-24sc7180/sc7280: Add missing set_resourcesKshitiz Godara
Added missing set_resources function to avoid error messages in boot up logs. BUG=b:230576402 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Kshitiz Godara <quic_kgodara@quicinc.com> Change-Id: Ie0a5bd345486293ce07e586a423d53740ad377f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-06-22device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki
There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-01sc7180: Trogdor to support 2 dcbSudheer Kumar Amrabadi
BUG=b:227946776 TEST=Validated on sc7180 Lazor board Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com> Change-Id: Ie4d7f7f0b24aee06ffb272b21b74fea4160fe87c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-05-31soc/qualcomm: Increase SPI frequency to 75 MHzShelley Chen
Increase frequency of sc7280 to 75 MHz. Setting the delay to 1/8 of a cycle as a result of experimentation. BUG=b:190231148 BRANCH=None TEST=Make sure that herobrine board boots HW Engineer measured SPI frequency and verified running at 75 MHz Signed-off-by: Shelley Chen <shchen@google.com> Change-Id: I3cf5a7c85f12800a11ece397a354349f2a0a235f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64673 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-24soc/qualcomm: Remove unused <timer.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <timer.h>' -- src/) <(git grep -l 'NSECS_PER_SEC\|USECS_PER_SEC\|MSECS_PER_SEC\|USECS_PER_MSEC\|mono_time\|microseconds\|timeout_callback\|expiration\|timer_monotonic_get\|timers_run\|timer_sched_callback\|mono_time_set_usecs\|mono_time_set_msecs\|mono_time_add_usecs\|mono_time_add_msecs\|mono_time_cmp\|mono_time_after\|mono_time_before\|mono_time_diff_microseconds\|stopwatch\|stopwatch_init\|stopwatch_init_usecs_expire\|stopwatch_init_msecs_expire\|stopwatch_tick\|stopwatch_expired\|stopwatch_wait_until_expired\|stopwatch_duration_usecs\|stopwatch_duration_msecs\|wait_us\|wait_ms' -- src/) Change-Id: Ibc08ea20263623159c78b634d34899ac7da0d3c6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-14soc/qualcomm/common: Make clock_configure() check for exact matchesShelley Chen
Previously, clock_configure() will configure the clocks to round up to the next highest frequency bin. This seems non-intuitive. Changing the logic to find an exact frequency match and will halt booting if no match is found. Recently fixed a bug in CB:63311, where the clock was being set incorrectly for emmc and was able to find it because of this stricter check. BUG=b:198627043 BRANCH=None TEST=build herobrine image and try to set SPI frequency to number not supported. Ensure device doesn't boot. Change-Id: I9cfad7236241f4d03ff1a56683654649658b68fc Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-03-09commonlib/bsd: Remove cb_err_tJulius Werner
cb_err_t was meant to be used in place of `enum cb_err` in all situations, but the choice to use a typedef here seems to be controversial. We should not be arbitrarily using two different identifiers for the same thing across the codebase, so since there are no use cases for serializing enum cb_err at the moment (which would be the primary reason to typedef a fixed-width integer instead), remove cb_err_t again for now. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-12sc7180: Update video mode active horizontal/vertical/total calculationsVinod Polimera
Remove vbp & hbp as the names are misleading and use edid variables to simplify the video mode active and total calculations. Change-Id: I9ccafabe226fa53c6f82e32413d4c00a0b4531be Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-10src/soc/qualcomm: Remove unused <delay.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <delay.h>' -- src/) <(git grep -l 'get_timer_fsb(\|init_timer(\|udelay(\|mdelay(\|delay(' -- src/) |grep "<" Change-Id: Id1e0f4cb9f6181dc2fc45e7b6cb149646111bb3e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-10src/soc/qualcomm: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: I9097972080499bd61981fe738be93f7b193f5813 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-08sc7180: Increase bootblock size and add pre-RAM TCPA bufferJulius Werner
In order to make SC7180 boards compatbile with some optional Kconfigs, increase the bootblock size a bit and add room for a TCPA log buffer to memlayout. The large pre-RAM CBFS cache wasn't really needed anymore anyway since we switched QcLib to use LZ4 compression. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I7321cca9d7b79368115c57f156b8e71657802a41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-01-01src: Drop duplicated includesElyes HAOUAS
<types.h> already provides <commonlib/bsd/cb_err.h>, <limits.h>, <stdbool.h>, <stdint.h> and <stddef.h> headers. Change-Id: I700b3f0e864ecce3f8b3b66f3bf6c8f1040acee1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-29soc/qualcomm/common/usb: Add support for common USB driverSandeep Maheswaram
Add common USB driver for qualcomm soc sc7180 and sc7280. This includes dwc3 controller, qmp ss phy, qusb hs phy and snsp hs phy. BUG=b:182963902 TEST=Validated USB enumeration on qcom sc7180 and sc7280 development board Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Change-Id: I1013ded22855286220cfa747cb25418070fe85a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-25soc/qualcomm: Commonize AOP firmware supportRavi Kumar Bokka
Move AOP firmware support from qualcomm/sc7180 into qualcomm/common BUG=b:182963902 TEST=Validated on qualcomm sc7180 development board Change-Id: I90b0f48e15df390970e027bff2065b7a89b14cec Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-23soc/qualcomm/common: Move UART SC7180 driver to common sectionRajesh Patil
Move existing UART driver from sc7180 to common folder. This implements UART driver for QCOM SoC's BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I7bc2d3765f956e04bae3e45c3a9b9e2ad424c7b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-21soc/qualcomm/common/spi: Add support for SPI common driverRavi Kumar Bokka
This implements qup spi driver for qualcomm chipsets Rename header file names for trogdor to prevent breakage. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I2f2b25b6661fcd518f70383da0c7788c5269c97b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55953 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-21soc/qualcomm/common/i2c: Add support for I2C common driverRajesh Patil
copy existing I2C driver from /soc/qualcomm/sc7180 to common folder. This implements i2c driver for qualcomm chipsets BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I16e6fc2c1c24b9814d1803bffd5cfbb657201cfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/55952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-16mainboard/google: Update the TLMM registers for sdhcShaik Sajida Bhanu
Update the TLMM register values for eMMC and SD card on Trogdor, Herobrine and Mistral boards. BUG=b:196936525 TEST=Validated on qualcomm sc7280 and sc7180 development board and checked basic boot up. Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Change-Id: Iccdb7757027c6de424a82e4374bad802501ac83c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57450 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16soc/qualcomm: clock: Clean up clock driverTaniya Das
Updated return type as CB_SUCCESS and aligned indentation. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Taniya Das <tdas@codeaurora.org> Change-Id: Ifabe0508a37a841779965f4e38172f680e18d38a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-16soc/qualcomm/common/qup: Add support for QUP common driverRavi Kumar Bokka
copy existing QUP driver from /soc/qualcomm/sc7180 to common folder. This QUP common driver provide QUP configurations, GPI and SE firmware loading and initializations. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I95a0fcf97b3b3a6ed26e62b3084feb4a2369cdc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-11mipi: Make panel init callback work directly on DSI transaction typesJulius Werner
Our MIPI panel initialization framework differentiates between DCS and GENERIC commands, but the exact interpretation of those terms is left to the platform drivers. In practice, the MIPI DSI transaction codes for these are standardized and platforms always need to do the same operation of combining the command length and transfer type into a correct DSI protocol code. This patch factors out the various platform-specific DSI protocol definitions into a single global one and moves the transaction type calculation into the common panel framework. The Qualcomm SC7180 implementation which previously only supported DCS commands is enhanced to (hopefully? untested for now...) also support GENERIC commands. While we're rewriting that whole section also fix some other issues about how exactly long and short commands need to be passed to that hardware which we identified in the meantime. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I09ade7857ca04e89d286cf538b1a5ebb1eeb8c04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-09-03soc/qualcomm/common/qspi: Add support for common QSPI driverRavi Kumar Bokka
copy existing QSPI driver from /soc/qualcomm/sc7180 to common folder. This common QSPI driver works in master mode and provides read/write operation for the slave devices like flash. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I5b3816b823e14db1dd13f1eb4a6761c7a61604b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03soc/qualcomm/common: clock: Add support for common clock driverTaniya Das
The clock driver supports configuring the general purpose PLLs, configuring the root clock generator (RCG), enable clock branch, enable gdsc and also the block resets. The common clock driver exposes PLL configuration functions and also different Agera PLL enable functions for the CPU PLLs. While at it, the common driver also supports reset of subsystems like AOP and SHRM. SC7180 clock driver is also refactored to use the common clock driver APIs. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Change-Id: I03d1b4a2fb90303c7259ec08f312d78b4e33ec39 Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03qualcomm/sc7180: Clean up drivers with common clockTaniya Das
As we move to use the common clock driver, the sc7180 clock driver, watchdog and display drivers requires few cleanups, thus update the impacted drivers. Earlier the display client is expected to provide 2n divider value, as the divider value in register is in form "2n-1". mdss_clk_cfg.div = half_divider ? (half_divider - 1) : 0; The older convention in the upcoming patches would be replaced with the common macro of QCOM_CLOCK_DIV, thus need the divider needs to be updated. mdss_clk_cfg.div = half_divider ? QCOM_CLOCK_DIV(half_divider) : 0; To accommodate impacting the functionality, the half_divider is taken care in the clock driver. BUG=b:182963902 TEST=Validated on qualcomm sc7180 development board Change-Id: Ic334fd0d43e5b4b1e43a27d5db7665f0bc151d66 Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-08-26device/mipi: Move to drivers/mipiJulius Werner
Sounds like we prefer to have this under drivers/ instead of device/. Also move all MIPI-related headers out from device/ into their own directory. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib3e66954b8f0cf85b28d8d186b09d7846707559d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-20qualcomm/sc7180: Switch to common MIPI panel libraryJulius Werner
This patch changes the sc7180 boards to use the new common MIPI panel framework, which allows more flexible initialization command packing and sharing panel definitions between boards. (I'm taking the lane count control back out again for now, since it seems we only ever want 4 for now anyway, and if we ever have a need for a different lane count it's not clear whether that should be a property of the board or the panel or both. Better to leave that decision until we have a real use case.) Also, the code was not written to deal with DCS commands that were not a length divisible by 4 (it would read over the end of the command buffer). The corresponding kernel driver seems to pad the command with 0xff instead, let's do the same here. (Also increase the maximum allowed command length to 256 bytes, as per Qualcomm's recommendation.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I78f6efbaa9da88a3574d5c6a51061e308412340e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56966 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-03sc7180: Add display support for mipi panelsVinod Polimera
- configure TROGDOR_HAS_MIPI_PANEL to "n" by default, it can be updated for mipi panels. - add simple rm69299 panel as an example to append new mipi panels. - use existing edid struct to update mipi panel parameters. - add dsi command tx interface for mipi panel on commands. Change-Id: Id698265a4e2399ad1c26e026e9a5f8ecd305467f Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52662 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02helpers: Add GENMASK macroYu-Ping Wu
The GENMASK is defined in multiple files (with various names such as MASKBIT), which sets certain consecutive bits to 1 and leaves the others to 0. To avoid duplicate macros, add GENMASK macro to helpers.h. GENMASK(high, low) sets bits from `high` to `low` (inclusive) to 1. For example, GENMASK(39, 21) gives us the 64-bit vector 0x000000ffffe00000. Remove duplicate macro definitions. Also utilize GENMASK for _BF_MASK in mmio.h. BUG=none TEST=make tests/commonlib/bsd/helpers-test TEST=emerge-cherry coreboot BRANCH=none Change-Id: If2e7c4827d8a7d27688534593b556a72f16f0c2b Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-22soc/qualcomm: move uart_bitbang UART w/gpio code to commonRavi Kumar Bokka
BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: Ic6c70f917a59e233f6ea518d9c39f73fe84991c3 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47284 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-22sc7180: Add target specific GPIO pin definitionsTaniya Das
The common gpio driver can be re-used for SC7180, thus remove the existing gpio driver support and also clean up the common macro definitions. Add GPIO pin details specific to SC7180 chipset for the consumers to be able to request for the gpio functionality as per their requirement. TEST=Validated on qualcomm sc7180 development board Signed-off-by: Taniya Das <tdas@codeaurora.org> Change-Id: Ifd206e6bc9a549706e7a2c4bde0b7d5527ca6268 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-07-21sc7180: Renaming the GPIO macro in QSPI and I2C driverRavi Kumar Bokka
As part of GPIO driver cleanup across qcom chipsets, GPIO_OUTPUT_ENABLE has been renamed to GPIO_OUTPUT. BUG=b:182963902 TEST=Validated on qualcomm sc7180 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I51eedc722a91c5ea8e009fb8468a60667d374b49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-04-24Coachz: Observe SPI_CLK voltage level is only 1.4V, need to adjustyolkshih
the signal integrity strength to correct voltage level 1.8V BUG=b:184714790 BRANCH=trogdor TEST=HW test Change-Id: Iee7b458b6aa7d701724da87ecdf0f993d0565c0c Signed-off-by: yolkshih <yolkshih@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wenchao Han <hanwenchao@huaqin.corp-partner.google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-04-08soc/qualcomm: move code to commonRavi Kumar Bokka
This commit includes makefile cleanup to exclude common source file compilation in each stage by using all-y flag. BUG=b:182963902 TEST=trogdor validated on limozeen Change-Id: I48464567974a0729c1c6b6157bcce4fac39a8b38 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-03-17cbfs: Remove prog_locate() for payloads (SELF and FIT)Julius Werner
This patch removes the prog_locate() call for all instances of loading payload formats (SELF and FIT), as the previous patch did for stages. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I582b37f36fe6f9f26975490a823e85b130ba49a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49336 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15sc7180: make symbols common accross multiple targets.Ravi Kumar Bokka
making the symbols common accross targets to avoid duplicates for each soc. Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: Ic60f46891dfadc7db5ece02756cb449aacdd63c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-02-19memlayout: Store region sizes as separate symbolsJulius Werner
This patch changes the memlayout macro infrastructure so that the size of a region "xxx" (i.e. the distance between the symbols _xxx and _exxx) is stored in a separate _xxx_size symbol. This has the advantage that region sizes can be used inside static initializers, and also saves an extra subtraction at runtime. Since linker symbols can only be treated as addresses (not as raw integers) by C, retain the REGION_SIZE() accessor macro to hide the necessary typecast. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ifd89708ca9bd3937d0db7308959231106a6aa373 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-16soc/qualcomm: Remove unused <string.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<' Change-Id: I78f8e115a54f869b990950a1c7d686e0f25033c8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-15src: use ARRAY_SIZE where possiblePatrick Georgi
Generated with a variant of https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15soc/qualcomm/sc7180: Remove unused <console/console.h>Elyes HAOUAS
Change-Id: Ie71cc6f79db9f2d722f9931e887f309e0bc9ce0b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50533 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15soc/qualcomm: Remove unused <console/console.h>Elyes HAOUAS
Change-Id: Idd93ed91e854c8775cbcf721e4e332aef7b36e42 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50530 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04soc/qualcomm/sc7180/aop_load_reset.c: Add missing <program_loading.h>Elyes HAOUAS
Change-Id: Ibb4bf488d9398240bf54f12b5b90d0f2a5a9119b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50196 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02cbfs: Simplify load/map API names, remove type argumentsJulius Werner
This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file() to cbfs_map() and cbfs_load() respectively. This is supposed to be the start of a new, better organized CBFS API where the most common operations have the most simple and straight-forward names. Less commonly used variants of these operations (e.g. cbfs_ro_load() or cbfs_region_load()) can be introduced later. It seems unnecessary to keep carrying around "boot" in the names of most CBFS APIs if the vast majority of accesses go to the boot CBFS (instead, more unusual operations should have longer names that describe how they diverge from the common ones). cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly reap mappings when desired. A few new cbfs_unmap() calls are added to generic code where it makes sense, but it seems unnecessary to introduce this everywhere in platform or architecture specific code where the boot medium is known to be memory-mapped anyway. In fact, even for non-memory-mapped platforms, sometimes leaking a mapping to the CBFS cache is a much cleaner solution than jumping through hoops to provide some other storage for some long-lived file object, and it shouldn't be outright forbidden when it makes sense. Additionally, remove the type arguments from these function signatures. The goal is to eventually remove type arguments for lookup from the whole CBFS API. Filenames already uniquely identify CBFS files. The type field is just informational, and there should be APIs to allow callers to check it when desired, but it's not clear what we gain from forcing this as a parameter into every single CBFS access when the vast majority of the time it provides no additional value and is just clutter. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02cbfs: Enable CBFS mcache on most chipsetsJulius Werner
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with. Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-17src: Add missing 'include <console/console.h>'Elyes HAOUAS
"Die()" needs <console/console.h>. Change-Id: I250988d77b0b0a093a1d116bea44a0cbb84189dd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-17src: Add missing 'include <console/console.h>'Elyes HAOUAS
"printk()" needs <console/console.h>. Change-Id: Iac6b7000bcd8b1335fa3a0ba462a63aed2dc85b8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-13mrc_cache: Move code for triggering memory training into mrc_cacheShelley Chen
Currently the decision of whether or not to use mrc_cache in recovery mode is made within the individual platforms' drivers (ie: fsp2.0, fsp1.1, etc.). As this is not platform specific, but uses common vboot infrastructure, the code can be unified and moved into mrc_cache. The conditions are as follows: 1. If HAS_RECOVERY_MRC_CACHE, use mrc_cache data (unless retrain switch is true) 2. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_BOOTBLOCK, this means that memory training will occur after verified boot, meaning that mrc_cache will be filled with data from executing RW code. So in this case, we never want to use the training data in the mrc_cache for recovery mode. 3. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_ROMSTAGE, this means that memory training happens before verfied boot, meaning that the mrc_cache data is generated by RO code, so it is safe to use for a recovery boot. 4. Any platform that does not use vboot should be unaffected. Additionally, we have removed the MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config because the mrc_cache driver takes care of invalidating the mrc_cache data for normal mode. If the platform: 1. !HAS_RECOVERY_MRC_CACHE, always invalidate mrc_cache data 2. HAS_RECOVERY_MRC_CACHE, only invalidate if retrain switch is set BUG=b:150502246 BRANCH=None TEST=1. run dut-control power_state:rec_force_mrc twice on lazor ensure that memory retraining happens both times run dut-control power_state:rec twice on lazor ensure that memory retraining happens only first time 2. remove HAS_RECOVERY_MRC_CACHE from lazor Kconfig boot twice to ensure caching of memory training occurred on each boot. Change-Id: I3875a7b4a4ba3c1aa8a3c1507b3993036a7155fc Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46855 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-06sc7180: Correct mmu configuration for AOP SRAM regionsT Michael Turney
NOC errors detected at runtime in AOP SRAM region strongly suggested speculative memory accesses were occurring in memory regions that either don't exist or are device memory rather than SRAM. Signed-off-by: T Michael Turney <mturney@codeaurora.org> Change-Id: I6611dc614c80063c7df057b59337417c8f56fd9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/47261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-11-02sc7180: Fix prefill requirement and correct the fetch start checkVinod Polimera
With Innolux panel timings, the fetch_start has evaluated to be more than v_total which is invalid. Add a check to accommodate the extra h_total addition in fetch_start calculation. Secondly, made the prefill line requirement same as Kernel driver. Change-Id: If7624c0b28421759fdf47dd92f23214a78058199 Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-11-02sc7180: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot.mkurumel
two different modem regions wifi and lte to be handled in QC_SEC and modem Change-Id: Ib4592ca66d3d0db4c4768be4cd27422fe9f786b8 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-10-23sc7180: enable RECOVERY_MRC_CACHEShelley Chen
Enable caching of memory training data for recovery as well as normal mode because memory training is taking too long in recovery as well. This required creating a space in the fmap for RECOVERY_MRC_CACHE. BUG=b:150502246 BRANCH=None TEST=Run power_state:rec twice on lazor. Ensure that on first boot, memory training occurs and on second boot, memory training is skipped. Change-Id: Id9059a8edd7527b0fe6cdc0447920d5ecbdf296e Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46651 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-17trogdor/sc7180: Clarify USE_QC_BLOBS requirementsJulius Werner
This patch adds some Kconfig hints to make it clearer that the USE_QC_BLOBS option is required for SC7180 boards and guide the user in the right direction through menuconfig. Also add those little arrows to the Trogdor board options that are there on most other boards. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I973cae8026a229408a1a1817c4808b0266387ea7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philip Chen <philipchen@google.com>
2020-10-13sc7180: Enable bootblock compressionJulius Werner
This patch enables bootblock compression on SC7180. In my tests, that makes it boot roughly 10ms faster (which isn't much, but... might as well take it). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ibbe06eeb05347cc77395681969e6eaf1598b4260 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45855 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-09trogdor: Modify DDR training to use mrc_cacheShelley Chen
Currently, trogdor devices have a section RO_DDR_TRAINING that is used to store memory training data. Changing so that we reuse the same mrc_cache API as x86 platforms. This requires renaming RW_DDR_TRAINING to RW_MRC_CACHE and removing RO_DDR_TRAINING in the fmap table. BUG=b:150502246 BRANCH=None TEST=FW_NAME="lazor" emerge-trogdor coreboot chromeos-bootimage Make sure that first boot after flashing does memory training and next boot does not. Boot into recovery two consecutive times and make sure memory training occurs on both boots. Change-Id: I16d429119563707123d538738348c7c4985b7b52 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-10-07sc7180: Remove LIMITS_CFG loading in romstage.mkurumel
LIMITS_CFG is not used/required by trogdor. Supporting this requires an FMAP partition as well as code, removing this support saves space and maintenance headaches. Change-Id: I9f57f5b520599ba6d708c91df9851e0e86b4b6c0 Signed-off-by: Manideep Kurumella <mkurumel@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45704 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21soc/qualcomm: Drop unneeded empty linesElyes HAOUAS
Change-Id: If76502ff91896959ef171c192b4fc138dff18fc6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-16sc7180: report hardware watchdog reset after rebootRavi Kumar Bokka
add WATCHDOG_TOMBSTONE in memlayout.ld Change-Id: I57ece39ff3d49f2bab259cbd92ab039a49323119 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-15sc7180: clock: Remove unwanted QUPv3 FrequencyTaniya Das
As the UART clock frequency is no longer required by the UART driver, remove the unwated frequency. Tested: Compile and boot up testing. Change-Id: I137682b3ca45481ad34ac8ddb5cd308444f752a7 Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-15sc7180: Remove QcLib specific changes from CB UARTRoja Rani Yarubandi
To achieve 115200 baudrate QcLib reconfigures UART frequency with the lowest supported frequency from QUP clock table. With this console logs were getting corrupted at qclib stage. In ChromeOS coreboot, baudrate is configuarable using Kconfig. QcLib should not assume the baudrate and reconfigure any UART register once after the configuration is done in coreboot. To fix the issue QcLib done the changes to not to reconfigure any UART registers. Hence clock_configure_qup() is not required in coreboot UART driver. Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Change-Id: I2531b64eddfa6e877f769af0d17be61f5e4d0c35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-12include/console/uart: make index parameter unsignedFelix Held
The UART index is never negative, so make it unsigned and drop the checks for the index to be non-negative. Change-Id: I64bd60bd2a3b82552cb3ac6524792b9ac6c09a94 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-10sc7180: Add display hardware pipe line initializationVinod Polimera
Add sc7180 display hardware pipeline programming support and invoke the display initialization from soc_init. Changes in V1: - added display init required check. - added edid read function using i2c communication. - added sn65dsi86 bridge driver to init bridge. - moved display initialization to mainboard file. Changes in V2: - moved diplay init sequence to mainboard file - moved edid read function to bridge driver. - calculated timing paramters using edid parameters. - removed command mode config code. - moved bridge driver to drivers/ti. - seperated out bridge and soc code with mainboard file as interface. Changes in V3: - add GPIO selection at runtime based on boardid. - add vbif register struct overlay. Changes in V4: - update gpio config for lazor board. Change-Id: I7d5e3f1781c48759553243abeb3d694f76cd008e Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-10sc7180: Add display dsi interface programmingVinod Polimera
This change adds support for sc7180 dsi interface host programming. Changes in V1: - remove dual dsi config code. - update register access using struct overlays. - remove dsc config & command mode code. Changes in V2: - remove dsi read and write functions. - remove target and panel related code. Changes in V3: - move prototypes to headers. - define macros for constants. Changes in V4: - define register bits instead of hardcoded values. Change-Id: Ie64354ce8bc2a64b891fb9478fbca38d6ec4c321 Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-10sc7180: enable bl31T Michael Turney
Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/28014/44 Change-Id: Ia961ee0e30478e21fd786ce464655977449df510 Signed-off-by: Ashwin Kumar <ashk@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-09sc7180: Add display 10nm phy & pll programming supportVinod Polimera
Adds basic headers as well as source required for display dsi 10nm phy & pll programming. Changes in V1: - add struct overlays to model hardware registers. - remove typedef structures. - remove dead code such as dual dsi,split config etc. Changes in V2: - remove panel related header files. - update the bitclock calculation using edid parameters. - add phy timing calculation function. - update copyright license. Changes in V3: - update the mdss clock structure. - remove dsi_phy_configinfo_type struct. - remove unused struct fields. Changes in V4: - update clock apis. - remove unused structures. Change-Id: I8ff400922ae594f558cf73a5aaa433a3a93347c2 Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-09sc7180: clock: Add display external clock in corebootTaniya Das
Add support for display external clock in coreboot for SC7180. Tested: Display clocks are configured. Change-Id: Ida222890252b80db738fa1f685b212b3f7c6e689 Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-09trogdor: Change Memlayout to increase QcLib region from 512 to 596kBAshwin Kumar
Change-Id: I49008ea9bc6254c745352b2e8ee965ddc2e8e5e4 Signed-off-by: Ashwin Kumar <ashk@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-09trogdor: SoC makefile blob supportashk
Following blobs will includes with SoC makefile: * AOP * BOOT * QTISECLIB * QCSEC * QUPV3FW Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Signed-off-by: Ashwin Kumar <ashk@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-02src: Drop redundant 'select BOOTBLOCK_CONSOLE'Elyes HAOUAS
BOOTBLOCK_CONSOLE is already set to yes in console/Kconfig file. Change-Id: I2a4ee517795bc7b378afc5eae92e2799ad36111b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-18src: Remove unused 'include <delay.h>'Elyes HAOUAS
Change-Id: I6afea5c102299e570378a1656d3dcd329a373399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44093 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18src: Remove unuse '<timestamp.h>Elyes HAOUAS
Change-Id: I4fa03c4576bb0256b73f1d36ca840e120b750a74 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-08-18src: Remove unused '<halt.h>'Elyes HAOUAS
Change-Id: I3037edf89c933f4f136ca61d6a5bce41126ec6b9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-08-03qualcomm/sc7180: Fix TLMM assignments for GPIOs 29, 31 and 32Julius Werner
According to my SC7180 reference manual, these three GPIOs are in the NORTH TLMM, but our pin table lists them as SOUTH. That means all accesses our code has been doing to them have just been hitting empty address space. BUG=b:160115694 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If9c03ac890a7975855394c2e08b8433472df204d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-07-26src/soc/qualcomm: Add include <types.h>Elyes HAOUAS
BIT(x) needs <types.h>. Change-Id: I6b89bd9616b3f091d6694f9cc20b4bd1a74aad3b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-14src: Remove unused 'include <stdint.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX' -- src/) |grep -v vendorcode |grep '<' Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41827 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14src: Remove unused 'include <types.h>'Elyes HAOUAS
Files found using: diff <(git grep -l '#include <types.h>' -- src/) <(git grep -l 'BIT(\|size_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\|MAYBE_STATIC_NONZERO\|zeroptr\|int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|bool\|true\|false\|cb_err\|CB_SUCCESS\|CB_ERR\|CB_ERR_ARG\|CB_CMOS_\|CB_KBD_\|CB_I2C_\|cb_err_t\|DIV_ROUND_CLOSEST\|container_of\|__unused\|alloca(\|ARRAY_SIZE\|ALIGN\|ALIGN_UP\|ALIGN_DOWN\|IS_ALIGNED\|__CMP_UNSAFE\|MIN_UNSAFE\|MAX_UNSAFE\|__CMP_SAFE\|__CMP\|MIN(\|MAX(\|ABS(\|IS_POWER_OF_2\|POWER_OF_2\|DIV_ROUND_UP\|SWAP(\|KiB\|MiB\|GiB\|KHz\|MHz\|GHz\|offsetof(\|check_member\|member_size' -- src/)|grep -v vendor |grep '<' Change-Id: I5d99d844cc58d80acb505d98da9d3ec76319b2eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41677 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22soc/qualcomm/sc7180/qupv3_config.c: Add missing includesElyes HAOUAS
Add <string.h> and <cbfs.h> Change-Id: I7e66a3cbf50fa27b4f6be6885b324de90eddd387 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-06-13treewide: Add Kconfig variable MEMLAYOUT_LD_FILEFurquan Shaikh
This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows SoC/mainboard to provide a linker file for the platform. x86 already provides a default memlayout.ld under src/arch/x86. With this new Kconfig variable, it is possible for the SoC/mainboard code for x86 to provide a custom linker file as well. Makefile.inc is updated for all architectures to use this new Kconfig variable instead of assuming memlayout.ld files under a certain path. All non-x86 boards used memlayout.ld under mainboard directory. However, a lot of these boards were simply including the memlayout from SoC. So, this change also updates these mainboards and SoCs to define the Kconfig as required. BUG=b:155322763 TEST=Verified that abuild with --timeless option results in the same coreboot.rom image for all boards. Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove unused '#include <timer.h>'Elyes HAOUAS
Change-Id: I57e064d26b215743a1cb06bb6605fc4fe1160876 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41491 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18src: Remove unused 'include <string.h>'Elyes HAOUAS
Unused includes found using following commande: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|atol\|strrchr\|skip_atoi\|STRINGIFY' -- src/) |grep -v vendorcode |grep '<' Change-Id: Ibaeec213b6019dfa9c45e3424b38af0e094d0c51 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-05-13src/mainboard: Remove unused 'include <stdlib.h>'Elyes HAOUAS
Found using following commande: diff <(git grep -l '#include <stdlib.h>' -- src/) <(git grep -l ' memalign\|malloc\|free' -- src/) |grep -v vendorcode |grep '<' Change-Id: Ib2ee840a10de5c10d57aa7a75b805ef69dc8da84 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41241 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11sc7180: clock: Add support to bump CPU levelsTaniya Das
Add support to configure the Silver and L3 PLLs and switch the APSS GFMUX to use the PLL to speed up the boot cores. Tested: CPU speed frequency validated for speed bump Change-Id: Iafd3b618fb72e0e8cc8dd297e4a3e16b83550883 Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-05-11sc7180: Adjust memory allocations per upstream commentsT Michael Turney
Update memory regions, etc. Change-Id: If852fe4465fb431809570be6cdccff3ad9d9f4f0 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39362 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11sc7180: Fix for hang during DMA transfer in SPI-NOR flash driversatya priya
Transfer sequence used by SPI-Flash application present in CB/DC. 1. Assert CS through GPIO 2. Data transfer through QSPI (involves construction of command descriptor for multiple read/write transfers) 3. De-assert CS through GPIO. With above sequence, in DMA mode we dont have the support for read transfers that are not preceded by write transfer in QSPI controller. Ex: "write read read read" sequence results in hang during DMA transfer, where as "write read write read" sequence has no issue. As we have application controlling CS through GPIO, we are making fragment bit "set" for all transfers, which keeps CS in asserted state although the ideal way to operate CS is through QSPI controller. Change-Id: Ia45ab793ad05861b88e99a320b1ee9f10707def7 Signed-off-by: satya priya <skakit@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39807 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 05:51:21 +0000