Age | Commit message (Collapse) | Author |
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Init frequency to 19.2 MHz
TEST=build
Change-Id: I566c7ff2b7085c9dd89ea74a08f3ba862feab2ab
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Initialize 1st 4GB as Device Memory, except:
* 1st page: NULL address
* System_IMEM: Cached SRAM
* Boot_IMEM: Cached SRAM
Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Adding the basic infrastruture soc support for qcs405 and
a new build variant.
TEST=build
Change-Id: Ia379cf375e4459ed55cc36cb8a0a92cab18b705e
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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