coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2021-09-16	mainboard/google: Update the TLMM registers for sdhc	Shaik Sajida Bhanu
	Update the TLMM register values for eMMC and SD card on Trogdor, Herobrine and Mistral boards. BUG=b:196936525 TEST=Validated on qualcomm sc7280 and sc7180 development board and checked basic boot up. Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Change-Id: Iccdb7757027c6de424a82e4374bad802501ac83c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57450 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21	soc/qualcomm: Drop unneeded empty lines	Elyes HAOUAS
	Change-Id: If76502ff91896959ef171c192b4fc138dff18fc6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-07-14	src: Remove unused 'include <stdint.h>	Elyes HAOUAS
	Found using: diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\\|int16_t\\|int32_t\\|int64_t\\|intptr_t\\|intmax_t\\|s8\\|u8\\|s16\\|u16\\|s32\\|u32\\|s64\\|u64\\|INT8_MIN\\|INT8_MAX\\|INT16_MIN\\|INT16_MAX\\|INT32_MIN\\|INT32_MAX\\|INT64_MIN\\|INT64_MAX\\|INTMAX_MIN\\|INTMAX_MAX' -- src/) \|grep -v vendorcode \|grep '<' Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41827 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14	src: Remove unused 'include <types.h>'	Elyes HAOUAS
	Files found using: diff <(git grep -l '#include <types.h>' -- src/) <(git grep -l 'BIT(\\|size_t\\|wchar_t\\|wint_t\\|NULL\\|DEVTREE_EARLY\\|DEVTREE_CONST\\|MAYBE_STATIC_NONZERO\\|zeroptr\\|int8_t\\|int16_t\\|int32_t\\|int64_t\\|intptr_t\\|intmax_t\\|s8\\|u8\\|s16\\|u16\\|s32\\|u32\\|s64\\|u64\\|INT8_MIN\\|INT8_MAX\\|INT16_MIN\\|INT16_MAX\\|INT32_MIN\\|INT32_MAX\\|INT64_MIN\\|INT64_MAX\\|INTMAX_MIN\\|INTMAX_MAX\\|bool\\|true\\|false\\|cb_err\\|CB_SUCCESS\\|CB_ERR\\|CB_ERR_ARG\\|CB_CMOS_\\|CB_KBD_\\|CB_I2C_\\|cb_err_t\\|DIV_ROUND_CLOSEST\\|container_of\\|__unused\\|alloca(\\|ARRAY_SIZE\\|ALIGN\\|ALIGN_UP\\|ALIGN_DOWN\\|IS_ALIGNED\\|__CMP_UNSAFE\\|MIN_UNSAFE\\|MAX_UNSAFE\\|__CMP_SAFE\\|__CMP\\|MIN(\\|MAX(\\|ABS(\\|IS_POWER_OF_2\\|POWER_OF_2\\|DIV_ROUND_UP\\|SWAP(\\|KiB\\|MiB\\|GiB\\|KHz\\|MHz\\|GHz\\|offsetof(\\|check_member\\|member_size' -- src/)\|grep -v vendor \|grep '<' Change-Id: I5d99d844cc58d80acb505d98da9d3ec76319b2eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41677 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-13	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	Furquan Shaikh
	This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows SoC/mainboard to provide a linker file for the platform. x86 already provides a default memlayout.ld under src/arch/x86. With this new Kconfig variable, it is possible for the SoC/mainboard code for x86 to provide a custom linker file as well. Makefile.inc is updated for all architectures to use this new Kconfig variable instead of assuming memlayout.ld files under a certain path. All non-x86 boards used memlayout.ld under mainboard directory. However, a lot of these boards were simply including the memlayout from SoC. So, this change also updates these mainboards and SoCs to define the Kconfig as required. BUG=b:155322763 TEST=Verified that abuild with --timeless option results in the same coreboot.rom image for all boards. Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11	treewide: Replace BSD-3-Clause and ISC headers with SPDX headers	Patrick Georgi
	Commands used: perl -i -p0e 's\|\/\[\s]Permission[\s]to[\s]use,[\s]copy,[\s]modify,[\s]and.or[\s]distribute[\s]this[\s]software[\s]for[\s]any[\s]purpose[\s]with[\s]or[\s]without[\s]fee[\s]is[\s]hereby[\s]granted,[\s]provided[\s]that[\s]the[\s]above[\s]copyright[\s]notice[\s]and[\s]this[\s]permission[\s]notice[\s]appear[\s]in[\s]all[\s]copies.[\s]THE[\s]SOFTWARE[\s]IS[\s]PROVIDED[\s].AS[\s]IS.[\s]AND[\s]THE[\s]AUTHOR[\s]DISCLAIMS[\s]ALL[\s]WARRANTIES[\s]WITH[\s]REGARD[\s]TO[\s]THIS[\s]SOFTWARE[\s]INCLUDING[\s]ALL[\s]IMPLIED[\s]WARRANTIES[\s]OF[\s]MERCHANTABILITY[\s]AND[\s]FITNESS.[\s]IN[\s]NO[\s]EVENT[\s]SHALL[\s]THE[\s]AUTHOR[\s]BE[\s]LIABLE[\s]FOR[\s]ANY[\s]SPECIAL,[\s]DIRECT,[\s]INDIRECT,[\s]OR[\s]CONSEQUENTIAL[\s]DAMAGES[\s]OR[\s]ANY[\s]DAMAGES[\s]WHATSOEVER[\s]RESULTING[\s]FROM[\s]LOSS[\s]OF[\s]USE,[\s]DATA[\s]OR[\s]PROFITS,[\s]WHETHER[\s]IN[\s]AN[\s]ACTION[\s]OF[\s]CONTRACT,[\s]NEGLIGENCE[\s]OR[\s]OTHER[\s]TORTIOUS[\s]ACTION,[\s]ARISING[\s]OUT[\s]OF[\s]OR[\s]IN[\s]CONNECTION[\s]WITH[\s]THE[\s]USE[\s]OR[\s]PERFORMANCE[\s]OF[\s]THIS[\s]SOFTWARE.[\s]\\/\|/* SPDX-License-Identifier: ISC /\|s' $(cat filelist) perl -i -p0e 's\|(\#\#)\sPermission[\#\s]to[\#\s]use,[\#\s]copy,[\#\s]modify,[\#\s]and.or[\#\s]distribute[\#\s]this[\#\s]software[\#\s]for[\#\s]any[\#\s]purpose[\#\s]with[\#\s]or[\#\s]without[\#\s]fee[\#\s]is[\#\s]hereby[\#\s]granted,[\#\s]provided[\#\s]that[\#\s]the[\#\s]above[\#\s]copyright[\#\s]notice[\#\s]and[\#\s]this[\#\s]permission[\#\s]notice[\#\s]appear[\#\s]in[\#\s]all[\#\s]copies.[\#\s]THE[\#\s]SOFTWARE[\#\s]IS[\#\s]PROVIDED[\#\s].AS[\#\s]IS.[\#\s]AND[\#\s]THE[\#\s]AUTHOR[\#\s]DISCLAIMS[\#\s]ALL[\#\s]WARRANTIES[\#\s]WITH[\#\s]REGARD[\#\s]TO[\#\s]THIS[\#\s]SOFTWARE[\#\s]INCLUDING[\#\s]ALL[\#\s]IMPLIED[\#\s]WARRANTIES[\#\s]OF[\#\s]MERCHANTABILITY[\#\s]AND[\#\s]FITNESS.[\#\s]IN[\#\s]NO[\#\s]EVENT[\#\s]SHALL[\#\s]THE[\#\s]AUTHOR[\#\s]BE[\#\s]LIABLE[\#\s]FOR[\#\s]ANY[\#\s]SPECIAL,[\#\s]DIRECT,[\#\s]INDIRECT,[\#\s]OR[\#\s]CONSEQUENTIAL[\#\s]DAMAGES[\#\s]OR[\#\s]ANY[\#\s]DAMAGES[\#\s]WHATSOEVER[\#\s]RESULTING[\#\s]FROM[\#\s]LOSS[\#\s]OF[\#\s]USE,[\#\s]DATA[\#\s]OR[\#\s]PROFITS,[\#\s]WHETHER[\#\s]IN[\#\s]AN[\#\s]ACTION[\#\s]OF[\#\s]CONTRACT,[\#\s]NEGLIGENCE[\#\s]OR[\#\s]OTHER[\#\s]TORTIOUS[\#\s]ACTION,[\#\s]ARISING[\#\s]OUT[\#\s]OF[\#\s]OR[\#\s]IN[\#\s]CONNECTION[\#\s]WITH[\#\s]THE[\#\s]USE[\#\s]OR[\#\s]PERFORMANCE[\#\s]OF[\#\s]THIS[\#\s]SOFTWARE.\s(\# \n)\|\1 SPDX-License-Identifier: ISC\n\n\|s' $(cat filelist) perl -i -p0e 's\|\/\[\s]Redistribution[\s]and[\s]use[\s]in[\s]source[\s]and[\s]binary[\s]forms,[\s]with[\s]or[\s]without[\s]modification,[\s]are[\s]permitted[\s]provided[\s]that[\s]the[\s]following[\s]conditions[\s]are[\s]met:[\s][1. ]Redistributions[\s]of[\s]source[\s]code[\s]must[\s]retain[\s]the[\s]above[\s]copyright[\s]notice,[\s]this[\s]list[\s]of[\s]conditions[\s]and[\s]the[\s]following[\s]disclaimer.[\s][\s][2. ]Redistributions[\s]in[\s]binary[\s]form[\s]must[\s]reproduce[\s]the[\s]above[\s]copyright[\s]notice,[\s]this[\s]list[\s]of[\s]conditions[\s]and[\s]the[\s]following[\s]disclaimer[\s]in[\s]the[\s]documentation[\s]and.or[\s]other[\s]materials[\s]provided[\s]with[\s]the[\s]distribution.[\s][3. ].used[\s]to[\s]endorse[\s]or[\s]promote[\s]products[\s]derived[\s]from[\s]this[\s]software[\s]without[\s]specific[\s]prior[\s]written[\s]permission.[\s]THIS[\s]SOFTWARE[\s]IS[\s]PROVIDED.AS[\s]IS.[\s]AND[\s]ANY[\s]EXPRESS[\s]OR[\s]IMPLIED[\s]WARRANTIES,[\s]INCLUDING,[\s]BUT[\s]NOT[\s]LIMITED[\s]TO,[\s]THE[\s]IMPLIED[\s]WARRANTIES[\s]OF[\s]MERCHANTABILITY.FITNESS[\s]FOR[\s]A[\s]PARTICULAR[\s]PURPOSE.ARE[\s]DISCLAIMED.[\s]IN[\s]NO[\s]EVENT[\s]SHALL.LIABLE[\s]FOR[\s]ANY[\s]DIRECT,[\s]INDIRECT,[\s]INCIDENTAL,[\s]SPECIAL,[\s]EXEMPLARY,[\s]OR[\s]CONSEQUENTIAL[\s]DAMAGES[\s].INCLUDING,[\s]BUT[\s]NOT[\s]LIMITED[\s]TO,[\s]PROCUREMENT[\s]OF[\s]SUBSTITUTE[\s]GOODS[\s]OR[\s]SERVICES;[\s]LOSS[\s]OF[\s]USE,[\s]DATA,[\s]OR[\s]PROFITS;[\s]OR[\s]BUSINESS[\s]INTERRUPTION.[\s]HOWEVER[\s]CAUSED[\s]AND[\s]ON[\s]ANY[\s]THEORY[\s]OF[\s]LIABILITY,[\s]WHETHER[\s]IN[\s]CONTRACT,[\s]STRICT[\s]LIABILITY,[\s]OR[\s]TORT[\s].INCLUDING[\s]NEGLIGENCE[\s]OR[\s]OTHERWISE.[\s]ARISING[\s]IN[\s]ANY[\s]WAY[\s]OUT[\s]OF[\s]THE[\s]USE[\s]OF[\s]THIS[\s]SOFTWARE,[\s]EVEN[\s]IF[\s]ADVISED[\s]OF[\s]THE[\s]POSSIBILITY[\s]OF[\s]SUCH[\s]DAMAGE.[\s]\\/\|/ SPDX-License-Identifier: BSD-3-Clause /\|s' $(cat filelist) $1 perl -i -p0e 's\|(\#\#) Redistribution[\#\s]and[\#\s]use[\#\s]in[\#\s]source[\#\s]and[\#\s]binary[\#\s]forms,[\#\s]with[\#\s]or[\#\s]without[\#\s]modification,[\#\s]are[\#\s]permitted[\#\s]provided[\#\s]that[\#\s]the[\#\s]following[\#\s]conditions[\#\s]are[\#\s]met:[\#\s][1. ]Redistributions[\#\s]of[\#\s]source[\#\s]code[\#\s]must[\#\s]retain[\#\s]the[\#\s]above[\#\s]copyright[\#\s]notice,[\#\s]this[\#\s]list[\#\s]of[\#\s]conditions[\#\s]and[\#\s]the[\#\s]following[\#\s]disclaimer.[\#\s][2. ]Redistributions[\#\s]in[\#\s]binary[\#\s]form[\#\s]must[\#\s]reproduce[\#\s]the[\#\s]above[\#\s]copyright[\#\s]notice,[\#\s]this[\#\s]list[\#\s]of[\#\s]conditions[\#\s]and[\#\s]the[\#\s]following[\#\s]disclaimer[\#\s]in[\#\s]the[\#\s]documentation[\#\s]and.or[\#\s]other[\#\s]materials[\#\s]provided[\#\s]with[\#\s]the[\#\s]distribution.[\#\s][\#\s][3. ].used[\#\s]to[\#\s]endorse[\#\s]or[\#\s]promote[\#\s]products[\#\s]derived[\#\s]from[\#\s]this[\#\s]software[\#\s]without[\#\s]specific[\#\s]prior[\#\s]written[\#\s]permission.[\#\s]THIS[\#\s]SOFTWARE[\#\s]IS[\#\s]PROVIDED.AS[\#\s]IS.[\#\s]AND[\#\s]ANY[\#\s]EXPRESS[\#\s]OR[\#\s]IMPLIED[\#\s]WARRANTIES,[\#\s]INCLUDING,[\#\s]BUT[\#\s]NOT[\#\s]LIMITED[\#\s]TO,[\#\s]THE[\#\s]IMPLIED[\#\s]WARRANTIES[\#\s]OF[\#\s]MERCHANTABILITY.FITNESS[\#\s]FOR[\#\s]A[\#\s]PARTICULAR[\#\s]PURPOSE.ARE[\#\s]DISCLAIMED.[\#\s]IN[\#\s]NO[\#\s]EVENT[\#\s]SHALL.LIABLE[\#\s]FOR[\#\s]ANY[\#\s]DIRECT,[\#\s]INDIRECT,[\#\s]INCIDENTAL,[\#\s]SPECIAL,[\#\s]EXEMPLARY,[\#\s]OR[\#\s]CONSEQUENTIAL[\#\s]DAMAGES[\#\s].INCLUDING,[\#\s]BUT[\#\s]NOT[\#\s]LIMITED[\#\s]TO,[\#\s]PROCUREMENT[\#\s]OF[\#\s]SUBSTITUTE[\#\s]GOODS[\#\s]OR[\#\s]SERVICES;[\#\s]LOSS[\#\s]OF[\#\s]USE,[\#\s]DATA,[\#\s]OR[\#\s]PROFITS;[\#\s]OR[\#\s]BUSINESS[\#\s]INTERRUPTION.[\#\s]HOWEVER[\#\s]CAUSED[\#\s]AND[\#\s]ON[\#\s]ANY[\#\s]THEORY[\#\s]OF[\#\s]LIABILITY,[\#\s]WHETHER[\#\s]IN[\#\s]CONTRACT,[\#\s]STRICT[\#\s]LIABILITY,[\#\s]OR[\#\s]TORT[\#\s].INCLUDING[\#\s]NEGLIGENCE[\#\s]OR[\#\s]OTHERWISE.[\#\s]ARISING[\#\s]IN[\#\s]ANY[\#\s]WAY[\#\s]OUT[\#\s]OF[\#\s]THE[\#\s]USE[\#\s]OF[\#\s]THIS[\#\s]SOFTWARE,[\#\s]EVEN[\#\s]IF[\#\s]ADVISED[\#\s]OF[\#\s]THE[\#\s]POSSIBILITY[\#\s]OF[\#\s]SUCH[\#\s]DAMAGE.\s(\#* \n)\|\1 SPDX-License-Identifier: BSD-3-Clause\n\n\|s' $(cat filelist) Change-Id: I7ff9c503a2efe1017a4666baf0b1a758a04f5634 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-11	treewide: split off license text, remove extra copyright notices	Patrick Georgi
	Copyright notices are best stored in AUTHORS Change-Id: Ib9025c58987ee2f7db600e038f5d3e4edc69aacc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41203 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
	Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " \|egrep ":( /\.\/\$\|#\|;#\|-- \| \ )" \| cut -d: -f1 \|grep -v crossgcc \|grep -v gcov \| grep -v /elf.h \|grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. /") -# This file is part of a set of unofficial pre-commit hooks available -/ This file is part of coreboot / -# This file is part of msrtool. -/ This file is part of msrtool. / - This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. / - This file is part of the coreboot project. - /* This file is part of the coreboot project. / -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/ This file is part of the coreboot project / -/ This file is part of the coreboot project. / -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. / -/ This file is part of the ectool project. / - This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. / -## This file is part of the superiotool project. -/ This file is part of the superiotool project / -/ This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-06	treewide: replace GPLv2 long form headers with SPDX header	Patrick Georgi
	This replaces GPLv2-or-later and GPLv2-only long form text with the short SPDX identifiers. Commands used: perl -i -p0e 's\|/\[\n\t ]This program is free software[:;].you.can.redistribute.it.and/or.modify.it.under.the.terms.of.the.GNU.General.Public.License.as.published.by.the.Free.Software.Foundation[;,].version.2.of.the.License.or.(at.your.option).any.later.version.+This.program.is.distributed.in.the.hope.that.it.will.be.useful,.but.;.without.even.the.implied.warranty.of.MERCHANTABILITY.or.FITNESS.FOR.A.PARTICULAR.PURPOSE...See.the.GNU.General.Public.License for more details.[\n\t ]\/\|/ SPDX-License-Identifier: GPL-2.0-or-later /\|s' $(cat filelist) perl -i -p0e 's\|/\[\n\t ]This program is free software[:;].you.can.redistribute.it.and/or.modify.it.under.the.terms.of.the.GNU.General.Public.License.as.published.by.the.Free.Software.Foundation[;,].version.2.+This.program.is.distributed.in.the.hope.that.it.will.be.useful,.but.;.without.even.the.implied.warranty.of.MERCHANTABILITY.or.FITNESS.FOR.A.PARTICULAR.PURPOSE...See.the.GNU.General.Public.License for more details.[\n\t ]\/\|/* SPDX-License-Identifier: GPL-2.0-only /\|s' $(cat filelist) perl -i -p0e 's\|/\[\n\t ]This program is free software[:;].you.can.redistribute.it.and/or.modify.it.under.the.terms.of.the.GNU.General.Public.License.version.2.as.published.by.the.Free.Software.Foundation[.;,].+This.program.is.distributed.in.the.hope.that.it.will.be.useful,.but.;.without.even.the.implied.warranty.of.MERCHANTABILITY.or.FITNESS.FOR.A.PARTICULAR.PURPOSE...See.the.GNU.General.Public.License for more details.[\n\t ]\/\|/* SPDX-License-Identifier: GPL-2.0-only /\|s' $(cat filelist) perl -i -p0e 's\|/\[\n\t ]This software is licensed under.the.terms.of.the.GNU.General.Public.License.version.2.as.published.by.the.Free.Software.Foundation,.+This.program.is.distributed.in.the.hope.that.it.will.be.useful,.but.;.without.even.the.implied.warranty.of.MERCHANTABILITY.or.FITNESS.FOR.A.PARTICULAR.PURPOSE...See.the.GNU.General.Public.License for more details.[\n\t ]\/\|/* SPDX-License-Identifier: GPL-2.0-only */\|s' $(cat filelist) Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06	treewide: move copyrights and authors to AUTHORS	Patrick Georgi
	Also split "this is part of" line from copyright notices. Change-Id: Ibc2446410bcb3104ead458b40a9ce7819c61a8eb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06	treewide: Move "is part of the coreboot project" line in its own comment	Patrick Georgi
	That makes it easier to identify "license only" headers (because they are now license only) Script line used for that: perl -i -p0e 's\|/\.\n.This file is part of the coreboot project.\n.\\|/* This file is part of the coreboot project. /\n/\|' # ...filelist... Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-18	soc: Remove copyright notices	Patrick Georgi
	They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-12-04	Change all clrsetbits_leXX() to clrsetbitsXX()	Julius Werner
	This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/$[cs][le][rt]bits$_le$[136][624]$/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-11-14	lib/fmap: Add optional pre-RAM cache	Julius Werner
	This patch adds an optional pre-RAM cache for the FMAP which most platforms should be able to use, complementing the recently added post-RAM FMAP cache in CBMEM. vboot systems currently read the FMAP about half a dozen times from flash in verstage, which will all be coalesced into a single read with this patch. It will also help future vboot improvements since when FMAP reads become "free" vboot doesn't need to keep track of so much information separately. In order to make sure we have a single, well-defined point where the new cache is first initialized, eliminate the build-time hardcoding of the CBFS section offsets, so that all CBFS accesses explicitly read the FMAP. Add FMAP_CACHEs to all platforms that can afford it (other than the RISC-V things where I have no idea how they work), trying to take the space from things that look like they were oversized anyway (pre-RAM consoles and CBFS caches). Change-Id: I2820436776ef620bdc4481b5cd4b6957764248ea Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Joel Kitching <kitching@google.com>
2019-06-05	coreboot: Add i2c clock API for qcs405	Taniya Das
	Add support of i2c clock enable, disable and configure API. Change-Id: Ia0b42357ac09bf0ab60aad18c44e5ef27fe9dac3 Signed-off-by: Shefali Jain <shefjain@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32545 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04	qcs405: Add SPI driver support	Prudhvi Yarlagadda
	Add SPI driver support in coreboot. Change-Id: I813ba0b5cc8344c463c3e41ff6db80bc0d8ebd96 Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32058 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04	qcs405: Add UART support	Prudhvi Yarlagadda
	Add support for UART driver in coreboot. TEST=build & run Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f Signed-off-by: Prudhvi Yarlagadda<pyarlaga@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29964 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23	qcs405: Add support of GPIO IRQ APIs	Taniya Das
	Add support of GPIO IRQ APIs. Change-Id: I11715a93999012622a5e28455731cbe249ba8f2c Signed-off-by: Shefali Jain <shefjain@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-23	qcs405: clock: Update SPI API	Taniya Das
	Update SPI enable/disable and configure clock API for supporting all the blsp and qup for qcs405. Change-Id: I39622571cb671f62312283a010129ceecb654f61 Signed-off-by: Shefali Jain <shefjain@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-28	qcs405: Add support for USB host mode	Vijayavardhan Vennapusa
	Add required changes for USB host mode for USB disk enumeration. TEST=build & run Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Signed-off-by: Vijayavardhan Vennapusa <vvreddy@partner-android.googlesource.com> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-26	qcs405: clock: Adding the clock support for qcs405	Pranav Agrawal
	Add basic clock support and enable UART, SPI clocks. Change-Id: I991bdde5f69e1c0f6ec5d6961275a1c077bc5bae Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Signed-off-by: Pranav Agrawal <pranava@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-26	qcs405: Add GPIO API	Nitheesh Sekar
	Introduce new and required GPIO APIs, using common pinmux definitions for GPIO configuration. TEST=build & run Change-Id: I85ce9007c545b44371c4704a0456774d0eff12a8 Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-21	vboot: standardize on working data size	Joel Kitching
	Previously, the size of memory made for vboot_working_data through the macro VBOOT2_WORK was always specified in each individual memlayout file. However, there is effectively no reason to provide this customizability -- the workbuf size required for verifying firmware has never been more than 12K. (This could potentially increase in the future if key sizes or algorithms are changed, but this could be applied globally rather than for each individual platform.) This CL binds the VBOOT2_WORK macro to directly use the VB2_WORKBUF_RECOMMENDED_DATA_SIZE constant as defined by vboot API. Since the constant needs to be used in a linker script, we may not include the full vboot API, and must instead directly include the vb2_constants.h header. BUG=b:124141368, b:124192753 TEST=Build locally for eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild BRANCH=none CQ-DEPEND=CL:1504490 Change-Id: Id71a8ab2401efcc0194d48c8af9017fc90513cb8 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18	qcs405: Add DRAM resources	Nitheesh Sekar
	TEST=build Change-Id: Iea79a942c297400c88aa205da713bcfcb8c51185 Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18	soc/qualcomm/qcs405: Add MMU support	Nitheesh Sekar
	Initialize 1st 4GB as Device Memory, except: * 1st page: NULL address * System_IMEM: Cached SRAM * Boot_IMEM: Cached SRAM Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18	soc/qualcomm/qcs405: Support for new SoC	Nitheesh Sekar
	Adding the basic infrastruture soc support for qcs405 and a new build variant. TEST=build Change-Id: Ia379cf375e4459ed55cc36cb8a0a92cab18b705e Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>