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path: root/src/soc/qualcomm/ipq806x/timer.c
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2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-10-27src/soc: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I9c1228d3f9e7a12fe30c48e3b1f143520fed875c Reviewed-on: https://review.coreboot.org/c/coreboot/+/36332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2015-04-08ipq806x: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns ipq806x to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Storm. Change-Id: Icb81a77e6f458625f5379a980e8760388dd3a1f9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1bf23774c9ffa5d08c211f3658d39adcfa47b339 Original-Change-Id: I283cc7e6094be977d67ed4146f376cebcea6774a Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224502 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9368 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: Patrick Georgi <pgeorgi@google.com>
2015-03-17soc/ipq806x: Replace GPT with fine grained DGT timer.Deepa Dinamani
Support 1MHz libpayload restriction on timer implementation by using DGT (debug) timer instead of GPT (general purpose) timer. BUG=chrome-os-partner:28880 TEST=manual verified DGT timer functions in coreboot and depthcharge. Original-Change-Id: Iab322d7e863e3959c027e9ce876223a64eb7e257 Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201574 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit ddf11eee5ec2d86a62095e932dbec9313b8fb9e1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id73e805801fd8d135b607df9f4f8caf567ec5b83 Reviewed-on: http://review.coreboot.org/8596 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-06doxygen fixes: change @var to @param varMartin Roth
These files were trying to document the parameters, but didn't have the syntax quite right. Change the comments from @varname to @param varname as required by doxygen. Change-Id: I63662094d3f1686e3e35b61925b580eb06e72e28 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8100 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-03ipq8084: provide monotonic us timerVadim Bendebury
This service is required by various coreboot code modules. It looks like the 8064 SOC does not provide anything better than a 32 KHz free running counter (it is used in u-boot for us timer as well). Let's use this for now. BUG=chrome-os-partner:27784 TEST=manual . with the rest of the patches applied AP148 boots all the way to trying to start the payload. Original-Change-Id: I98b91ce179f7388d59c769a59caf49ca7640e047 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197896 (cherry picked from commit d526830f9d9618e4ca3460165d7b9ecc8ab268cf) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id37ed21193db67ceee11a795713c34ef26383380 Reviewed-on: http://review.coreboot.org/7993 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-30ipq8064: make timer services availableMarc Jones
Make sure it is initialized at different stages. BUG=chrome-os-partner:27784 TEST=manual . not much at this point, just verified that it compiles Original-Change-Id: I343e7a6648e2ca935606cd76befd204aabd93726 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196592 (cherry picked from commit aedc41924313e5c21aef97b036f5a0643d59082d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4a90ae5ba6c9a561b7d5c938d18b6ea2b855855f Reviewed-on: http://review.coreboot.org/7981 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-13ipq8064: Make timer code compileVadim Bendebury
Commment out nonessential timer services and modify the source code to cleanly build in coeboot environment. Do not remove dead code just yet, these functions might be necessary later. Need to rename the soc timer.h to prevent collisions with timer.h in the top level include directory. Currently build timer code for ramstage only. BUG=chrome-os-partner:27784 TEST='emerge-storm coreboot' still succeeds Original-Change-Id: Ib10133ccb42697840708845a8ea6d75ceeaeb3d5 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/194067 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 987ce95220953c16216d1e1d70d5a941d05fc9bc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia9cf175da11c70709354def5e51bf79df4fda2fe Reviewed-on: http://review.coreboot.org/7269 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-12Copy u-boot sources as is and modify the tree to still buildVadim Bendebury
This patch brings in ipq806x source files from the vendor's u-boot tree as it was published in the 'cs_banana' release. The following files are being copied: arch/arm/cpu/armv7/ipq/clock.c => src/soc/qualcomm/ipq806x/clock.c arch/arm/cpu/armv7/ipq/gpio.c => src/soc/qualcomm/ipq806x/gpio.c arch/arm/cpu/armv7/ipq/timer.c => src/soc/qualcomm/ipq806x/timer.c arch/arm/include/asm/arch-ipq806x/clock.h => src/soc/qualcomm/ipq806x/clock.h arch/arm/include/asm/arch-ipq806x/gpio.h => src/soc/qualcomm/ipq806x/gpio.h arch/arm/include/asm/arch-ipq806x/gsbi.h => src/soc/qualcomm/ipq806x/gsbi.h arch/arm/include/asm/arch-ipq806x/iomap.h => src/soc/qualcomm/ipq806x/iomap.h arch/arm/include/asm/arch-ipq806x/timer.h src/soc/qualcomm/ipq806x/timer.h arch/arm/include/asm/arch-ipq806x/uart.h => src/soc/qualcomm/ipq806x/uart.h board/qcom/ipq806x_cdp/ipq806x_cdp.c => src/mainboard/google/storm/cdp.c board/qcom/ipq806x_cdp/ipq806x_cdp.h => src/soc/qualcomm/ipq8064/cdp.h drivers/serial/ipq806x_uart.c => src/console/ipq806x_console.c Note that local timer.c gets overwritten with the original version. To prevent a build breakage some shortly to be reverted modifications had to be made to src/soc/qualcomm/ipq806x/Makefile.inc and src/soc/qualcomm/ipq806x/cbfs.c. BRANCH=none BUG=chrome-os-partner:27784 TEST='emerge-storm coreboot' still succeeds Original-Change-Id: I3f50bfbec2e18a3b5d2c640cff353a26f88c98c1 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193722 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 3c9c2ede7e97e330cad2c2f3e557cc9bcdaecdcc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia7bc66cecfc16f1dd4a9f3cb9840cbe91878adf4 Reviewed-on: http://review.coreboot.org/7263 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-25soc/qualcomm: Add generic support skeleton for ipq806xFurquan Shaikh
Skeleton for soc ipq806x Old-Change-Id: I92a8d592d762f59665e15d1a7fc6cc73dc74c296 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/190723 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit e71d45733d86e77717fd2f592ef06113246db911) soc/ipq806x: Disable LPAE mode. LPAE (large physical address extension) is not available on this SOC core, do not enable it. Old-Change-Id: I9e9ad1aeaf613f04987c0c306a574085042d0e7b Signed-off-by: Deepa Dinamani <deepad@codeaurora.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198023 Reviewed-by: deepa dinamani <deepad@quicinc.com> (cherry picked from commit e6e12c39efd54e4fcbd444134bf30e211948a71b) Squashed 2 commits for the Qualcomm ipq806x SOC. Change-Id: I14521d3b2844ddd68112882de81453ce8d19fc16 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6963 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)