aboutsummaryrefslogtreecommitdiff
path: root/src/soc/qualcomm/ipq40xx/include
AgeCommit message (Collapse)Author
2016-05-10soc/qualcomm/ipq40xx: Enable crashdump handlingVaradarajan Narayanan
Clear the crash dump cookie set by SBL to indicate that it is a normal reset. Inform DDR image of the entrypoint for SDI image to be preserved in OCIMEM which will be needed during watchdog resets. BUG=chrome-os-partner:49249 TEST=DDR image is able to fetch the entry point address BRANCH=none Change-Id: I3e6e4a108585bb257e3ad02956c420acbcb2554e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bd726256a5ae89672810b57e1d2a7a9287f60627 Original-Change-Id: Id6e09516209f47c3ea8fa3d8d90440789b395660 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333321 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14679 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-10soc/qualcomm/ipq40xx: Add support for BLSP QUP I2CVaradarajan Narayanan
Able to talk to the TPM device and the commands seem to succeed. BUG=chrome-os-partner:49249 chrome-os-partner:49250 TEST=All commands to the TPM succeed BRANCH=none Original-Commit-Id: c13900108f524c8422c38dee88469c8bfe24d0bd Original-Change-Id: Ie8c3c1ab1290cd8d7e6ddd1ae22f765c7be81019 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333314 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> squashed: soc/qualcomm/ipq40xx: Add support for BLSP QUP SPI - Enable BLSP SPI driver for ipq40xx - supports only FIFO mode BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: 0714025975854dd048d35fe602824ead4c7d94e9 Original-Change-Id: If809b0fdf7d6c9405db6fd3747a3774c00ea9870 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333303 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ia518af5bfc782b08a0883ac93224d476d07e2426 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14677 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-10soc/qualcomm/ipq40xx: Streamline memory mapVaradarajan Narayanan
BUG=chrome-os-partner:49249 TEST=Able to compile and boot to depthcharge BRANCH=none Change-Id: I042fce58526b1c2add6b930429bf397e0dcfad2c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 66a630db6132e0e8a736b635d65e9e11c269b54a Original-Change-Id: Ie2b6f59b3dbbac8117636c103d4d0acb782f4cb3 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333322 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14665 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10google/gale: Remove NAND initVaradarajan Narayanan
This is stale code from ipq806x, n/a for ipq40xx. Hence removing it. BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Change-Id: I2ac73677f77d4bfbc70f56c73a661cc2c22dd384 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2f9796588648bc477f118282aad89037f0577f23 Original-Change-Id: I8bcf928ee23ac24a21b0e633e207354ea9fa0511 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333299 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14664 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10soc/qualcomm/ipq40xx: Enable timerVaradarajan Narayanan
BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: 35c0e6046899dc1af03736ae9fa77f9eeec7f668 Original-Change-Id: I681e92fa673c1d3aee2974a7bba5074e2bfd6e02 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333297 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> squashed: soc/qualcomm/ipq40xx: Enable UART on ipq40xx - BLSP/UART Clock configuration - GPIO Configuration BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: 7bba1fc7f50e7aeb4e7b37f164e85771e53f47e6 Original-Change-Id: I474a0e97b24ac9b3f2cba599cd709b6801b08f91 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333300 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: I5e31d036ee7ddcf72ed9739cef1f7f7d0ca6c427 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14667 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10soc/qualcomm/ipq40xx: Return NULL for cbmem_top if DRAM is not initializedVaradarajan Narayanan
DRAM initialization on gale requires ipq blobs to be loaded from cbfs. vboot_locator first checks cbmem_find to see if cbmem is initialized and contains selected region info, else it falls back to vboot work buffer. Since cbmem_find calls into cbmem_top to identify the location of cbmem area, board/chipset is expected to return NULL until the backing store is ready, which in this case until DRAM is initialized in romstage, return NULL for cbmem_top. BUG=chrome-os-partner:49249 TEST=Able to compile and boot to depthcharge. Doesn't crash in imd_handle_init_partial_recovery BRANCH=none Change-Id: Iaac24252ee4fb9f59d767730bf9dd68baa42a68f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4849c15dee2d3782ede4ee4157e432bd4d5602f0 Original-Change-Id: I3722b7ab5a6585a250138c828eb3d7919b0c1178 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/335425 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14660 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10soc/qualcomm/ipq40xx: Update memory map to align to ipq40xxVaradarajan Narayanan
Update the memory to map to align with the internal memory region map of IPQ40XX BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: e33712a729ef9831508c2e9aae81d0b32495b681 Original-Change-Id: Iba1c5281a2fbda4ab96126676b901ba71f6b28e0 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333295 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> squashed: soc/qualcomm/ipq40xx: Update DRAM address ranges BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: 9150c125cb82f8dccb1347d898106703d85a5192 Original-Change-Id: Ic48d3e3f46a7c13a009a5cbed20984bd253eb85b Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333296 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: Iea40484751a1c0439ed511319ef09a0254eba757 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14654 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10soc/qualcomm/ipq40xx: Initial commit for IPQ40xx SoC supportVaradarajan Narayanan
Copy 'ipq806x' files as a template BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: dc6a5937953fe61cd4b5a99ca49f9371c4b712d4 Original-Change-Id: If171fcdd3b0561cb6b7dab5f8434de7ef711ea41 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/333178 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> squashed: soc/qualcomm/ipq40xx: Update ipq806x/storm references Since the files were taken from ipq806x/storm as template. Update those references to reflect ipq40xx/gale. BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: c6c76d184cc92c09e6826fbdc7d7fac59b2cb69b Original-Change-Id: Ieae1bce25291243b4a6034d37a6949978f318997 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333293 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ie5794c48131ae562861074b406106734541880d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14644 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-24 20:52:35 +0000