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2015-06-30t210: Set UTMIP_PCOUNT_UPDN_DIV to 0Stephen Barber
Improve USB device mode stability as per suggestion by Laurent. BUG=chrome-os-partner:40929 BRANCH=smaug TEST=flash firmware and check that USB device mode is still functional. Change-Id: Id6dd7bb2e1632c512cfdf7d38a16de26a8f71471 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4298741ef4440c8bd8dac4a9f9eaa55ba560cbfb Original-Change-Id: I07d6c46d215f2ccf2c76c580f59c4fa0d519eaa5 Original-Signed-off-by: Stephen Barber <smbarber@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/278030 Original-Reviewed-by: Benson Leung <bleung@chromium.org> Original-Tested-by: Benson Leung <bleung@chromium.org> Reviewed-on: http://review.coreboot.org/10695 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-23nvidia/tegra: expose more registersTom Warren
This is in preparation for t210 Change-Id: I3e640b1f7fc583518361527dec4c3c1072c80251 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e762d4bde1a18691257453e4b87a0bb42a0a2d7c Original-Change-Id: Ida096106bb0137c07ad62d2df06628e37f0d884c Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272754 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10632 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-06-23tegra: Move pinmux enum constants from tegra/pinmux.h to soc-specific pinmux.hFurquan Shaikh
Since pinmux register format has changed completely for t210, move the constants to pinmux.h in soc-specific folders. BUG=chrome-os-partner:37546 BRANCH=None TEST=Compiles successfully for ryu and foster. Change-Id: Ic1680ac50fc2619657d0c610a5dfc3fb51df7286 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7844c941a6187f884b31a8f7cc52e64268d2c732 Original-Change-Id: Icd3b2a72f3698e0772e888d9209e1fcd5d10e77d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/260900 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10631 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-06-21Remove obsolete EARLY_CONSOLE usageMartin Roth
The EARLY_CONSOLE Kconfig symbol was removed in commit 48713a1b - console: Drop EARLY_CONSOLE option The arm64 and mips directories don't even have early_console.c to include. Change-Id: Idc60ffb2bac2b180f4fdd0adf5c411e1f692a846 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10615 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-21Remove old HAVE_UART_MEMORY_MAPPED select statementsMartin Roth
The HAVE_UART_MEMORY_MAPPED symbol is no longer present, so these don't actually select anything. Change-Id: I6d0eb610e48a4506ac7449ac677ee67981d0ff0d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10608 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-09cbmem: Unify CBMEM init tasks with CBMEM_INIT_HOOK() APIKyösti Mälkki
Squashed and adjusted two changes from chromium.git. Covers CBMEM init for ROMTAGE and RAMSTAGE. cbmem: Unify random on-CBMEM-init tasks under common CBMEM_INIT_HOOK() API There are several use cases for performing a certain task when CBMEM is first set up (usually to migrate some data into it that was previously kept in BSS/SRAM/hammerspace), and unfortunately we handle each of them differently: timestamp migration is called explicitly from cbmem_initialize(), certain x86-chipset-specific tasks use the CAR_MIGRATION() macro to register a hook, and the CBMEM console is migrated through a direct call from romstage (on non-x86 and SandyBridge boards). This patch decouples the CAR_MIGRATION() hook mechanism from cache-as-RAM and rechristens it to CBMEM_INIT_HOOK(), which is a clearer description of what it really does. All of the above use cases are ported to this new, consistent model, allowing us to have one less line of boilerplate in non-CAR romstages. BRANCH=None BUG=None TEST=Built and booted on Nyan_Blaze and Falco with and without CONFIG_CBMEM_CONSOLE. Confirmed that 'cbmem -c' shows the full log after boot (and the resume log after S3 resume on Falco). Compiled for Parrot, Stout and Lumpy. Original-Change-Id: I1681b372664f5a1f15c3733cbd32b9b11f55f8ea Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/232612 Reviewed-by: Aaron Durbin <adurbin@chromium.org> cbmem: Extend hooks to ramstage, fix timestamp synching Commit 7dd5bbd71 (cbmem: Unify random on-CBMEM-init tasks under common CBMEM_INIT_HOOK() API) inadvertently broke ramstage timestamps since timestamp_sync() was no longer called there. Oops. This patch fixes the issue by extending the CBMEM_INIT_HOOK() mechanism to the cbmem_initialize() call in ramstage. The macro is split into explicit ROMSTAGE_/RAMSTAGE_ versions to make the behavior as clear as possible and prevent surprises (although just using a single macro and relying on the Makefiles to link an object into all appropriate stages would also work). This allows us to get rid of the explicit cbmemc_reinit() in ramstage (which I somehow accounted for in the last patch without realizing that timestamps work exactly the same way...), and replace the older and less flexible cbmem_arch_init() mechanism. Also added a size assertion for the pre-RAM CBMEM console to memlayout that could prevent a very unlikely buffer overflow I just noticed. BRANCH=None BUG=None TEST=Booted on Pinky and Falco, confirmed that ramstage timestamps once again show up. Compile-tested for Rambi and Samus. Original-Change-Id: If907266c3f20dc3d599b5c968ea5b39fe5c00e9c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/233533 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I1be89bafacfe85cba63426e2d91f5d8d4caa1800 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7878 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-08Remove empty lines at end of fileElyes HAOUAS
Used command line to remove empty lines at end of file: find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \; Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/10446 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-02cbfs: new API and better program loadingAaron Durbin
A new CBFS API is introduced to allow making CBFS access easier for providing multiple CBFS sources. That is achieved by decoupling the cbfs source from a CBFS file. A CBFS source is described by a descriptor. It contains the necessary properties for walking a CBFS to locate a file. The CBFS file is then decoupled from the CBFS descriptor in that it's no longer needed to access the contents of the file. All of this is accomplished using the regions infrastructure by repsenting CBFS sources and files as region_devices. Because region_devices can be chained together forming subregions this allows one to decouple a CBFS source from a file. This also allows one to provide CBFS files that came from other sources for payload and/or stage loading. The program loading takes advantage of those very properties by allowing multiple sources for locating a program. Because of this we can reduce the overhead of loading programs because it's all done in the common code paths. Only locating the program is per source. Change-Id: I339b84fce95f03d1dbb63a0f54a26be5eb07f7c8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9134 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-26coreboot: introduce boot_deviceAaron Durbin
The boot_device is a region_device that represents the device from which coreboot retrieves and boots its stages. The existing cbfs implementations use the boot_device as the intermediary for accessing the CBFS region. Also, there's currently only support for a read-only view of the boot_device. i.e. one cannot write to the boot_device using this view. However, a writable boot_device could be added in the future. Change-Id: Ic0da796ab161b8025c90631be3423ba6473ad31c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10216 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-19Remove Kconfig variable that has no effectPatrick Georgi
DYNAMIC_CBMEM is only selected a couple of times but never declared or read. Remove it. Change-Id: I5016dac2c935d3f261001e9f388a8989540e93ae Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10255 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-19arm64: Reorganize payload entry code and related KconfigsJulius Werner
Rename Kconfig options for secmon and spintable to be prefixed with ARM64_ instead of ARCH_, which seems to be the standard throughout the rest of coreboot (e.g. ARM_LPAE or X86_BOOTBLOCK_SIMPLE). I think this provides a clearer separation between generic options that are selected by the architecture (e.g. a hypothetical ARCH_HAS_FEATURE_X similar to some of the MAINBOARD_HAS_... we have) and options that only make sense in the context of a single architecture. Change-Id: I38c2efab833f252adbb7b61ef0af60ab25b768b0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10242 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19arm64: Reorganize payload entry code and related KconfigsJulius Werner
Remove the secmon Kconfig guard from Makefiles that add to the secmon class since they are redundant (the class is simply not used when compiling without secmon) to improve readability/ease-of-use. [pg: taken out of the patch linked below] Change-Id: I2f0ad8a923ca32fcade748ac8ee50c23cf9bafb9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10241 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-11nvidia/tegra132: we write tables in ramstagePatrick Georgi
So that's more precise than "anything non-pre-ram". Change-Id: I21db536a5ea704c4b087f57d0b761dd3fdf43e3e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10128 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-053rdparty: move to 3rdparty/blobsPatrick Georgi
There's now room for other repositories under 3rdparty. Change-Id: I51b02d8bf46b5b9f3f8a59341090346dca7fa355 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10109 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-053rdparty: Move to blobsPatrick Georgi
To move 3rdparty to 3rdparty/blobs (ie. below itself from git's broken perspective), we need to work around it - since some git implementations don't like the direct approach. Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10108 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-05nvidia/tegra132: Fix vboot2 memory layoutAaron Durbin
bootblock et al were listed twice, which shouldn't happen. Change-Id: I3e6077d70e064ebe74bd4e5e3156f87d548c2fcb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10097 Tested-by: build bot (Jenkins)
2015-05-05vboot: remove uses of vboot2_verify_firmware()Aaron Durbin
The vboot mechanism will be implemented within the program loader subsystem to make it transparent to mainboards and chipsets. Change-Id: Icd0bdcba06cdc30591f9b25068b3fa3a112e58fb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10094 Tested-by: build bot (Jenkins)
2015-04-29kbuild: automatically include SOCsStefan Reinauer
This change switches all SOC vendors and southbridges to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in soc/Makefile.inc or in soc/<vendor>/Makefile.inc. This means, vendor and SOC directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: Iede26fe184b09c53cec23a545d04953701cbc41d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9799 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-22nvidia/tegra132: Add spi_crop_chunk()Patrick Georgi
Missed during upstreaming Change-Id: Ifef4bb8a097a71244bdb648840cd64a812673107 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9950 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22t132: Add gic.c to secmonFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully for ryu. Change-Id: Iaff771cdd1c8b6a7447e1e86aa35ea3ed40b17ad Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2856d3d4f4ab4e56259d36769d9cbb0ec9642951 Original-Change-Id: I702d7c6fa70b1af02c16b874f9de22c6b04a9100 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265624 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9927 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22nvidia/tegra*: check bus number for i2c driver APIsYen Lin
BRANCH=None BUG=None TEST=emerge-foster coreboot Change-Id: I383d2b5f269ed348065a9f270f80514a2ff45742 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fba6973c304e1612a9869c2e78a08650b6e5fe66 Original-Change-Id: I6d5d0098db8dbfb21529bf112a04b97779a0f381 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/264027 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9913 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22soc: select generic gpio lib on (almost) all non-x86 SOCsStefan Reinauer
BOARD_ID functionality is not what requires the GPIO lib, but it is the mainboard specific implementations that do. The option essentially says whether the SoC provides <soc/gpio.h> (with the interface required by the common GPIO code). Right now, x86 and Samsung's Exynos SOCs don't have support for this interface. So this should be selected by the SOC, not by BOARD_ID_SUPPORT. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BUG=none BRANCH=none TEST=emerge-storm coreboot still successfully compiled an image Change-Id: I0ce2bd7ce023f22791d31a6245833b61135504b3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0dd4dea521372194eedf11b077d95fd3b15ad9f7 Original-Change-Id: I3dea6c2fb42a23fcb9d384c3bbfa7fc8e217be2d Original-Reviewed-on: https://chromium-review.googlesource.com/262743 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9899 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21arm(64): Manually clean up the mess left by write32() transitionJulius Werner
This patch is a manual cleanup of all the rubble left by coccinelle waltzing through our code base. It's generally not very good with line breaks and sometimes even eats comments, so this patch is my best attempt at putting it all back together. Also finally remove those hated writel()-style macros from the headers. BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: Id572f69c420c35577701feb154faa5aaf79cd13e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 817402a80ab77083728b55aed74b3b4202ba7f1d Original-Change-Id: I3b0dcd6fe09fc4e3b83ee491625d6dced98e3047 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254865 Reviewed-on: http://review.coreboot.org/9837 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21arm(64): Globally replace writel(v, a) with write32(a, v)Julius Werner
This patch is a raw application of the following spatch to src/: @@ expression A, V; @@ - writel(V, A) + write32(A, V) @@ expression A, V; @@ - writew(V, A) + write16(A, V) @@ expression A, V; @@ - writeb(V, A) + write8(A, V) @@ expression A; @@ - readl(A) + read32(A) @@ expression A; @@ - readb(A) + read8(A) BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6 Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254864 Reviewed-on: http://review.coreboot.org/9836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21arm(64): Replace write32() and friends with writel()Julius Werner
This patch is a raw application of the following spatch to the directories src/arch/arm(64)?, src/mainboard/<arm(64)-board>, src/soc/<arm(64)-soc> and src/drivers/gic: @@ expression A, V; @@ - write32(V, A) + writel(V, A) @@ expression A, V; @@ - write16(V, A) + writew(V, A) @@ expression A, V; @@ - write8(V, A) + writeb(V, A) This replaces all uses of write{32,16,8}() with write{l,w,b}() which is currently equivalent and much more common. This is a preparatory step that will allow us to easier flip them all at once to the new write32(a,v) model. BRANCH=none BUG=chromium:451388 TEST=Compiled Cosmos, Daisy, Blaze, Pit, Ryu, Storm and Pinky. Change-Id: I16016cd77780e7cadbabe7d8aa7ab465b95b8f09 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 93f0ada19b429b4e30d67335b4e61d0f43597b24 Original-Change-Id: I1ac01c67efef4656607663253ed298ff4d0ef89d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254862 Reviewed-on: http://review.coreboot.org/9834 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-20Kconfig: rename CONSOLE_SERIAL_UART to DRIVERS_UARTPatrick Georgi
Some upstreaming patches missed that, so follow up. Change-Id: I28665c97ac777d8b0b0f909e64b32681ed2b98f7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9771 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-04-18vboot: make vboot2_verify_firmware returnDaisuke Nojiri
this allows each board to decide what to do after firmware verification is done. some board needs to return back to the previous stage and let the previous stage kick off the verified stage. this also makes it more visible what is going to happen in the verstage since stage_exit now resides in main(). BUG=none BRANCH=tot TEST=booted cosmos dev board. booted blaze in normal and recovery mode. built for all current boards. Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I3cb466cedf2a9c2b0d48fc4b0f73f76d0714c0c7 Original-Reviewed-on: https://chromium-review.googlesource.com/232517 (cherry picked from commit 495704f36aa54ba12231d396376f01289d083f58) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ic20dfd3fa93849befc2b37012a5e0907fe83e8e2 Reviewed-on: http://review.coreboot.org/9702 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17chromeos: Move memlayout.h/symbols.h into common directoryJulius Werner
Turns out there are uses for memlayout regions not specific to vboot2. Rather than add yet another set of headers for a single region, let's make the vboot2 one common for chromeos. BRANCH=veyron BUG=chrome-os-partner:35705 TEST=Booted Jerry, compiled Blaze, Cosmos, Ryu and Storm. Change-Id: I228e0ffce1ccc792e7f5f5be6facaaca2650d818 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c6d7aab9f4e6d0cfa12aa0478288e54ec3096d9b Original-Change-Id: I1dd7d9c4b6ab24de695d42a38913b6d9b952d49b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/242630 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9748 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17uart: pass register width in the coreboot tableVadim Bendebury
Some SOCs (like pistachio, for instance) provide an 8250 compatible UART, which has the same register layout, but mapped to a bus of a different width. Instead of adding a new driver for these controllers, it is better to have coreboot report UART register width to libpayload, and have it adjust the offsets accordingly when accessing the UART. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the rest of the patches integrated depthcharge console messages show up when running on the FPGA board Change-Id: I30b742146069450941164afb04641b967a214d6d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c30845f269ec6ae1d53ddc5cda0b4320008fa42 Original-Change-Id: Ia0a37cd5f24a1ee4d0334f8a7e3da5df0069cec4 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240027 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9738 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14tegra132: lock down VPRAaron Durbin
The GPU MMU won't function properly until it sees the VPR is locked down. Therefore, do the appropriate work. BUG=None BRANCH=None TEST=Built. Change-Id: I6011c75c1e6c231f2fa416e0057cb5805a88a2bb Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: ca9cc9917b98a148442468d1d1541a0408ab6c2c Original-Change-Id: I3601f419b561cee392391577ef8db66b9fbd8c1b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/242910 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/9660 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14rush: Enable dp displayJimmy Zhang
Add dp/sor supporting functions to enable dp panel. BUG=chrome-os-partner:34336 BRANCH=none TEST=build rush and ryu Change-Id: I1cc5a95ef5e3ea7cc701c1cb124a7eb5a5dbd872 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 795a7cddd36bd783cfdd6f1d3f7092bf48ebd8e7 Original-Change-Id: I336336dbbc5a772eec19ba96db8e7b50f6ea1497 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/238945 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9616 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-14ryu: display: Add function to pass mode info to payloadJimmy Zhang
This change is intended for code sharing. BUG=chrome-os-partner:34336 BRANCH=none TEST=build ryu and rush Change-Id: Ib83106f1c2d83c1d98b38567626f3169f2aec626 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9f7414132aaaa6a98663852219e17acbe919d704 Original-Change-Id: Idedb0c16e33a630c954c04767592c3a75c49944b Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/238944 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9615 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-14ryu: display: Set display shift clock dividerJimmy Zhang
Add and call display shift clock divider function to set shift clock divider. This change is also intended for code sharing on dc settings. BUG=chrome-os-partner:34336 BRANCH=none TEST=build ryu and rush Change-Id: I9ad1b32de50395720355bb2d00f5800c7f6c4b73 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 24a72fa3411652d54ae1f7d69db0a7293aad7877 Original-Change-Id: I01582c6863d31627ac93db9fddda93f4f78249cd Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/238943 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9614 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-14rush: Configure display related clock, pad, and powerJimmy Zhang
BUG=chrome-os-partner:34336 BRANCH=none TEST=build rush Change-Id: I9c2235ccc5571f1919dc013c62488390fe31dcbc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7468c14842c680be81620ad3fd2ea9ae056d525f Original-Change-Id: Iaf7f70727fc914b9bb2d063c9a30ece4451d40da Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/238942 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9613 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-14rush: Add dp related parametersJimmy Zhang
Add these parameters so that they can be specified in devicetree. BUG=chrome-os-partner:34336 BRANCH=none TEST=build ryu and rush Change-Id: I77ee16263e1ce6a8c32b3cd203c1b8a499514a8e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c3b254936e696f81ca7eeeb7f6968a5350352b59 Original-Change-Id: Iba47afe95c3889047a82582730be7a253fae76e7 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/238940 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9611 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-14CBFS: Automate ROM image layout and remove hardcoded offsetsJulius Werner
Non-x86 boards currently need to hardcode the position of their CBFS master header in a Kconfig. This is very brittle because it is usually put in between the bootblock and the first CBFS entry, without any checks to guarantee that it won't overlap either of those. It is not fun to debug random failures that move and disappear with tiny alignment changes because someone decided to write "ORBC1112" over some part of your data section (in a way that is not visible in the symbolized .elf binaries, only in the final image). This patch seeks to prevent those issues and reduce the need for manual configuration by making the image layout a completely automated part of cbfstool. Since automated placement of the CBFS header means we can no longer hardcode its position into coreboot, this patch takes the existing x86 solution of placing a pointer to the header at the very end of the CBFS-managed section of the ROM and generalizes it to all architectures. This is now even possible with the read-only/read-write split in ChromeOS, since coreboot knows how large that section is from the CBFS_SIZE Kconfig (which is by default equal to ROM_SIZE, but can be changed on systems that place other data next to coreboot/CBFS in ROM). Also adds a feature to cbfstool that makes the -B (bootblock file name) argument on image creation optional, since we have recently found valid use cases for CBFS images that are not the first boot medium of the device (instead opened by an earlier bootloader that can already interpret CBFS) and therefore don't really need a bootblock. BRANCH=None BUG=None TEST=Built and booted on Veyron_Pinky, Nyan_Blaze and Falco. Change-Id: Ib715bb8db258e602991b34f994750a2d3e2d5adf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e9879c0fbd57f105254c54bacb3e592acdcad35c Original-Change-Id: Ifcc755326832755cfbccd6f0a12104cba28a20af Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229975 Reviewed-on: http://review.coreboot.org/9620 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-13arm: Add bootblock_mainboard_early_init() for pre-console initializationJulius Werner
On most platforms, enabling the console and exception handlers are amongst the very first things you want to do, as they help you see what's going on and debug errors in other early init code. However, most ARM boards require some small amount of board-specific initialization (pinmuxing, maybe clocks) to get the UART running, which is why bootblock_mainboard_init() (and with it almost all of the actual bootblock code) always had to run before console initialization for now. This patch introduces an explicit bootblock_mainboard_early_init() hook for only that part of initialization that absolutely needs to run before console output. The other two hooks for SoC and mainboard are moved below console_init(). This model has already proven its worth before in the tegra124 and tegra132 custom bootblocks. BRANCH=None BUG=chrome-os-partner:32123 TEST=Booted on Pinky. Compiled for Daisy, Storm and Ryu. Change-Id: I510c58189faf0c08c740bcc3b5a654f81f892464 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f58e84a2fc1c9951e9c4c65cdec1dbeb6a20d597 Original-Change-Id: I4257b5a8807595140e8c973ca04e68ea8630bf9a Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/231941 Reviewed-on: http://review.coreboot.org/9603 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-13rush: Add and select DO_SOR_INIT config optionJimmy Zhang
Select DO_SOR_INIT to enable dp display api BUG=chrome-os-partner:34336 BRANCH=none TEST=build rush Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: Iddf19195722856865a7c06ce96492012ab729184 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 31492f51c030aeb7a3ac792a02665642ec999405 Original-Change-Id: I4daca43239235ca6d233c4457096d3b98fcaf65c Original-Reviewed-on: https://chromium-review.googlesource.com/234274 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-on: http://review.coreboot.org/9586 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13ryu: Add and select DO_DSI_INIT config optionJimmy Zhang
Enable display supporting functions by select DO_DSI_INIT BUG=chrome-os-partner:34336 BRANCH=none TEST=build ryu and rush Change-Id: Ie0e03506702ddab03d7f3fd2528c67c02126c7be Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 7133dfcd1afa221be92c6398221cf210d9eddf17 Original-Change-Id: I3a9f93107333ebf83ff235eb1b1e02fc747df3c6 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/234272 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9585 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13ryu: display: Move display api to mainboardJimmy Zhang
Display configuration is board specific. The change here is preparing for supporting other than dsi interface. BUG=chrome-os-partner:34336 BRANCH=none TEST=build ryu and test dev/rec mode, also build rush ok Change-Id: Ied39d5d539d2be4983ab70976bffbe51fccba276 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 36be6b2e35c6246d5384d71b9ab9d4ddbf17764a Original-Change-Id: I494a04f7d6c0dbad2d472f4c2cd0aabfb23b8c97 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/234271 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9584 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13ryu: display: Split dc functions from dsi display codeJimmy Zhang
dc supporting functions can be used for other than dsi display interfaces. This change is preparing for supporting sor display interface. BUG=chrome-os-partner:34336 BRANCH=none TEST=build ryu and test dev/rec mode, also build rush ok Change-Id: I8a310e188fae70d7726c4360894b392c4546e105 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a7ab7225e3419a0fd93894dbb9a959390f29945b Original-Change-Id: Id14cbd89457cb91c23526927a432f4eb7cc6291b Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/234270 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9583 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13t132: Add I2S1 support to funitTom Warren
Used for audio on Rush/Ryu. I2S1/DAP2 provides the audio 'stream' for the dev/rec mode 'beeps'. BUG=chrome-os-partner:32582 BRANCH=none TEST=With follow-on CLs that make use of this support, audio beeps (via VbExBeep) can be heard on Rush. Built both Rush and Ryu OK. Change-Id: Iea5559db4431e48001adbbce17fa0f3aaaf8387c Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 2bd701a5f4186e49739b25f4afd5000d5d9b4970 Original-Change-Id: Ia8c32303979f25300e22b5a14609d9d9d5ce3132 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/233670 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9576 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13t132: add RAM repair to cluster 1Yen Lin
RAM repair has to be performed to cluster 1 also. BRANCH=none BUG=none TEST=Test on Rush and make sure RAM repair completes Change-Id: I0daf969a995a2be152270bc06501eaf086a13a97 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 6b07894cc737cb192f68e254d522b55d8ca3b2f3 Original-Change-Id: I458e0a66d76318c6a4aa82547c9037c7b969f1e1 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/239360 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9592 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10tegra132: psci: add cpu_on/off supportJoseph Lo
The CPU on/off functions are the method for the Kernel to support CPU hot-plug function in PSCI. To support this, we still need flow controller support to capture the WFI from the CPU and inform PMC to power gate the CPU core. On the other path, we turn on the CPU by toggling the PMC and use flow controller to let go when the power is steady. BUG=chrome-os-partner:32136 BRANCH=None TEST=built the kernel with PSCI enabled, check both of the CPUs are coming up, test the CPU hot-plug is working on Ryu Change-Id: If2c529b6719c5747d5aea95fb5049b2d7353ff17 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0f078e89daad1c4d8b342a395f36b3e922af66f5 Original-Change-Id: Ie49940adb2966dcc9967d2fcc9b1e0dcd6d98743 Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/231267 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9542 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Make non-vboot2 memlayout more usefulFurquan Shaikh
Update non-vboot2 memlayout: 1) Add timestamp region 2) Increase ramstage size 3) Change name from memlayout_vboot.ld to memlayout.ld so that any non-vboot upstream board can also use this layout. BUG=None BRANCH=None TEST=Compiles and boots to kernel prompt on ryu with vboot selected instead of vboot2. Change-Id: Idced98f9df7cdbab5f62cd1e382c6046ade1d867 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 20fffa282b20fb32ce2ff687f4479be630f90fcf Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I91accd54efc53ab563a2063b9c6e9390f5dd527f Original-Reviewed-on: https://chromium-review.googlesource.com/231547 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9536 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Change memlayout to have PRERAM and POSTRAM CBFS CacheFurquan Shaikh
Instead of having unified CBFS_CACHE and limiting the POSTRAM Cache size, split them into PRERAM and POSTRAM CBFS_CACHE. BUG=None BRANCH=None TEST=Compiles successfully for both rush and ryu. Boots to kernel prompt on ryu. Change-Id: I2a70df22fe5bae23e05cdf1b8a300369c7ccf87d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b93bc06de76cab0a1ec9a56e12c9a6942a430893 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: Iab21ff5c7ca880b6bd18846e5d8d71c26dff56cf Original-Reviewed-on: https://chromium-review.googlesource.com/231546 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9535 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Bump up ramstage to 256KFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully Change-Id: Ia4875948e0be5e084f54f1acb1c5acf5cdabad94 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 038e9abe2c6e1813cad50bb768e1f66cdd056ccd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: If5df6e0dbf85c837f9ada6a967fd3d01b5230307 Original-Reviewed-on: https://chromium-review.googlesource.com/232002 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9533 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: prepare cpu startup in psciAaron Durbin
In order to start CPUs while in secmon/psci one needs to set up the proper SoC state. Therefore, refactor the current CPU startup API to allow for this by adding cpu_prepare_startup() and start_cpu_silent(). BUG=chrome-os-partner:32136 BRANCH=None TEST=Built and booted kernel. Change-Id: I1424500f6c9398f7d44350949c25bb3d4832cec7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 70f9cf67085b345b529b41dd6554e37d38a5b350 Original-Change-Id: I842a391d3e27ddbfcdef1a2d60e3c66e60f99c77 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/231936 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9531 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Increase size of bootblock due to overflowTom Warren
The bootblock on Rush had bumped up into the verstage allocation, causing the build to break. Reduced verstage from 60K to 58K and increased bootblock from 20K to 22K. Rush and Ryu both build fine now. BUG=none BRANCH=none TEST=Built both Rush and Ryu OK. Verifed verstage size using cbfstool and it's around 55K, so plenty of room. Change-Id: Iaa3a5838c5235ec78c740a977bc032d8b5e270ef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 928a4d2d1efabe1e1d6a7fadc22ee0ac4269190e Original-Change-Id: I7018f027d72d5e8aeb894857a5ac6a0bdc1de388 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/230824 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9528 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: always bring up PLLDAaron Durbin
The kernel does not correctly function without PLLD being enabled. Additionally, PLLD can be the source for other clocks in the system. Therefore, initialize PLLD to 300MHz unconditionally at BS_DEV_INIT time in ramstage. BUG=chrome-os-partner:33825 BRANCH=None TEST=Built and booted ryu with display coming up both in dev mode as well as normal mode. Change-Id: Ib2a60bb9aafc03dc23aa932a480184d87f677c65 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c49f964b55c3c33d03b95363277b262b679e740 Original-Change-Id: Ic5905e25051a042cea5010b8c6d61b1fb89a0a81 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230774 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Sean Paul <seanpaul@chromium.org> Reviewed-on: http://review.coreboot.org/9525 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: rename clock_display() to clock_configure_plld()Aaron Durbin
Provide an explicit name for configuring PLLD. The new name, clock_configure_plld(), provides an explicit semantic to what it is doing. Also, provide the printk() about actual frequency vs requested frequency as most of the callers were doing this themselves. BUG=chrome-os-partner:33825 BRANCH=None TEST=Built and booted on ryu. Change-Id: I1880f0f305e69674922b070d282aac3acdc86aad Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c51d5b0864d8bd0db5927380803cec46ccd74d48 Original-Change-Id: If744332b466d9486f83b08d0ab4e9006fadfecdd Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230773 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Sean Paul <seanpaul@chromium.org> Reviewed-on: http://review.coreboot.org/9524 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Set dc to resize the difference between framebuffer and panelJimmy Zhang
Scale framebuffer resolution to panel resolution. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: Idb19f5871605e878ea380cc8f701a377350681fb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d2f08a704fe3a7be1e0448e4ed864c69b50d6838 Original-Change-Id: I5ac01539da3712cd6afdb8d08513da399ace0f92 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229494 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9522 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Add framebuffer parametersJimmy Zhang
Framebuffer line size and number of lines can have different values than panel's resolution. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: I228f1dd7fafc6577a8e8a987ff31ba73f7a655ed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9a4929dc5831076f2f2a5dd2e13f24b3477e197b Original-Change-Id: Iedeef796f02286bb03920413420f8952cf34334a Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229915 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9520 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Pass panel spec to lib_sysinfoJimmy Zhang
panel spec such as resoultion, bits per pixel are needed to pass to depthcharge/payload for displaying bitmap onto panel. Enable display code only if mainboard selects MAINBOARD_DO_NATIVE_VGA_INIT. Otherwise build breaks for boards that do not support display init yet. BRANCH=none BUG=chrome-os-partner:31936 TEST=Compiles for both rush and ryu. Display comes up for ryu in both normal and dev mode. Change-Id: I81b4d289699e7b0c2758ea1a009cbabaf8a2ce28 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b9b42486f203d332f6068ccd6f4a1a982d327a6b Original-Change-Id: I5c8fde17d57e953582a1c1dc814be4c08e349847 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Commit-Id: ce2883b21d3fbfd54eac3a355fb34ec70e9f31ad Original-Change-Id: Ib4a3c32f1ebf5c6ed71c96a24893dcdee7488b16 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/9519 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Expand ramstage size to 208k (from 192k)Jimmy Zhang
BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: Ief81194381193ef9acc7c1786915945d66f2efdb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 826ce3730f6d26c9f7a8c3f0429ab14a213172e8 Original-Change-Id: Icc62c776db6f8d8b27615c467518e9753627e72c Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229914 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9518 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Add dsi driverJimmy Zhang
Add dsi and related dc, panel configuration functions. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: I8440b6dfccc7ed7cd280a0df3a98cbc7b7d66070 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fb08563f67daf9a616b60609c4523b823d34f8e3 Original-Change-Id: I87b8047e23ebe114af353fcce5924a46621d16d2 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/227202 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9517 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Add panel mode specJimmy Zhang
BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: I23dae7bfdeb8e33a6ea5c9de0fb953a7c4d31345 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6cac26deeea0e024f2f6bd1850a41894f801bc5f Original-Change-Id: Ie77f8df4ba3425e0dd4e4243dd38157480de0efb Original-Reviewed-on: https://chromium-review.googlesource.com/229913 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9515 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: dsi: Enable panel related vdd and clocksJimmy Zhang
BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: Ia10bf7ae3bde389e883970f9a6ee931c32b8172b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f26902364b6a453adb850abfb0c4ce9686e99b5d Original-Change-Id: I68b92608098959cca14324bfc7e1e58389205989 Original-Reviewed-on: https://chromium-review.googlesource.com/226905 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9514 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Increase space for romstage in memlayoutFurquan Shaikh
Stack and Timestamp need lesser than 2K and since romstage is running out of memory, adjust the overall memory assignment. BUG=chrome-os-partner:33676 BRANCH=None TEST=Compiles and boots to kernel prompt. Change-Id: I5076252ae87268bd4e964c282d1cc337e0ea4e70 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f2d5d29e6f0f5058a41ed30aae98f79574e31609 Original-Change-Id: I0134f25dd49f2940bb159d131aaee12f81e13ef7 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229001 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/9512 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10vboot: move vboot files to designated directoryDaisuke Nojiri
This moves vboot1 and vboot2 files to their designated directory. Common code stays in vendorcode/google/chromeos. BUG=none BRANCH=none TEST=built cosmos, veyron_pinky, rush_ryu, nyan_blaze, samus, parrot, lumpy, daisy_spring, and storm. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ia9fb41ba30930b79b222269acfade7ef44b23626 Original-Reviewed-on: https://chromium-review.googlesource.com/222874 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit cbfef9ad40776d890e2149b9db788fe0b387d210) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia73696accfd93cc14ca83516fa77f87331faef51 Reviewed-on: http://review.coreboot.org/9433 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10google/rush: Add I2C1 init and audio clock enable/resetsTom Warren
This should allow the max98090 codec to play beeps via AHUB/I2S1 thru the depthcharge sound driver. BUG=none BRANCH=none TEST=Saw max98090 codec init signon and register dump. No sound yet. Change-Id: I1ee0b61f5cbfe587ebd16b7dd9dce08d9d62c2c5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f4ee2ce3704711a9e00531b7599a1bcf194203ec Original-Change-Id: I0bc8401e76b2c80a01083ac933a39f6cd4d1b78a Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229496 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Mike Frysinger <vapier@chromium.org> Reviewed-on: http://review.coreboot.org/9429 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Add routine to enable all audio periphs under AHUBTom Warren
If all devices under AHUB (AUDIO/I2S/DAM/ADX/etc) aren't clocked and taken out of reset, any access to any audio peripheral will hang the system. BUG=none BRANCH=none TEST=built both Rush and Ryu OK. Change-Id: Iee8e33f005c5abaf09a14104c0b243b06eb4af24 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0016bd533864942225f2fb8e08ce871a186f2746 Original-Change-Id: I741d5ba4dd8bd963b6d261fbf41cfb77c274cb79 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229910 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Mike Frysinger <vapier@chromium.org> Reviewed-on: http://review.coreboot.org/9428 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Add I2C1 support to funitTom Warren
I2C1 was missing in the funit/i2c/addressmap tables/code. BUG=none BRANCH=none TEST=Built Rush and Ryu. Built Rush w/code in mainboard.c to enable I2C1 for the MAX98090 audio codec - codec could be configured. Change-Id: I0c678d21546eedb7404a1d3d4329da777430fc97 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4b623097a2adc4464c17bceed96ec3838beda985 Original-Change-Id: Ibe4f012fa2d427b95cd4672687132b47576b6a9a Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229574 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9427 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: Implement PSCI command supportAaron Durbin
Provide support for SoCs to participate in PSCI commands. There are 2 steps to a command: 1. prepare() - look at request and adjust state accordingly 2. commit() - take action on the command The prepare() function is called with psci locks held while the commit() function is called with the locks dropped. No SoC implements the appropriate logic yet. BUG=chrome-os-partner:32136 BRANCH=None TEST=Booted PSCI kernel -- no SMP because cmd_prepare() knowingly fails. Spintable kernel still brings up both CPUs. Change-Id: I2ae4d1c3f3eac4d1060c1b41472909933815d078 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 698d38b53bbc2bc043548792cea7219542b5fe6b Original-Change-Id: I0821dc2ee8dc6bd1e8bc1c10f8b98b10e24fc97e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226485 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9423 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-04-10arm64: secmon: add entry point for turned on CPUsAaron Durbin
Newly turned on CPUs need a place to go bring its EL3 state inline with expectations. Plumb this path in for CPUs turning on as well as waking up from a power down state. Some of the infrastructure declarations were moved around for easier consumption in ramstage and secmon. Lastly, a psci_soc_init() is added to inform the SoC of the CPU's entry point as well do any initialization. BUG=chrome-os-partner:32112 BRANCH=None TEST=Built and booted. On entry point not actually utilized. Change-Id: I2af424c2906df159f78ed5e0a26a6bc0ba2ba24f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dbefec678a111e8b42acf2ae162c1ccdd7f9fd40 Original-Change-Id: I7b8c8c828ffb73752ca3ac1117cd895a5aa275d8 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228296 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9422 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-04-10ryu: Add display_start apiJimmy Zhang
Enable display only developer and recovery mode. Will add in the actual display supporting functions in coming patches. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: I0d312fd132dc310813432f4d8a28ad16c9bb36aa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dd1bd56e83532c77d675f72b301b413cbcf3f489 Original-Change-Id: Idfa24d23c81baaedb944d2b9835255edad4e422b Original-Reviewed-on: https://chromium-review.googlesource.com/226904 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-on: http://review.coreboot.org/9421 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-04-10gpio: Extend common GPIO header, simplify function namesJulius Werner
We've had gpiolib.h which defines a few common GPIO access functions for a while, but it wasn't really complete. This patch adds the missing gpio_output() function, and also renames the unwieldy gpio_get_in_value() and gpio_set_out_value() to the much easier to handle gpio_get() and gpio_set(). The header is renamed to the simpler gpio.h while we're at it (there was never really anything "lib" about it, and it was presumably just chosen due to the IPQ806x include/ conflict problem that is now resolved). It also moves the definition of gpio_t into SoC-specific code, so that different implementations are free to encode their platform-specific GPIO parameters in those 4 bytes in the most convenient way (such as the rk3288 with a bitfield struct). Every SoC intending to use this common API should supply a <soc/gpio.h> that typedefs gpio_t to a type at most 4 bytes in length. Files accessing the API only need to include <gpio.h> which may pull in additional things (like a gpio_t creation macro) from <soc/gpio.h> on its own. For now the API is still only used on non-x86 SoCs. Whether it makes sense to expand it to x86 as well should be separately evaluated at a later point (by someone who understands those systems better). Also, Exynos retains its old, incompatible GPIO API even though it would be a prime candidate, because it's currently just not worth the effort. BUG=None TEST=Compiled on Daisy, Peach_Pit, Nyan_Blaze, Rush_Ryu, Storm and Veyron_Pinky. Change-Id: Ieee77373c2bd13d07ece26fa7f8b08be324842fe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9e04902ada56b929e3829f2c3b4aeb618682096e Original-Change-Id: I6c1e7d1e154d9b02288aabedb397e21e1aadfa15 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220975 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9400 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-09soc: Use DEVICE_NOOP macro formalism over static stub funcEdward O'Callaghan
Change-Id: Ice7e27230010ffc48948f952394e849533f94085 Signed-off-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-on: http://review.coreboot.org/8989 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-09tegra132: configure debug uart to 115200n8 in tegra_lp0_resumeYen Lin
Need to configure debug uart port to have proper baudrate/width/parity. Hard-code it to 115200n8. BUG=chrome-os-partner:32015 BRANCH=None TEST=successfully suspend/resume on Rush/Ryu Change-Id: I502fd8361baf2bea642fabbc4d5e126da5411ba3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8c70625ad41efca9117c8682113b226e929e93c5 Original-Change-Id: I6a96c80654ce52f5b877fd46995ca8c1aceb7017 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226407 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9391 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-04-09arm64: psci: add node hierarchyAaron Durbin
In order to properly support more arm64 SoCs PSCI needs to handle the hierarchy of cpus/clusters within the SoC. The nodes within PSCI are kept in a tree as well as a depth-first ordered array of same tree. Additionally, the PSCI states are now maintained in a hierachal manner. OFF propogates up the tree as long as all siblings are set to OFF. ON propogates up the tree until a node is not already set to OFF. The SoC provides the operations for determining how many children are at a given affinity level. Lastly, the secmon startup has been reworked in that all non-BSP CPUs wait for instructions from the BSP. BUG=chrome-os-partner:32136 BRANCH=None TEST=Can still boot into kernel with SMP. Change-Id: I036fabaf0f1cefa2841264c47e4092c75a2ff4dc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 721d408cd110e1b56d38789177b740aa0e54ca33 Original-Change-Id: I520a9726e283bee7edcb514cda28ec1eb31b5ea0 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226480 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9390 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-04-08t132: Add vboot2 supportFurquan Shaikh
BUG=chrome-os-partner:32684 BRANCH=None TEST=Compiles successfully and boots to kernel prompt using vboot2 Original-Change-Id: Ibf7666d273e4d1af719c60d3f02bddcb4461f4bd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/221576 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 8335915940ae9ba9e51e360df6963a27b05d6324) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I7d3d5cda4c4be945931d9133ab18680dac1dcefe Reviewed-on: http://review.coreboot.org/9430 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-04-08timer: Add generic udelay() implementationAaron Durbin
Add GENERIC_UDELAY Kconfig option so that a generic udelay() implementation is provided utilizing the monotonic timer. That way each board/chipset doesn't need to duplicate the same udelay(). Additionally, assume that GENERIC_UDELAY implies init_timer() is not required. BUG=None BRANCH=None TEST=Built nyan, ryu, and rambi. May need help testing. Change-Id: I7f511a2324b5aa5d1b2959f4519be85a6a7360e8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1a85fbcad778933d13eaef545135abe7e4de46ed Original-Change-Id: Idd26de19eefc91ee3b0ceddfb1bc2152e19fd8ab Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219719 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9334 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-08tegra124: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns tegra124 to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Nyan, Nyan_Big and Nyan_Blaze. Change-Id: Ia82ab86b2af903690cc6c9d310f7bdda3425ea7c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4d23774e071ec22781991ff20fbf63802f620c88 Original-Change-Id: Ia126cff8590117788d1872e50608c257d2659c1f Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224504 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9326 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-08tegra132: Remove clamp_tristate_inputs() callTom Warren
As per NV SysEng, setting PINMUX_CLAMP_INPUTS=1 is now considered a bad thing. It clamps _all_ tristated inputs to zero, and isn't really the panacea for duplicated pinmux mappings as was stated previously. BUG=None BRANCH=None TEST=Built both Rush and Ryu OK. Tested on Rush, booted kernel OK. Change-Id: I7d6982a18a772efda7f1d3bf0dcb0d4d0a5bed8f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c5f77fa31961d39dd7b4bd2902288ead9ad80100 Original-Change-Id: I566c4516b34686b744a47a2b0c18c4b801456727 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/224032 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9346 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-08tegra132: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns tegra132 to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Rush_Ryu. Change-Id: I5cdf4008a65db84f15c937ef53aab5e4d3ef24c4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d5c5c63d7b6399d3eb8a211b15d47829fe93a591 Original-Change-Id: Ifafd4d42d4fb04a1c37e8a5f23877c2b550cf44c Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224505 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9369 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-07tegra132: Provide weak implementation of usb_setup_utmip in funitcfg.cFurquan Shaikh
Provide a weak implemenation of usb_setup_utmip function for those stages that do not include usb.c. BUG=chrome-os-partner:32684 BRANCH=None TEST=Compiles successfully Change-Id: Ia659b7f64e6c3e23053837337ccd267d4c179fba Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 49487e5af4471bff708d8939492af15fb5cb9e64 Original-Change-Id: Ib235cf039a17204ef7e06d545a3c86b75aff5b4c Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/221575 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9325 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-04-07kconfig: drop intermittend forwarder filesStefan Reinauer
With kconfig understanding wildcards, we don't need Kconfig files that just include other Kconfig files anymore. Change-Id: I7584e675f78fcb4ff1fdb0731e340533c5bc040d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9298 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-06New mechanism to define SRAM/memory map with automatic bounds checkingJulius Werner
This patch creates a new mechanism to define the static memory layout (primarily in SRAM) for a given board, superseding the brittle mass of Kconfigs that we were using before. The core part is a memlayout.ld file in the mainboard directory (although boards are expected to just include the SoC default in most cases), which is the primary linker script for all stages (though not rmodules for now). It uses preprocessor macros from <memlayout.h> to form a different valid linker script for all stages while looking like a declarative, boilerplate-free map of memory addresses to the programmer. Linker asserts will automatically guarantee that the defined regions cannot overlap. Stages are defined with a maximum size that will be enforced by the linker. The file serves to both define and document the memory layout, so that the documentation cannot go missing or out of date. The mechanism is implemented for all boards in the ARM, ARM64 and MIPS architectures, and should be extended onto all systems using SRAM in the future. The CAR/XIP environment on x86 has very different requirements and the layout is generally not as static, so it will stay like it is and be unaffected by this patch (save for aligning some symbol names for consistency and sharing the new common ramstage linker script include). BUG=None TEST=Booted normally and in recovery mode, checked suspend/resume and the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies with ToT and looked for red flags. Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614 Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213370 Reviewed-on: http://review.coreboot.org/9283 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-06tegra132: Add tegra_lp0_resume codeYen Lin
BUG=chrome-os-partner:32015 BRANCH=None TEST=successfully suspend/resume on Rush/Ryu Signed-off-by: Yen Lin <yelin@nvidia.com> Change-Id: I279e42fd055805f0060951d272571bda66514ea6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a02452e431d9aa6245fb2421773d66fc416d0a6e Original-Change-Id: I11cca0a8f5e7a36c1fff690c8070c74706348949 Original-Reviewed-on: https://chromium-review.googlesource.com/214580 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Yen Lin <yelin@nvidia.com> Original-Tested-by: Yen Lin <yelin@nvidia.com> Reviewed-on: http://review.coreboot.org/9102 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04t132: Enable SMMU translationsFurquan Shaikh
BUG=None BRANCH=None TEST=Verified by reading back the value of SMMU_CONFIG register that enable bit is set to 1 Original-Change-Id: Iccc870141f9b9729971bf12119f9f3dae8181a43 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/222770 Original-Reviewed-by: Olof Johansson <olofj@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit a06b36f9003d801709d83a8faed6fc04bb91df1b) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Iae3949940a5a0efa2761542974d5c209178ce397 Reviewed-on: http://review.coreboot.org/9258 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04tegra132: Store ODMDATA from BCT into PMC scratch for use by kernelTom Warren
In able to do earlyprintk spew on LP0 resume, the kernel needs to know the board UART. ODMDATA (in bct/odmdata.cfg) contains this info, and the kernel looks for it in PMC_SCRATCH20. Fetch the ODMDATA word from the BCT copy stored in IRAM by the BootROM. BUG=chrome-os-partner:32015 BRANCH=none TEST=Built for Rush and Ryu OK. Dumped PMC_SCRATCH20 in TegraShell on Rush and confirmed value is what's in odmdata.cfg. Original-Change-Id: I63f33558ee8b00bd6c1e313efcd531e1d5fc67eb Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/222402 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3f6a21afdb81f7d2ae90119c563535b4c87c9ade) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I9819ffdf0f7618f0dd8dc50f81b5b26d6f94bfbd Reviewed-on: http://review.coreboot.org/9257 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04tegra132: remove framebuffer reservationAaron Durbin
There's no need to reserve the framebuffer within coreboot. If the payloads need a framebuffer they can allocate one themselves. BUG=chrome-os-partner:31355 BRANCH=None TEST=Built and booted on ryu. Original-Change-Id: I8d8b159e7fdd877e392193c5474a7518e9b3ad21 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221726 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 1ff8da9fed414fceeda3f94b296312f4531b320f) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I4e7c0417824f2be9836b1bc2bb99322c78490ca2 Reviewed-on: http://review.coreboot.org/9256 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04tegra124: use known-good drive for fast-train onlyNeil Chen
A higher drive setting is used for fast link training, once the link training succeeds, a known-good drive setting will be used for the main stream transactions. For full link training sequence, the sink devices may ask for a preferred drive setting, thus this drive setting should be used for the main stream transactions too. BUG=chrome-os-partner:32129 TEST=all panels on blaze/big devices work fine. Original-Change-Id: Icc540650dc1329af07fd9ee4661eb7fad435fde4 Original-Signed-off-by: Neil Chen <neilc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219544 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 13d6accfdbe678e785851057f0800a3bbef11bea) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: If2fe7d5621f15aa3134d2a3920220e149bb64be6 Reviewed-on: http://review.coreboot.org/9248 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-04tegra124: add support for full DP link trainingNeil Chen
The original dp driver supports only fast link training and a special drive setting is used for the link training sequence. This might not be accepted by all panels. The better way is to go through full link training sequence to negotiate for a best drive setting. With the change, dp driver will try fast link training first, this is same as before. If it fails in fast link training, will try full link training. BUG=chrome-os-partner:32129 TEST=all panels on blaze/big devices work fine. Original-Change-Id: I6f3402c4c5993a156c965c7f52b011d336a2946f Original-Signed-off-by: Neil Chen <neilc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219543 Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 24966517d41252384af3c2784def36aebad42434) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I3e7e7e749e5c8a9f07ac6132859fcad6fc96c39c Reviewed-on: http://review.coreboot.org/9247 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-04-03tegra132: implement platform_prog_run()Aaron Durbin
The tegra132 SoC is currently booting up on the AVP cpu which bootstraps the rest of the SoC. Upon exiting romstage it runs ramstage from its faster armv8 core. Instead of hard coding the stage loading operations use run_ramstage(). Change-Id: Ib9b3eecf376ae022f910295920a085bde6e17f9f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8848 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-03tegra124: implement platform_prog_run()Aaron Durbin
The tegra124 SoC is currently booting up on the AVP cpu which bootstraps the rest of the SoC. Upon exiting bootblock it runs romstage from its faster armv7 core. Instead of hard coding the stage loading operations use run_romstage(). Change-Id: Idddcfd5443f08d4dd41e1d9b71650ff6d4b14bc4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8847 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-02Nyans: replace cpu_reset with hard_resetDaisuke Nojiri
The existing cpu_reset does board-wide reset, thus, should be renamed. BUG=none BRANCH=none TEST=Built firmware for Nyans. Ran faft on Blaze. Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I5dc4fa9bae328001a897a371d4f23632701f1dd9 Original-Reviewed-on: https://chromium-review.googlesource.com/212982 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 29753b9c1dfe7ecd156042d69b74e9fe4244f455) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I98eca40c50637bda01a9029a904bca6880cd081f Reviewed-on: http://review.coreboot.org/9179 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-31cbfs: remove cbfs_core.h includesAaron Durbin
Some of the files which include cbfs_core.h don't even need the header definition while others just need the cbfs API which can be obtained from cbfs.h. Change-Id: I34f3b7c67f64380dcf957e662ffca2baefc31a90 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9126 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-30Update hex values to CBFS binary name types in MakefilesMartin Roth
These binaries were being added to CBFS using hexadecimal values instead of the CBFS binary type names. The same value was being used in different places for different things. For example, the value 0xAB is used for SPDs, MRC & FSP binaries. This patch uses CBFS type names instead of hex values everywhere a hex value was previously used. Change-Id: Id5ac74c3095eb02a2b39d25104a25933304a8389 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8978 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-28tegra132: Add support for pmc_rst_status get and printFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully and pmc rst status POR is seen. Change-Id: Ic09cb46d9be7670e467543e42b251efb1a4313d0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5dbfae6bbc0f4f30e216e37b515f4120f7833a38 Original-Change-Id: Id0c2b208222deaf099b8938ba583551979588d52 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220721 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9106 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: Replace use of clk_rst with CLK_RST_REGFurquan Shaikh
Also, get rid of unused clk_rst variables. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I6487162454159a81b31fe0d6d39c2bdbed3f859a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 030081fe85fc9609fdf2003cf51b7350e08f0429 Original-Change-Id: I880ae5c396c33006f6b184cca7f171e4373f4016 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220720 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9105 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: measure romstage timingsAaron Durbin
Measure the MTS load time, MTS initialization time, and the ramstage verification/load time. BUG=None BRANCH=None TEST=Booted and noted timings. Change-Id: I1eb1e3a73316a3fa76ef8e73314bedde34c6c582 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b5b34a3abd388359b7d1cba5a858e4e5a402b476 Original-Change-Id: I71119689182e86406d5052f007908152d41e9092 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219715 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9103 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132/rush/ryu: Use CLK_RST_REG instead of &clk_rst->...Furquan Shaikh
BUG=chrome-os-partner:31821 BRANCH=None TEST=Built and booted to kernel prompt on ryu. Rush compiled successfully. Change-Id: I63ba55c53094c185d72dcb5c5d0d766461989806 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4a9aa565244bae5659e458ea90064eb5b803d574 Original-Change-Id: I5b00fbcb8e414c67563f1ad548f84c281898f939 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219392 Original-Reviewed-by: Tom Warren <twarren3959@gmail.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9100 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: Clean up clock register writesFurquan Shaikh
Clean up functions to write to clk_enb and rst_dev registers and add clock_disable and clock_set_reset functions to provide a complete API for updating the registers. BUG=chrome-os-partner:31821 BRANCH=None TEST=Compiles successfully and boots to kernel prompt on ryu. Compiles successfully on rush Change-Id: Ib0b7e3fc322f18be396ecf3b02b2399d4ba33e9b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1bb222adc22c7e26077dfb2ba6e4d41a4965d183 Original-Change-Id: Icb8081fe3d80174c920eaaecf5cbb0aa912d5b19 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219191 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9099 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-03-28Ryu: Move I2C6 init to ramstageTom Warren
BUG=chrome-os-partner:31820 BRANCH=none TEST=Dumped Speaker Driver (AD SSM4567) regs on Ryu, looks good. Change-Id: I9b094e9d22726d67d41f2ce78088f361c73895fd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c0bfb5f747f55009b7c2b2ba4b24d91443b1639 Original-Change-Id: Idd5b95cfec7d3ade7508393b81ab3049ce15a2fb Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/218950 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9095 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28Ryu: Rewrite I2C6 mux initTom Warren
Do the absolute minimum needed to allow the DPAUX mux ctl write for I2C6. This leaves HOST1X off (reset and clock disabled) to avoid a conflict with any kernel display driver init. I2C6 init/enable will be moved to ramstage in the next CL. BUG=chrome-os-partner:31820 BRANCH=none TEST=Dumped Speaker Driver (AD SSM4567) regs on Ryu, looks good. Change-Id: I42106778a26c5a1d1483cc308b8314599c391539 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 24a9ebfda31c620b24e5c765dc950b87e3e5587b Original-Change-Id: I0760222f1d7ccee207ae9871aeed3e2ddbca3dca Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/218900 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9093 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: remove private spin table implementationAaron Durbin
Support the generic spin table code instead of having the one-off implementation. BUG=chrome-os-partner:32082 BRANCH=None TEST=Built and booted to kernel w/ smp. Both w/ and w/o secure monitor. Change-Id: I8557298d1a159b70818cbd8864470ff0d8a46fb1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8d89af95a7919f0b8acc92d82f3abda965514ccf Original-Change-Id: I24d56a30fdabd7a35ebc28dcc355c675de823a51 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218655 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9085 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: Add secmon supportFurquan Shaikh
BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully and secmon loads and jumps to payload successfully. Change-Id: I929cf2c938fb5d8c20e13fbd1fdbd349378914ff Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2e5d6adc63c4d820417985e34f1f04810b38422b Original-Change-Id: I442546178ad945e7639a99dd2943d13a69b06d09 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214372 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9081 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: use generic GIC driverAaron Durbin
As the arm64 boot flow handles initializing the GIC by way of the driver provide the SoC support for that driver and use it. BUG=chrome-os-partner:31945 BRANCH=None TEST=Built and booted kernel on ryu. Change-Id: I6ba20339be8fc823e241b4299ad6c3deb82799fa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 582cd9cef58e27aef2ce9c9b4fba4a78365bec6e Original-Change-Id: I34efaf28369377f353b4c51d20d19c9433befda4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217514 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9077 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-18 15:37:24 +0000