summaryrefslogtreecommitdiff
path: root/src/soc/nvidia/tegra210
AgeCommit message (Collapse)Author
2015-08-09license headers: Drop FSF addresses againPatrick Georgi
Some FSF addresses found their way back into our tree. Change-Id: I34b465fc78734d818eca1d6962a1e62bf9d6e7f3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11145 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-29t210: lp0_resume: implement MBIST workaroundYen Lin
As in cold boot path, implement MBIST workaround in lp0 resume path. BUG=chrome-os-partner:40741 BRANCH=None TEST=Tested on Smaug; able to suspend/resume Change-Id: I997009ecb0f52fb5a47c62b8daea33e472ec2664 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 4b1f80ea4c1d3782eb9f2c90c2a8d7b2e97ba050 Original-Change-Id: Ib4944401e1df02bf0aab1e78db7e14ef56c7f829 Original-Reviewed-on: https://chromium-review.googlesource.com/287287 Original-Tested-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Benson Leung <bleung@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Yen Lin <yelin@nvidia.com> Reviewed-on: http://review.coreboot.org/11071 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-24tegra210: Fix parameter order of write32()Stefan Reinauer
The correct function prototype is void write32(void *addr, uint32_t val) BUG=chrome-os-partner:38073 BRANCH=none TEST=build lp0 code and see it succeed. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Change-Id: Icadc9e2d142e5a222509e894f43b0c8a70eed031 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b46635d9d3ee1ca364e7ad6d6dd7ea9efa9dedbc Original-Change-Id: Id2b6847af80dfddcb3b7133a663becb78ed477ba Original-Reviewed-on: https://chromium-review.googlesource.com/285544 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Original-Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/11049 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-24tegra lp0: fix checkpatch errorsStefan Reinauer
The checkpatch.pl scripts complains about the placing of the inline keyword: ERROR: inline keyword should sit between storage class and type Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BUG=chrome-os-partner:38073 BRANCH=none TEST=repo upload works ;) Change-Id: Ibd2b8a437eda2fc720f8fc32c5821bae3be41d12 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d20c0d34240966d5ae39c1667d4486b4341e183b Original-Change-Id: I36d600c4677c622c334d849bf260323592a8a4fc Original-Reviewed-on: https://chromium-review.googlesource.com/285543 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Original-Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/11048 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-23t210: audio: add CLK_V_EXTPERIPH1 clockYen Lin
For audio to work, need to enable CLK_V_EXTPERIPH1 clock. This CL is needed because after MBIST workaround is applied, CLK_V_EXTPERIPH1 clock is default to be off. BUG=None BRANCH=None TEST=Tested on Smaug, hear beep when press Ctrl+U at serial console when DEV screen is showing Change-Id: I32dccc0c7983f8fa86812d845a2f00ac9881d521 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 149d04e6ba642734d5ea36cac8206fad3ac13ce0 Original-Change-Id: Ifa1afb0798c1039c8ea9084b5a7ee3b09b4d70ac Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285604 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/11041 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-23t210: Enable WRAP to INCR burst type conversion in MSELECTYen Lin
Enable WRAP to INCR burst type conversion in MSELECT. MSELECT CONFIG register can only be accessed by CPU. So do it in ramstage when CPU is started. BUG=None BRANCH=None TEST=tested on Smaug, still boot to kernel Change-Id: Iee05531c45e566f47af24870be6068247c2d9a00 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 21d9e4d3a8827f7bba57c03ca36b702aaba1ce20 Original-Change-Id: I6a241455b28f24b8756ad09bf7605a2e7e52af57 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282418 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/11040 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-23t210: implement MBIST workaroundYen Lin
MBIST has left some registers in non-suggested states. This CL restores CAR CE's, SLCG overrides & PLLD settings. BUG=None BRANCH=None TEST=tested on Smaug, still boot to kernel Change-Id: I1ddb19dd9fb6d8fb4d36e67eedeb847c6fd9f774 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 37a1c90c6deb351b2ae2caa03e5076553126744b Original-Change-Id: I613b4ef622d64305d436cb8379a5170b0fe1c9af Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282417 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/11039 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-23t210: lp0_resume: set CAR2PMC_CPU_ACK_WIDTH to 0Yen Lin
Like in cold boot path, need to set CAR2PMC_CPU_ACK_WIDTH to 0 in lp0 resume path. BUG=chrome-os-partner:40741 BRANCH=None TEST=Tested on Smaug; able to suspend/resume Change-Id: Iffd7fa4d0266e2ec482ec17e5203ceff8afe748f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 052b649b1e6a4e34d621d710ee43aec7149ab8a8 Original-Change-Id: Icdf9879469485fb37b820b30c9663eda528ac013 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286600 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/11037 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-23t210: change memlayout.ldYen Lin
MBIST workaround needs more space in bootblock. bootblock += 4KB; romstage -= 4KB BUG=None BRANCH=None TEST=tested on Smaug, still boot to kernel Change-Id: I8338d0a134185a425af36e302dcf0ed1520b7e21 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 388523bf4fa25ff3ecf9607ff36ce7c6109485ed Original-Change-Id: Ib08f2ff438f9d96a19b44af1b3e13260966f98f1 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287286 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/11038 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-21t210: Add tegra_lp0_resume codeYen Lin
BUG=chrome-os-partner:40741 BRANCH=None TEST=tested on Smaug; able to suspend/resume Change-Id: I3e796bee4b1bedfd4cce0a37549108d5271658a6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 207ca26cb2c157c0dcf476c4d4973b4d4ec67cc7 Original-Change-Id: I8565d4cf1632d6d3023aa55b2bff824a092f2c3b Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277025 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/11018 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-07-21t210: Correct device MMIO rangeJimmy Zhang
Address region from 0x0 to 0x00ffffff is used for IROM_LOVEC and can not be accessed by Bootloader. Issue found in CL: 283104 is captured by this patch. BUG=None BRANCH=None TEST=Compiles successfully and reboot test does not crash in firmware Here are memory mapping table before and after this CL for evt2 board: Before: Mapping address range [0000000000000000:0000000040000000) as cacheable | read-write | secure | device Mapping address range [0000000040000000:0000000040040000) as cacheable | read-write | non-secure | normal Mapping address range [0000000040040000:0000000080000000) as cacheable | read-write | secure | device Mapping address range [0000000080000000:00000000feb00000) as cacheable | read-write | non-secure | normal Mapping address range [00000000fec00000:0000000100000000) as cacheable | read-write | secure | normal Mapping address range [0000000100000000:0000000140000000) as cacheable | read-write | non-secure | normal After: Mapping address range [0000000001000000:0000000040000000) as cacheable | read-write | secure | device Mapping address range [0000000040000000:0000000040040000) as cacheable | read-write | non-secure | normal Mapping address range [0000000040040000:0000000080000000) as cacheable | read-write | secure | device Mapping address range [0000000080000000:00000000feb00000) as cacheable | read-write | non-secure | normal Mapping address range [00000000fec00000:0000000100000000) as cacheable | read-write | secure | normal Mapping address range [0000000100000000:0000000140000000) as cacheable | read-write | non-secure | normal Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: I07d38a8994c37bf945a68fb95a156c13f435ded2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3eee44944c2c83cc3530bfac0d71b86d3265f5b2 Original-Change-Id: I2b827064807ed715625af627db1826c3a01121ec Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285260 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11015 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-16t210: new sdram_lp0_save_params() functionYen Lin
New sdram_lp0_save_params() function for T210. Due to its size, move the function from romstage to ramstage. BUG=chrome-os-partner:40741 BRANCH=None TEST=Build ok on Smaug; and check scratch registers Change-Id: I420ac4c15262f2c6307bcd84beb6c5da0310c7c0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 38860895938c40062a9f860f75e31a539f15992b Original-Change-Id: Iaa478969458946faedd295578fe7d72b5a32e701 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277022 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10952 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16t210: correct odmdata location in bctYen Lin
Correct the odmdata location in bct for T210. BUG=chrome-os-partner:40741 BRANCH=None TEST=build ok on Smaug Change-Id: I2258556ec5cf5d25782e60e084f3d5657b441c86 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 288a5d71c35fbea1812ad0c91f2c6c5f5a022363 Original-Change-Id: I0efb033442c2aafc7f44898c16b3e91946e092d5 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277023 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10953 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16t210: Reorganize memlayout.ldFurquan Shaikh
Take up space from PRERAM_CBMEM_CACHE and increase verstage and romstage sizes. BUG=chrome-os-partner:36613 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: I7fdd6c08f3ca1998a6220edd80a570816ec65ab5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cce3d7baa7446e227d3da41341d9e273d4195299 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285344 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Change-Id: I6d97a60b26fbbb29a875285c46724fb43b5fe5ab Original-Reviewed-on: https://chromium-review.googlesource.com/285533 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/10948 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16t210: SPI driver cleanupFurquan Shaikh
1. Get rid of spi_delay - Instead have a tight loop to check for the spi status 2. The first check for SPI operation complete i.e. FIFOs have been processed is the SPI_STATUS_RDY bit. Thus, tegra_spi_wait should check for this bit before reading BLOCK_COUNT or any other fifo count field. 3. Flush both TX and RX FIFOs for SEND and RECV operations for PIO and DMA. 4. No need to check for rx_fifo_count == spi_byte_count to determine pio_finish operation. RDY bit should be sufficient to ensure that the SPI operation is complete. Added assert to ensure we never hit the case of RDY bit being set, yet rx_fifo_count != spi_byte_count for PIO. BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and reboot test runs successfully for 10K+ iterations. Change-Id: I1adb9672c1503b562309a8bc6c22fe7d2271768e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: de1515605e17e0c6b81874f9f3c49fd0c1b92756 Original-Change-Id: I5853d0df1bfd6020a17e478040bc4c1834563fe4 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285141 Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10947 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16t210: Correct dma_busy functionFurquan Shaikh
In case of continuous mode, use STA_ACTIVITY bit to determine if DMA operation is complete. However, in case of ONCE mode, use STA_BSY bit to determine if DMA operation on the channel is complete. BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and reboot test runs fine for 10K+ iterations Change-Id: If98f195481b18c402bd9cac353080c317e0e1168 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 927026db6fd910dac32dc218f28efcbc7b788b4e Original-Change-Id: Ib66bedfb413f948728a4f9cffce9d9c3feb0bfda Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285140 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10946 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16t210: Add PINMUX macros for drive strengthFurquan Shaikh
BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: Ic606838639d33242b227fece9cbb019d8f3b3729 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 805831489ad80e4ed335ece458f81238af704876 Original-Change-Id: I54a730c3b97c3603a5b1981089913c58af2a42db Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284958 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10944 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-13tegra124/tegra210: Include stages.h in bootblock.cStefan Reinauer
Needed for the main() prototype Change-Id: I921a77d8b131b751291d3a279b23ee18b13eca8d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10862 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-13tegra210: Fix coding style in clock.cStefan Reinauer
Change-Id: I1a8ce0b8ec291a5ddd8fdefcda24842e2a3c692d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10861 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-13t210: Apply A57 hardware issue workaround during cpu startupFurquan Shaikh
Define custom stage_entry to apply workaround for A57 hardware issue for power on reset. It is observed that BTB contains stale data after power on reset. This could lead to unexpected branching and crashes at random intervals during the boot flow. Thus, invalidate the BTB immediately after power on reset. BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and reboot test does not crash in firmware for 10K iterations. Change-Id: Ifbc9667bc5556112374f35733192b67b64a345d2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc7c2fec3c6b29e291235669ba9f22ff611064a7 Original-Change-Id: I1f5714074afdfee64b88cea8a394936ca848634b Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284869 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10899 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-13t210: Add TZDRAM_BASE param to BL31_MAKEARGSFurquan Shaikh
1. Make TTB_SIZE Kconfig option 2. Add Kconfig option for maximum secure component size 3. Add check in Makefile to ensure that Trustzone area is big enough to hold TTB and secure components 4. Calculate TZDRAM_BASE depending upon TTB_SIZE and TZ_CARVEOUT_SIZE BUG=chrome-os-partner:42319 BRANCH=None Change-Id: I9ceb46ceedc931826657e5a0f6fc2b1886526bf8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a425d4978a467b157ea5d71e600242ebf427b5bb Original-Change-Id: I152a38830773d85aafab49c92cef945b7c4eb62c Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284074 Original-Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10878 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09t210: set CAR2PMC_CPU_ACK_WIDTH to 0Yen Lin
HW team has suggested to set CAR2PMC_CPU_ACK_WIDTH to 0. BUG=None BRANCH=None TEST=Tested on Smaug; still boot to kernel Change-Id: I4d13a4048b73455b16da7a40c408c912fa97e4e7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8891a79e72af26d986af9e415149d4ca0aa6fedd Original-Change-Id: I850a6756d7743993802fb85aad403e4cbef7a661 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282416 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10841 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09t210: i2c6: enable SOR_SAFE and DPAUX1 clocks for i2c6 to workYen Lin
I2C6 controller needs SOR_SAFE and DPAUX1 clocks to work. These 2 clocks are mistakenly enabled by MBIST. MBIST fix will be submitted next, which will disable these 2 clocks as initial states. Enable these 2 clocks now so I2C6 will continue to work after MBIST fix. BUG=None BRANCH=None TEST=Tested on Smaug, make sure that panel shows display (I2C6 is used to turn on backlight) Change-Id: Id47453e784d53fd6831e8d19a8d57c04c4e1f82f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 83e935f100be85e1e831a3f9f16962304f7cd7d6 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Change-Id: If312881c94570066bdc54f0f5c48226e862bddc6 Original-Reviewed-on: https://chromium-review.googlesource.com/282415 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10840 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-08memlayout: Add timestamp regions for t210 and cygnusStefan Reinauer
This is needed to make those SOCs compile with timestamps enabled. Change-Id: Iac20cb9911e1c76a18c8530385c9d7b8b46399e5 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10833 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-07-07T210: UTMIP: Correct UTMIP PLL programming as per Mark KuoTom Warren
BUG=chrome-os-partner:39603 BRANCH=none TEST=Built OK for Smaug. Change-Id: Iba170d8ad6f1dff111421fd61f71da19de57efaa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1bf1c1442dacf45bac5d55b05ada99a2c96f2e45 Original-Change-Id: Iecf04691a637b56e2f2287ab7d4d0cdda0382421 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282720 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-by: Mark Kuo <mkuo@nvidia.com> Reviewed-on: http://review.coreboot.org/10814 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06t210: MTC cleanupFurquan Shaikh
1. Correct MTC weak function definitions. 2. Correct MTC message in case no training data is present. BUG=None BRANCH=None TEST=Compiles successfully and boots to kernel prompt on smaug. Change-Id: Iba3c994982da947af3fbd2d7e9a06dff7947f2b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ce9a4cd7d824acd0da5615b33319869f6cf1cd56 Original-Change-Id: I037439246709c8ec0ec7f12ea109cbe0ae1073ae Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/278027 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10780 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-07-04Kconfig: Fix references to obsolete symbolsMartin Roth
These are all Kconfig symbols that have been removed or renamed. USE_PRINTK_IN_CAR was removed in commit 8c4f31b3 Drop the USE_PRINTK_IN_CAR option. It's a bogus decision... DYNAMIC_CBMEM was removed in commit e2b0affd Remove Kconfig variable that has no effect MAINBOARD_HAS_BOOTBLOCK_INIT was removed in commit 342535cc Remove Kconfig variable that has no effect CACHE_ROM was removed in commit 4337020b Remove CACHE_ROM. SMM_MODULES was removed in commit 44cbe10f smm: Merge configs SMM_MODULES and SMM_TSEG INCLUDE_MICROCODE_IN_BUILD was removed in commit eb73a218 soc/fsp_baytrail: Fix use of microcode-related Kconfig variables CAR_MIGRATION was removed in commit cbf5bdfe CBMEM: Always select CAR_MIGRATION REQUIRES_BLOB was removed in commit 70c85eab build system: Retire REQUIRES_BLOB CPU_MICROCODE_IN_CBFS was renamed to SUPPORT_CPU_UCODE_IN_CBFS in commit 66e0c4c8 - cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS CONSOLE_SERIAL_UART was renamed to CONSOLE_SERIAL in commit afa7b13b uart: Redefine Kconfig options CONSOLE_SERIAL8250MEM was renamed to DRIVERS_UART_8250MEM in commit afa7b13b - uart: Redefine Kconfig options Change-Id: I8952ca8c53ac2e6cec5f9c77d2f413f086bfab9d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10766 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-03Kconfig whitespace cleanup: Change leading spaces to tabsMartin Roth
Change-Id: Icab6bd9f55f086da7b51ae463f34e29366d50e1a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10764 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-01nvidia/tegra210: Drop unused Kconfig symbolPatrick Georgi
The deleted symbols aren't used anywhere in the coreboot tree and come from the downstream chromeos-2013.04 branch. Change-Id: I0ebc2936dff400cf8fe68794c86ac583aba2a14b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10752 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-01tegra210: Include correct include filesStefan Reinauer
Some include files were unnecessary, and program_loading.h was missing. Change-Id: Ief3d970af5fbbb6b79da06ba3ea1d8613bfc314f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10749 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-06-30nvidia/tegra210: reserve more room for the romstage in vboot buildsPatrick Georgi
Change-Id: I11c2e270179c54af8687435ff662a509ac714505 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10733 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-06-30nvidia/tegra210: add new SoCPatrick Georgi
This includes Chrome OS downstream up to Change-Id: Ic89ed54c. Change-Id: I81853434600390d643160fe57554495b2bfe60ab Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10633 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-22 02:55:12 +0000