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2015-03-07t132: add Kconfig option for MTS microcode directoryAaron Durbin
In order to make sharing of the location of MTS microcode easier provide a Kconfig option that is the path to the files. BUG=chrome-os-partner:30569 BRANCH=None TEST=Built rush coreboot. Original-Change-Id: I36775d0018fc8591d5e77c2943e28a51381713f5 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207839 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 6f1de0e7fd312c1d6798e65d4b43d586f0994337) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I660cb9d8bd13c765c89b54b0807b5b3ee836e807 Reviewed-on: http://review.coreboot.org/8614 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-07tegra132: add preboot MTS to bct generationAaron Durbin
The preboot MTS microcode needs to be supplied within the bct so the BootROM can load it. The size of the bootblock space in SPI needed to be extended to accomodate the extra length. BUG=chrome-os-partner:29059 BUG=chrome-os-partner:29060 BRANCH=None TEST=Built rush with updated cbootimage with t132 support. Original-Change-Id: Iafc1837cd81cc1165a9be5da6ec7425cec2e2ffc Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/204940 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 22e054496465c74fc12afd865d14b87c5858d889) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5e46c408a7215ecc789b0a0f35070ef9036a7d11 Reviewed-on: http://review.coreboot.org/8466 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-05tegra132: add support for TZ carve-outAaron Durbin
The TrustZone carve-out needs to be taken into account when determining the memory layout. However, things are complicated by the fact that TZ carve-out registers are not accessible by the AVP. BUG=chrome-os-partner:30572 BRANCH=None TEST=Built and booted to end of ramstage. Noted that denver cores can read TZ registers while AVP doesn't bother. Original-Change-Id: I2d2d27e33a334bf639af52260b99d8363906c646 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207835 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> (cherry picked from commit a4d792f4ed6a0c39eab09d90f4454d3d5dc3db26) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8fbef03d5ac42d300e1e41aeba9b86c929e01494 Reviewed-on: http://review.coreboot.org/8593 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-03-05t132: handle carve-outs for addressable memoryAaron Durbin
The carve-out regions need to be taken into account when calculating addressable memory because those regions aren't accessible from the main cpu. The additional exposed functions are to accommodate adding resources during ramstage resource reading. The TZ (trust zone) region is empty for now until more documentation is provided on determining its location. BUG=None TEST=Built and booted through attempting payload loading. MTS carve-out is taken into account programmatically. Original-Change-Id: I3301b2a12680ad79047198ada41f32eb1b7fa68b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207585 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 15b9c74dd1ef5bfb1fd7c6dab50624f815658e14) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I46d54dbbb8e102fc70ab34bc4bbd2361ef1ea504 Reviewed-on: http://review.coreboot.org/8591 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-05t132: Enable cbmem console supportAaron Durbin
Enabled CBMEM support for t132 platforms. Some of the existing code is moved around to avoid dependencies in the other stages that need it. BUG=None BRANCH=None TEST=Built and booted a rush with cbmem support. Original-Change-Id: I78a31b58ab9cc01a7b5d1fffdb6c8ae0c446c7dd Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207163 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit f552197dbda06c754b5664c3bed4ed361154229a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8fa2919714b467cc976e5bb5c4716e5b7979694b Reviewed-on: http://review.coreboot.org/8589 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-05t132: bring up 64-bit denver coreAaron Durbin
The startup sequence for cpu0 is implemented while also providing a trampoline for transitioning to 64-bit mode because the denver cores on t132 come out of cold reset in 32-bit mode. Mainboard callbacks are provided for providing the board-specific bits of the bringup sequence. BUG=chrome-os-partner:29923 BRANCH=None TEST=Built and booted through ramstage. Original-Change-Id: I50755fb6b06db994af8667969d8493f214a70aae Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207263 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 17f09bf4bdb43986c19067ca8fd65d4c5365a7c6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I14d99c24dd6e29a4584c8c548c4b26c92b6ade97 Reviewed-on: http://review.coreboot.org/8586 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04coreboot t132: Stack init re-workFurquan Shaikh
1) In order to avoid stack from overflowing during ramstage decompression, initialize stack right at the beginning of romstage. 2) Declare different Kconfig options for stack at each stage. 3) Provide a macro that does stack seeding if required and calls appropriate function. BUG=None BRANCH=None TEST=Compiles and runs successfully on rush. Original-Change-Id: I55d6ce59ea91affba3e86d68406921497c83fb52 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206880 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 5e32d73803a2a9d222fcc4ca5f58efd3abe95d34) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib833a1badb170a33cbf20d232019425b59db60cd Reviewed-on: http://review.coreboot.org/8583 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04t132: kick off core complex after loading MTS microcodeAaron Durbin
Once the MTS microcode is loaded the core complex can be directed to decode the MTS and start running. The cores, however, won't start executing until instructed to do so. BUG=chrome-os-partner:29222 BRANCH=None TEST=Built, booted, ran. Noted it took about 920ms for the core complex to decode and handshake back. Original-Change-Id: I0a9ed53e596eb65801461b2769d133710a92a48a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/206075 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> (cherry picked from commit 6edb6e21a69d84ba5b23137e9e390954159e7887) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I179e561bb3a34b206620eecde6781a1c05a3744e Reviewed-on: http://review.coreboot.org/8581 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-04t132: load MTS microcodeAaron Durbin
The armv8 cores need to have microcode loaded before they can be taken out of reset. Locate and load the MTS microcode at the fixed address of 0x82000000. The ccplex, once enabled, will decode and transfer the microcode to the carveout region. BUG=chrome-os-partner:29922 BRANCH=None TEST=Built and ran. Confirmed dump of MTS region after loading code. Original-Change-Id: Ie5ab72e5363cbdb251d169356f718020d375fce6 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/206290 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 6726d8862c08b155b9218aa5e2e39428a105089e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I425c2e2fd1eaec49d81bef1ff4bf4f36da9296df Reviewed-on: http://review.coreboot.org/8580 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-04t132: Replace fallback with CONFIG_CBFS_PREFIXMarc Jones
Use the Kconfig value to load the name of the stage instead of the hard-coded fallback stage. (cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1ac707efe38e29f109dbbe206de74fbfe7cb7b0b Reviewed-on: http://review.coreboot.org/8576 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04t132: Add shared romstageAaron Durbin
There's no reason to duplicate code in the mainboards. Therefore, drive the flow of romstage boot in the SoC. This allows for easier scaling with multiple devices. BUG=None BRANCH=None TEST=Built and booted to same place as before. Original-Change-Id: I0d4df84034b19353daad0da1f722b820596c4f55 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205992 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie74f0eb1c983aff92d3cbafb7fe7d9d7cb65ae19 Reviewed-on: http://review.coreboot.org/8575 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04coreboot rush: Add dram init codeFurquan Shaikh
Add support for initializing dram within romstage. This is an essential before we move to the armv8 core. BUG=None BRANCH=None TEST=Compiles succesfully for rush. Tried writing to and reading value from the base of sdram and it worked fine. Also tested with primitive_memtest CL: https://chromium-review.googlesource.com/#/c/186309/5 Original-Change-Id: I67ec04c766e249c9727b0cf2ba216522c862c2f5 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205823 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 33c468b16e7ccd8cf9266d6a9ca30c02da104821) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4baface2c109ca74f85f43a25508677c46c64159 Reviewed-on: http://review.coreboot.org/8574 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04coreboot rush: Add support for basic romstageFurquan Shaikh
Add basic romstage support for rush. Since, dram init needs to be done before we can jump to armv8 core, romstage will run on armv4 core as well. Thus, correcting the compiler selection options. BUG=None BRANCH=None TEST=Compiles successfully for rush. Prints romstage banner and initial printk Original-Change-Id: Ie3cd290e56a712b07c1503dab199e4e34cec04d2 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205763 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit d20b4e66209e902f54a07a17d5ce741f0a0b3a7b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic6b7ef4a2ea01c95d0c7f040bbd079219cf5750a Reviewed-on: http://review.coreboot.org/8573 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-04coreboot t132: Enable loading of romstage from CBFS mediaFurquan Shaikh
Add proper Kconfig options and initialize cbfs media to enable loading of romstage BUG=None BRANCH=None TEST=Compiles successfully for rush and cbfs_load_stage returns entry pointer for romstage Original-Change-Id: If62edcdc0496d89d30003ffd7b827b77835910fd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205762 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c89c05bc86fd6c1e49fbed5e0730659b64bffc6c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I68c10171424c85605b5065a19634d3c5dd639b78 Reviewed-on: http://review.coreboot.org/8572 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04coreboot t132: Remove init pllx for nowFurquan Shaikh
We suspect that the code was stuck on init pllx (PLLX - acts as a clock source for the CPU cluster). So, remove the init call for pllx. This needs to be added later when required. Also, add a few more printks to display the progress. BUG=None BRANCH=None TEST=Compiles successfully for rush. Print messages seen on serial console. Original-Change-Id: I70e908a9ce1f3598d68bda68c0401a78834597d1 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205680 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit d557d99edb855fbf7b32231c6746c676041bf62a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iaf56f2d587708c6e9fb01d4ced2edb5931075a81 Reviewed-on: http://review.coreboot.org/8571 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04coreboot t132,rush: Add mainboard specific bootblock_initFurquan Shaikh
Pull in mainboard specific bootblock_init function from nyan into rush. Additionally, pull in all files required for proper compilation of rush after adding the bootblock_init function BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: I69c736275f66eca3ad92f97d166e91d4c2301364 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205583 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit e7aac547026717d7380f71593010e3ea34ecea51) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie26f91f8caaa06af3b195246febcdc70b9fe9795 Reviewed-on: http://review.coreboot.org/8570 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-03coreboot t132: Add clock.c to all three stages of corebootFurquan Shaikh
Enable adding of clock.c to romstage and ramstage in addition to bootblock. Code for enabling armv8 core is not included yet. clock_init added to bootblock.c BUG=None BRANCH=None TEST=Compiles successfully for rush. Original-Change-Id: I858c41a83d665da2c406707586b5e35a732177d4 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205581 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 61dbf1db72307815c4abdc218799479c334a4882) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I688e1e1373dea26557a84507a8e92d3055862801 Reviewed-on: http://review.coreboot.org/8569 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-02coreboot arm: Define function for setting cntfrq registerFurquan Shaikh
Define functions for setting cntfrq register in arm and arm64 arch. This allows SoCs to set this register independently of the architecture being used. BUG=None BRANCH=None TEST=Compiles successfully for nyan and rush Original-Change-Id: I93240419b2c012eee29a408deff34a42af943a63 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205580 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 768463fef5d630dec915aa0b95e7724d4a6f74b6) armv8: GPL license armv8 lib BUG=None BRANCH=None TEST=Compiles successfully. Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250950 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I298c3e76cb52f0876bce3dd4f54d875f62e9310a Reviewed-on: http://review.coreboot.org/8468 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-02tegra132: Enable bootblock support in tegra132 including UART supportFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: Ia9420cfec5333dd5477f04cf080bdad8a37db025 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/203143 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit a1037f203c6a07cb116eeb1632cb7200ad022cd3) This cherry-pick was modified to match the tegra124 uart.c, which uses the idx and base address calculations instead of Kconfig settings. This driver could use the 8250MEM driver when the ARM vs x86 IO calling convention is worked out. Change-Id: I6e439359b8bb541db4679ac144c519cf251ffed6 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8517 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-17tegra132: Postprocess bootblock properlyPatrick Georgi
It's not very useful to try to link a host tool into the bootblock image. Change-Id: Id3b6496c061d41184fbb516d56746855b455b0c3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/8473 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-17tegra132: Add BCT support in tegra132 socFurquan Shaikh
Builds with cbootimage. BUG=None BRANCH=None TEST=build test Original-Change-Id: I796f171031bacf17106878d4a554e8f1cbfe93f8 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/203145 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 4778ae4d08a25306407f0fd2fe47976d63463f9d) Increase the bootblock area for the larger BCT that is generated by the coreboot version of the cbootimage tool. Change-Id: I42b8208504bf4936a9fa14f820d665590f6a3754 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8413 Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-13tegra132: Fix build for verstageMarc Jones
Verstage isn't included yet, but we need to have the Kconfig option for toolchain.inc to pass. Change-Id: I7fae73cd3b77fd347398221489caf745274701eb Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8409 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-26tegra132: Add support for tegra132 socFurquan Shaikh
Add basic support for tegra132 soc. BUG=None BRANCH=None TEST=Compiles successfully for rush board using tegra132 soc Original-Change-Id: If2a3de80026e7729ac6da8484ff6c56607c52a63 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197398 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 4746bff6e9f4b20abc44d0b6fce9691aea63583c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If2a3de80026e7729ac6da8484ff6c56607c52a63 Reviewed-on: http://review.coreboot.org/8040 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-29 21:00:55 +0000