| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-02-21 | soc/*: fix uart's regwidth specification in cbtables | Patrick Georgi |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
| 2015-05-11 | nvidia/tegra132: we write tables in ramstage | Patrick Georgi |
| 2015-04-21 | arm(64): Manually clean up the mess left by write32() transition | Julius Werner |
| 2015-04-21 | arm(64): Globally replace writel(v, a) with write32(a, v) | Julius Werner |
| 2015-04-21 | arm(64): Replace write32() and friends with writel() | Julius Werner |
| 2015-04-17 | uart: pass register width in the coreboot table | Vadim Bendebury |
| 2015-04-08 | tegra132: Change all SoC headers to <soc/headername.h> system | Julius Werner |
| 2015-03-02 | tegra132: Enable bootblock support in tegra132 including UART support | Furquan Shaikh |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |