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path: root/src/soc/nvidia/tegra132/soc.c
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2015-11-07arm64: Remove cpu intialization through device-treeFurquan Shaikh
Since, SMP support is removed for ARM64, there is no need for CPU initialization to be performed via device-tree. Change-Id: I0534e6a93c7dc8659859eac926d17432d10243aa Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/11913 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-07arm64: Remove SMP supportFurquan Shaikh
As ARM Trusted Firmware is the only first class citizen for booting arm64 multi-processor in coreboot remove SMP support. If SoCs want to bring up MP then ATF needs to be ported and integrated. Change-Id: Ife24d53eed9b7a5a5d8c69a64d7a20a55a4163db Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/11909 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-07arm64: remove spin table supportAaron Durbin
As ARM Trusted Firmware is the only first class citizen for booting arm64 multi-processor in coreboot remove spintable support. If SoCs want to bring up MP then ATF needs to be ported and integrated. Change-Id: I1f38b8d8b0952eee50cc64440bfd010b1dd0bff4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11908 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-04bootmode: add display_init_required()Aaron Durbin
Some of the Chrome OS boards were directly calling vboot called in some form after contorting around #ifdef preprocessor macros. The reasoning is that Chrome OS doesn't always do display initialization during startup. It's runtime dependent. While this is a requirement that doesn't mean vboot functions should be sprinkled around in the mainboard and chipset code. Instead provide one function, display_init_required(), that provides the policy for determining display initialization action. For Chrome OS devices this function honors vboot_skip_display_init() and all other configurations default to initializing display. Change-Id: I403213e22c0e621e148773597a550addfbaf3f7e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11490 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-04-21arm(64): Globally replace writel(v, a) with write32(a, v)Julius Werner
This patch is a raw application of the following spatch to src/: @@ expression A, V; @@ - writel(V, A) + write32(A, V) @@ expression A, V; @@ - writew(V, A) + write16(A, V) @@ expression A, V; @@ - writeb(V, A) + write8(A, V) @@ expression A; @@ - readl(A) + read32(A) @@ expression A; @@ - readb(A) + read8(A) BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6 Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254864 Reviewed-on: http://review.coreboot.org/9836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21arm(64): Replace write32() and friends with writel()Julius Werner
This patch is a raw application of the following spatch to the directories src/arch/arm(64)?, src/mainboard/<arm(64)-board>, src/soc/<arm(64)-soc> and src/drivers/gic: @@ expression A, V; @@ - write32(V, A) + writel(V, A) @@ expression A, V; @@ - write16(V, A) + writew(V, A) @@ expression A, V; @@ - write8(V, A) + writeb(V, A) This replaces all uses of write{32,16,8}() with write{l,w,b}() which is currently equivalent and much more common. This is a preparatory step that will allow us to easier flip them all at once to the new write32(a,v) model. BRANCH=none BUG=chromium:451388 TEST=Compiled Cosmos, Daisy, Blaze, Pit, Ryu, Storm and Pinky. Change-Id: I16016cd77780e7cadbabe7d8aa7ab465b95b8f09 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 93f0ada19b429b4e30d67335b4e61d0f43597b24 Original-Change-Id: I1ac01c67efef4656607663253ed298ff4d0ef89d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254862 Reviewed-on: http://review.coreboot.org/9834 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-14tegra132: lock down VPRAaron Durbin
The GPU MMU won't function properly until it sees the VPR is locked down. Therefore, do the appropriate work. BUG=None BRANCH=None TEST=Built. Change-Id: I6011c75c1e6c231f2fa416e0057cb5805a88a2bb Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: ca9cc9917b98a148442468d1d1541a0408ab6c2c Original-Change-Id: I3601f419b561cee392391577ef8db66b9fbd8c1b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/242910 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/9660 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10tegra132: always bring up PLLDAaron Durbin
The kernel does not correctly function without PLLD being enabled. Additionally, PLLD can be the source for other clocks in the system. Therefore, initialize PLLD to 300MHz unconditionally at BS_DEV_INIT time in ramstage. BUG=chrome-os-partner:33825 BRANCH=None TEST=Built and booted ryu with display coming up both in dev mode as well as normal mode. Change-Id: Ib2a60bb9aafc03dc23aa932a480184d87f677c65 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c49f964b55c3c33d03b95363277b262b679e740 Original-Change-Id: Ic5905e25051a042cea5010b8c6d61b1fb89a0a81 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230774 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Sean Paul <seanpaul@chromium.org> Reviewed-on: http://review.coreboot.org/9525 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Pass panel spec to lib_sysinfoJimmy Zhang
panel spec such as resoultion, bits per pixel are needed to pass to depthcharge/payload for displaying bitmap onto panel. Enable display code only if mainboard selects MAINBOARD_DO_NATIVE_VGA_INIT. Otherwise build breaks for boards that do not support display init yet. BRANCH=none BUG=chrome-os-partner:31936 TEST=Compiles for both rush and ryu. Display comes up for ryu in both normal and dev mode. Change-Id: I81b4d289699e7b0c2758ea1a009cbabaf8a2ce28 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b9b42486f203d332f6068ccd6f4a1a982d327a6b Original-Change-Id: I5c8fde17d57e953582a1c1dc814be4c08e349847 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Commit-Id: ce2883b21d3fbfd54eac3a355fb34ec70e9f31ad Original-Change-Id: Ib4a3c32f1ebf5c6ed71c96a24893dcdee7488b16 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/9519 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Add dsi driverJimmy Zhang
Add dsi and related dc, panel configuration functions. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: I8440b6dfccc7ed7cd280a0df3a98cbc7b7d66070 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fb08563f67daf9a616b60609c4523b823d34f8e3 Original-Change-Id: I87b8047e23ebe114af353fcce5924a46621d16d2 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/227202 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9517 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10ryu: Add display_start apiJimmy Zhang
Enable display only developer and recovery mode. Will add in the actual display supporting functions in coming patches. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: I0d312fd132dc310813432f4d8a28ad16c9bb36aa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dd1bd56e83532c77d675f72b301b413cbcf3f489 Original-Change-Id: Idfa24d23c81baaedb944d2b9835255edad4e422b Original-Reviewed-on: https://chromium-review.googlesource.com/226904 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-on: http://review.coreboot.org/9421 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-04-09soc: Use DEVICE_NOOP macro formalism over static stub funcEdward O'Callaghan
Change-Id: Ice7e27230010ffc48948f952394e849533f94085 Signed-off-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-on: http://review.coreboot.org/8989 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-08tegra132: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns tegra132 to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Rush_Ryu. Change-Id: I5cdf4008a65db84f15c937ef53aab5e4d3ef24c4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d5c5c63d7b6399d3eb8a211b15d47829fe93a591 Original-Change-Id: Ifafd4d42d4fb04a1c37e8a5f23877c2b550cf44c Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224505 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9369 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04tegra132: remove framebuffer reservationAaron Durbin
There's no need to reserve the framebuffer within coreboot. If the payloads need a framebuffer they can allocate one themselves. BUG=chrome-os-partner:31355 BRANCH=None TEST=Built and booted on ryu. Original-Change-Id: I8d8b159e7fdd877e392193c5474a7518e9b3ad21 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221726 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 1ff8da9fed414fceeda3f94b296312f4531b320f) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I4e7c0417824f2be9836b1bc2bb99322c78490ca2 Reviewed-on: http://review.coreboot.org/9256 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: remove private spin table implementationAaron Durbin
Support the generic spin table code instead of having the one-off implementation. BUG=chrome-os-partner:32082 BRANCH=None TEST=Built and booted to kernel w/ smp. Both w/ and w/o secure monitor. Change-Id: I8557298d1a159b70818cbd8864470ff0d8a46fb1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8d89af95a7919f0b8acc92d82f3abda965514ccf Original-Change-Id: I24d56a30fdabd7a35ebc28dcc355c675de823a51 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218655 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9085 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: use generic GIC driverAaron Durbin
As the arm64 boot flow handles initializing the GIC by way of the driver provide the SoC support for that driver and use it. BUG=chrome-os-partner:31945 BRANCH=None TEST=Built and booted kernel on ryu. Change-Id: I6ba20339be8fc823e241b4299ad6c3deb82799fa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 582cd9cef58e27aef2ce9c9b4fba4a78365bec6e Original-Change-Id: I34efaf28369377f353b4c51d20d19c9433befda4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217514 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9077 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-03-28tegra132: update MTS version formattingAaron Durbin
Nvidia tracks their MTS versions using decimals. Update the format so there isn't an extra step in communicating versions while debugging things. BUG=chrome-os-partner:31864 BRANCH=None TEST=Booted and confirmed decimal print out. Change-Id: I8d8b8a6e9b80548509dd8a30abb17c9970afdead Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b7deb04a1deed41e1a54713320a29f6731401b35 Original-Change-Id: Ia7d0bc49318a4b4c969ee37e762e084ec65de543 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217260 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9061 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: support arm64 SMP bringupAaron Durbin
Use the formal devicetree way for bringing up each of the cpus. This includes providing a cpu_driver as well as calling arch_initialize_cpus() with the proper operations to start the cores. BUG=chrome-os-partner:31761 BRANCH=None TEST=Booted SMP on ryu. Change-Id: I276fe08916bc0c46c8f4dd30e47c7d9b135e2bbd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 038daec1b74f4c414ab7ad153d34e48d4644183a Original-Change-Id: I13d8bfd645abf66f270d56d48eff4331c4ea1200 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216926 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9043 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: add spin table supportAaron Durbin
Until PSCI is functional the other core still needs to be brought up in the kernel. The kernel boots these cpus with the spin table which is just an address in memory to monitor a jump location. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and brought up secondary core in linux. Change-Id: Iaa69110f6a647d8fd4149119d97db4fc45d7da00 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 01ca36685852bc5dd85fd4015c8a1e600e23e7ca Original-Change-Id: Ieaf19cd70aff3e6c8de932e04b1b5aba71822a97 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214777 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9021 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: add option to bring up and init secondary cpuAaron Durbin
Optionally bring up secondary cpu according to devicetree. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and enabled bringing up second core on ryu. Change-Id: I5ede8b2f1b30a6170520cc11c18e263793cea301 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d7da2dcce9be653a3c551c33bbefb3810a6949e9 Original-Change-Id: Ia3f2c10dab2bbfd65ba883451bf4eafc26f2e7cf Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214776 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9020 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: initialize GICAaron Durbin
This provides are barebones initialization for tegra132 GIC on CPU0. It routes all interrupts to CPU0, moves them all into group 1, and attempts to allow non-secure access for all registers (doesn't appear to be implemented, though). BUG=chrome-os-partner:31449 BRANCH=None TEST=Built and booted past smp init in the kernel. Timers appear to be flowing now since jiffies are updated. Change-Id: Id45c13cc23e50feed3d88da13420c9eb694498a0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 81bad0a53083baa7af0f1fd5f82fef0538ee62df Original-Change-Id: I69dd9ae53f259e876a9bc4b9d7f65330150d2990 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212795 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8995 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: move page tables to trustzone regionAaron Durbin
In order to access secure device register space the cpu needs to have the page tables marked as secure memory. In addition the page tables need to live within secure memory otherwise the accesses default to non-secure. Therefore move the page tables to the trustzone region. Remove the TTB_* config options as well as removing the TTB reservations from coreboot's resource list. BUG=chrome-os-partner:31355 BUG=chrome-os-partner:31356 BRANCH=None CQ-DEPEND=CL:213140 TEST=Built and booted into kernel. Change-Id: I1fc8dda932c36935f8523792bc1147f6b0743d11 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1522a83bb57e33749843d5b3ea5545ded97a3953 Original-Change-Id: Ia4b9d07ef35500726ec5b289e059208b9f46d025 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213141 Reviewed-on: http://review.coreboot.org/8994 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: Initialize CNTFRQFurquan Shaikh
BUG=chrome-os-partner:31356 BRANCH=None TEST=Kernel boots with the changes required in depthcharge Change-Id: I061305e0ab8f6145c0dc74b2ff958a667ff7276a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ff2fc86c1c6e6b592fa3faffd360a3a8c6351a9 Original-Change-Id: If1c5850607174ab0f485ef41d47016056d9832cd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/212730 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8941 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25tegra132: output chip information and MTS versionAaron Durbin
It's helpful to be able to track this information. Therefore dump it in to the console log. BRANCH=None BUG=chrome-os-partner:31126 TEST=Built and ran on rush. Revision information is put out on the console. Change-Id: I22e7d222259c1179b90edda6d7807559357f6725 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 18d318331b696a6a32e0a45b8f903eb740896b02 Original-Change-Id: Ic95382126a6b8929d0998d1c9adfcbd10e90663f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210903 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8905 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17t132: Add TTB_BUFFER to resource reservedFurquan Shaikh
TTB_BUFFER holds the MMU tables. Thus, this memory needs to be preserved while performing a wipe in depthcharge. Hence, marking it as reserved BUG=None BRANCH=None TEST=Compiles successfully and boots upto depthcharge. Error wiping memory tables is fixed. Original-Change-Id: Idd5cd0235d50f7b9617df2cead3bf71012e3b630 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210000 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 670e21ed11f985ca6cfef4f051c71b3c06f9c6ff) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ifcbdd4fdaad0bd4bfe384698b13cc5013317345e Reviewed-on: http://review.coreboot.org/8681 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-13tegra132: Add code to setup chip operations and mem resources.Tom Warren
With this memory resource, the payload loading code should be able to create a bounce buffer and load the payload successfully. Adapted from tegra124 soc.c BUG=None BRANCH=None TEST=Built and booted to ramstage on rush. Original-Change-Id: I2e336ce93c1b0236104e63d3785f0e3d7d76bb01 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208121 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 20765da0b15ee8c35a5bbfe532331fc6b1cef502) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I267ced473ad0773b52f889dfa83c65562444c01f Reviewed-on: http://review.coreboot.org/8644 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 18:28:13 +0000