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This patch removes the old arm64/stage_entry.S code that was too
specific to the Tegra SoC boot flow, and replaces it with code that
hides the peculiarities of switching to a different CPU/arch in ramstage
in the Tegra SoC directories.
BRANCH=None
BUG=None
TEST=Built Ryu and Smaug. !!!UNTESTED!!!
Change-Id: Ib3a0448b30ac9c7132581464573efd5e86e03698
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12078
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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As ARM Trusted Firmware is the only first class citizen for
booting arm64 multi-processor in coreboot remove SMP
support. If SoCs want to bring up MP then ATF needs to be
ported and integrated.
Change-Id: Ife24d53eed9b7a5a5d8c69a64d7a20a55a4163db
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/11909
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
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It's been decided to only support ARM Trusted Firmware for
any EL3 monitor. That means any SoC that requires PSCI
needs to add its support for ATF otherwise multi-processor
bring up won't work.
Change-Id: Ic931dbf5eff8765f4964374910123a197148f0ff
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11897
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
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For vboot1 there was an rmodule that was loaded and ran to
do the firmware verification. That's no longer used so remove
the last vestiges of VBOOT_STUB.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built glados.
Change-Id: I6b41544874bef4d84d0f548640114285cad3474e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11817
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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I missed these Makefile.inc changes. As verstage.c was removed
remove the references within the Makefile.incs.
Change-Id: I5d38c0a87d057622a3706bf3bde1142944c3b17c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11759
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Currently coreboot expects the loader to clear the bss section
for all stages. i.e. stages don't clear their own bss. On ARM
SoCs the BootROM would be responsible for this. To do that
one needs to include the bss section data (all zeros) in the
bootblock.bin file. This was previously being attempted by
keeping the .bss info in the .data section because objcopy
happened zero out non-file allocated data section data.
Instead go back to linking bootblock with the bss section
but mark the bss section as loadable allocatable data. That
way it will be included in the binary properly when objcopy
-O binary is emplyed. Also do the same for the data section
in the case of no non-zero object values are in the data
section.
Without this change the trick of including .bss in .data
was not working when there wasn't a non-zero value object
in the data section.
BUG=None
BRANCH=None
TEST=Built emulation/qemu-armv7 and noted bootblock.bin contains
the cleared bss.
Change-Id: I94bd404c2c4a8b9332393e6224e98940a9cad4a2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11680
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The boot_device is a region_device that represents the
device from which coreboot retrieves and boots its stages.
The existing cbfs implementations use the boot_device as
the intermediary for accessing the CBFS region. Also,
there's currently only support for a read-only view of
the boot_device. i.e. one cannot write to the boot_device
using this view. However, a writable boot_device could
be added in the future.
Change-Id: Ic0da796ab161b8025c90631be3423ba6473ad31c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10216
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Rename Kconfig options for secmon and spintable to be prefixed with
ARM64_ instead of ARCH_, which seems to be the standard throughout the
rest of coreboot (e.g. ARM_LPAE or X86_BOOTBLOCK_SIMPLE). I think this
provides a clearer separation between generic options that are selected
by the architecture (e.g. a hypothetical ARCH_HAS_FEATURE_X similar to
some of the MAINBOARD_HAS_... we have) and options that only make sense
in the context of a single architecture.
Change-Id: I38c2efab833f252adbb7b61ef0af60ab25b768b0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e
Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/270783
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10242
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Remove the secmon Kconfig guard from Makefiles that add to the secmon
class since they are redundant (the class is simply not used when
compiling without secmon) to improve readability/ease-of-use.
[pg: taken out of the patch linked below]
Change-Id: I2f0ad8a923ca32fcade748ac8ee50c23cf9bafb9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e
Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/270783
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10241
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This change switches all SOC vendors and southbridges
to be autoincluded by Makefile.inc, rather than having to be
mentioned explicitly in soc/Makefile.inc or in
soc/<vendor>/Makefile.inc.
This means, vendor and SOC directories are now "drop
in", e.g. be placed in the coreboot directory hierarchy
without having to modify any higher level coreboot files.
The long term plan is to enable out of tree components to be
built with a given coreboot version (given that the API did not
change).
Change-Id: Iede26fe184b09c53cec23a545d04953701cbc41d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9799
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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BUG=None
BRANCH=None
TEST=Compiles successfully for ryu.
Change-Id: Iaff771cdd1c8b6a7447e1e86aa35ea3ed40b17ad
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2856d3d4f4ab4e56259d36769d9cbb0ec9642951
Original-Change-Id: I702d7c6fa70b1af02c16b874f9de22c6b04a9100
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/265624
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9927
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Some upstreaming patches missed that, so follow up.
Change-Id: I28665c97ac777d8b0b0f909e64b32681ed2b98f7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9771
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Add dp/sor supporting functions to enable dp panel.
BUG=chrome-os-partner:34336
BRANCH=none
TEST=build rush and ryu
Change-Id: I1cc5a95ef5e3ea7cc701c1cb124a7eb5a5dbd872
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 795a7cddd36bd783cfdd6f1d3f7092bf48ebd8e7
Original-Change-Id: I336336dbbc5a772eec19ba96db8e7b50f6ea1497
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/238945
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9616
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Select DO_SOR_INIT to enable dp display api
BUG=chrome-os-partner:34336
BRANCH=none
TEST=build rush
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Change-Id: Iddf19195722856865a7c06ce96492012ab729184
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 31492f51c030aeb7a3ac792a02665642ec999405
Original-Change-Id: I4daca43239235ca6d233c4457096d3b98fcaf65c
Original-Reviewed-on: https://chromium-review.googlesource.com/234274
Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-on: http://review.coreboot.org/9586
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Enable display supporting functions by select DO_DSI_INIT
BUG=chrome-os-partner:34336
BRANCH=none
TEST=build ryu and rush
Change-Id: Ie0e03506702ddab03d7f3fd2528c67c02126c7be
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 7133dfcd1afa221be92c6398221cf210d9eddf17
Original-Change-Id: I3a9f93107333ebf83ff235eb1b1e02fc747df3c6
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/234272
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9585
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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dc supporting functions can be used for other than dsi display
interfaces. This change is preparing for supporting sor display
interface.
BUG=chrome-os-partner:34336
BRANCH=none
TEST=build ryu and test dev/rec mode, also build rush ok
Change-Id: I8a310e188fae70d7726c4360894b392c4546e105
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: a7ab7225e3419a0fd93894dbb9a959390f29945b
Original-Change-Id: Id14cbd89457cb91c23526927a432f4eb7cc6291b
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/234270
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9583
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The CPU on/off functions are the method for the Kernel to support CPU
hot-plug function in PSCI. To support this, we still need flow controller
support to capture the WFI from the CPU and inform PMC to power gate the
CPU core. On the other path, we turn on the CPU by toggling the PMC and
use flow controller to let go when the power is steady.
BUG=chrome-os-partner:32136
BRANCH=None
TEST=built the kernel with PSCI enabled,
check both of the CPUs are coming up,
test the CPU hot-plug is working on Ryu
Change-Id: If2c529b6719c5747d5aea95fb5049b2d7353ff17
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0f078e89daad1c4d8b342a395f36b3e922af66f5
Original-Change-Id: Ie49940adb2966dcc9967d2fcc9b1e0dcd6d98743
Original-Signed-off-by: Joseph Lo <josephl@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/231267
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9542
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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In order to start CPUs while in secmon/psci one needs to
set up the proper SoC state. Therefore, refactor the current
CPU startup API to allow for this by adding cpu_prepare_startup()
and start_cpu_silent().
BUG=chrome-os-partner:32136
BRANCH=None
TEST=Built and booted kernel.
Change-Id: I1424500f6c9398f7d44350949c25bb3d4832cec7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 70f9cf67085b345b529b41dd6554e37d38a5b350
Original-Change-Id: I842a391d3e27ddbfcdef1a2d60e3c66e60f99c77
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/231936
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9531
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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panel spec such as resoultion, bits per pixel are
needed to pass to depthcharge/payload for displaying
bitmap onto panel.
Enable display code only if mainboard selects
MAINBOARD_DO_NATIVE_VGA_INIT. Otherwise build breaks for
boards that do not support display init yet.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=Compiles for both rush and ryu. Display comes up for ryu in both normal and
dev mode.
Change-Id: I81b4d289699e7b0c2758ea1a009cbabaf8a2ce28
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b9b42486f203d332f6068ccd6f4a1a982d327a6b
Original-Change-Id: I5c8fde17d57e953582a1c1dc814be4c08e349847
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Commit-Id: ce2883b21d3fbfd54eac3a355fb34ec70e9f31ad
Original-Change-Id: Ib4a3c32f1ebf5c6ed71c96a24893dcdee7488b16
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/9519
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add dsi and related dc, panel configuration functions.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Change-Id: I8440b6dfccc7ed7cd280a0df3a98cbc7b7d66070
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fb08563f67daf9a616b60609c4523b823d34f8e3
Original-Change-Id: I87b8047e23ebe114af353fcce5924a46621d16d2
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/227202
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9517
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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In order to properly support more arm64 SoCs PSCI needs
to handle the hierarchy of cpus/clusters within the SoC.
The nodes within PSCI are kept in a tree as well as
a depth-first ordered array of same tree. Additionally,
the PSCI states are now maintained in a hierachal manner.
OFF propogates up the tree as long as all siblings are
set to OFF. ON propogates up the tree until a node is
not already set to OFF.
The SoC provides the operations for determining how many
children are at a given affinity level. Lastly, the
secmon startup has been reworked in that all non-BSP CPUs
wait for instructions from the BSP.
BUG=chrome-os-partner:32136
BRANCH=None
TEST=Can still boot into kernel with SMP.
Change-Id: I036fabaf0f1cefa2841264c47e4092c75a2ff4dc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 721d408cd110e1b56d38789177b740aa0e54ca33
Original-Change-Id: I520a9726e283bee7edcb514cda28ec1eb31b5ea0
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/226480
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9390
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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BUG=chrome-os-partner:32684
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt using vboot2
Original-Change-Id: Ibf7666d273e4d1af719c60d3f02bddcb4461f4bd
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/221576
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 8335915940ae9ba9e51e360df6963a27b05d6324)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I7d3d5cda4c4be945931d9133ab18680dac1dcefe
Reviewed-on: http://review.coreboot.org/9430
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add GENERIC_UDELAY Kconfig option so that a generic
udelay() implementation is provided utilizing the
monotonic timer. That way each board/chipset doesn't
need to duplicate the same udelay(). Additionally,
assume that GENERIC_UDELAY implies init_timer()
is not required.
BUG=None
BRANCH=None
TEST=Built nyan, ryu, and rambi. May need help testing.
Change-Id: I7f511a2324b5aa5d1b2959f4519be85a6a7360e8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1a85fbcad778933d13eaef545135abe7e4de46ed
Original-Change-Id: Idd26de19eefc91ee3b0ceddfb1bc2152e19fd8ab
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219719
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9334
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This patch creates a new mechanism to define the static memory layout
(primarily in SRAM) for a given board, superseding the brittle mass of
Kconfigs that we were using before. The core part is a memlayout.ld file
in the mainboard directory (although boards are expected to just include
the SoC default in most cases), which is the primary linker script for
all stages (though not rmodules for now). It uses preprocessor macros
from <memlayout.h> to form a different valid linker script for all
stages while looking like a declarative, boilerplate-free map of memory
addresses to the programmer. Linker asserts will automatically guarantee
that the defined regions cannot overlap. Stages are defined with a
maximum size that will be enforced by the linker. The file serves to
both define and document the memory layout, so that the documentation
cannot go missing or out of date.
The mechanism is implemented for all boards in the ARM, ARM64 and MIPS
architectures, and should be extended onto all systems using SRAM in the
future. The CAR/XIP environment on x86 has very different requirements
and the layout is generally not as static, so it will stay like it is
and be unaffected by this patch (save for aligning some symbol names for
consistency and sharing the new common ramstage linker script include).
BUG=None
TEST=Booted normally and in recovery mode, checked suspend/resume and
the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and
Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies
with ToT and looked for red flags.
Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614
Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213370
Reviewed-on: http://review.coreboot.org/9283
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-by: Aaron Durbin <adurbin@google.com>
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These binaries were being added to CBFS using hexadecimal values instead
of the CBFS binary type names. The same value was being used in
different places for different things.
For example, the value 0xAB is used for SPDs, MRC & FSP binaries.
This patch uses CBFS type names instead of hex values everywhere a
hex value was previously used.
Change-Id: Id5ac74c3095eb02a2b39d25104a25933304a8389
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8978
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
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BUG=None
BRANCH=None
TEST=Compiles successfully and pmc rst status POR is seen.
Change-Id: Ic09cb46d9be7670e467543e42b251efb1a4313d0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5dbfae6bbc0f4f30e216e37b515f4120f7833a38
Original-Change-Id: Id0c2b208222deaf099b8938ba583551979588d52
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/220721
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9106
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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BUG=chrome-os-partner:31820
BRANCH=none
TEST=Dumped Speaker Driver (AD SSM4567) regs on Ryu, looks good.
Change-Id: I9b094e9d22726d67d41f2ce78088f361c73895fd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4c0bfb5f747f55009b7c2b2ba4b24d91443b1639
Original-Change-Id: Idd5b95cfec7d3ade7508393b81ab3049ce15a2fb
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/218950
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9095
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Support the generic spin table code instead of having
the one-off implementation.
BUG=chrome-os-partner:32082
BRANCH=None
TEST=Built and booted to kernel w/ smp. Both w/ and w/o secure monitor.
Change-Id: I8557298d1a159b70818cbd8864470ff0d8a46fb1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8d89af95a7919f0b8acc92d82f3abda965514ccf
Original-Change-Id: I24d56a30fdabd7a35ebc28dcc355c675de823a51
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218655
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9085
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully and secmon loads and jumps to payload successfully.
Change-Id: I929cf2c938fb5d8c20e13fbd1fdbd349378914ff
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2e5d6adc63c4d820417985e34f1f04810b38422b
Original-Change-Id: I442546178ad945e7639a99dd2943d13a69b06d09
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214372
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9081
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Until PSCI is functional the other core still needs to be
brought up in the kernel. The kernel boots these cpus with
the spin table which is just an address in memory to monitor
a jump location.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and brought up secondary core in linux.
Change-Id: Iaa69110f6a647d8fd4149119d97db4fc45d7da00
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 01ca36685852bc5dd85fd4015c8a1e600e23e7ca
Original-Change-Id: Ieaf19cd70aff3e6c8de932e04b1b5aba71822a97
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214777
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9021
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Implement smp_processor_id() for the arm64 cores.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built.
Change-Id: Id2fca068f92cdc816b02b5e7ce1229517787684a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d5c5c68329631ce0fc3cebef1c2422aa44ac192d
Original-Change-Id: I7a1cd2f94ba4ae1854450cc60ef8a62f2457aabb
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214664
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9008
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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In order to more easily bring up the 2nd core refactor
the cpu startup logic. A common 32bit_entry.S is compiled
both for romstage and ramstage to provide the common 32-bit
entry point.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted ryu to the kernel. Also, can get the 2nd
core up out of reset.
Change-Id: I0c2c9f637189009767e8d5510732678c64e62a2a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7394b271bf67dfad8a601f41faaac8f07ae6d4a5
Original-Change-Id: Id810df95c53d3dc8b36d8bd21851d3b0006a8bc2
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213850
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9001
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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This provides are barebones initialization for tegra132 GIC
on CPU0. It routes all interrupts to CPU0, moves them all
into group 1, and attempts to allow non-secure access for
all registers (doesn't appear to be implemented, though).
BUG=chrome-os-partner:31449
BRANCH=None
TEST=Built and booted past smp init in the kernel. Timers
appear to be flowing now since jiffies are updated.
Change-Id: Id45c13cc23e50feed3d88da13420c9eb694498a0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 81bad0a53083baa7af0f1fd5f82fef0538ee62df
Original-Change-Id: I69dd9ae53f259e876a9bc4b9d7f65330150d2990
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212795
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8995
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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I2C6 has a special mux in the SOR/DC domain, so there's a ton
of devices that need to be clocked, SOR unpowergated, and then
the I2C6 muxing done in the DPAUX_HYBRID_PADCTL register.
BUG=none
BRANCH=none
TEST=none, built rush/ryu AOK
Change-Id: Ibeeda763b7fb30fabaee85d03fbf7d5efb42a30a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0b4da98e20a89b045f2d5b5033a27cd7ab855f35
Original-Change-Id: I4aaa74ef1b3009da621d1a2ef6f79de8ebf545e2
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/212887
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8992
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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Continuing down the path of easing mainboard maintenance
provide a way to bring up the USB 2.0 ports through funit.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=With ryu patch was able to get same sporadic USB communication.
Change-Id: Ic75821acf1d48a9f1659849fa007251c61658640
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5183c5081a95219f84c4d6dfca70926b383abc1a
Original-Change-Id: Iee5ca30b3c8b876a9cae7b91db096fef933a8412
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212332
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8938
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With non-cacheable memory region and dma range addition, booting from usb
reaches the same point as mmc.
Change-Id: I218c751f41fb881af4fed0bcccc378dde1fd07b4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a26e07b58f454c598bf5b7a4940c238135548bbd
Original-Change-Id: I1083f8de2bfbe9a233d317b29b8fc56f47c7061d
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211039
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8937
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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This api provides a common interface to initialize various clock sources,
dividers as well as enabling the clock for various functional units.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Compiles successfully for rush and boots till last known good point.
Change-Id: I2b8df5abf7301bc940315427af4cb38a635f07f8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9814f93a9f99fc9df6267167f991ebef427e9ae3
Original-Change-Id: I7abb193d6a9cfa448df1c48c346b4edbad802329
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211765
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8921
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
coreboot already has a reset API. Utilize it by selecting
HAVE_HARD_RESET. The tegra132 boards have to provide the
hard_reset() implementation as that involves board-specific
bits. The tegra132 code then provides a cpu_reset() routine
that just promotes that call to a hard_reset().
For the existing tegra132 boards remove the unnecessary files
from the build.
BUG=chrome-os-partner:30784
BRANCH=None
TEST=Ensured hard_reset() does something on Ryu.
Change-Id: I6d5aa928fec95b361175e35e0a26812829ffdfc3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 31edd4ff7486ded87d2525cd360d48959b6aef7c
Original-Change-Id: I1e1b014062dafb5d81fb9da40006c5405073a95d
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211131
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8911
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
It's helpful to be able to track this information. Therefore
dump it in to the console log.
BRANCH=None
BUG=chrome-os-partner:31126
TEST=Built and ran on rush. Revision information is put out on the
console.
Change-Id: I22e7d222259c1179b90edda6d7807559357f6725
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 18d318331b696a6a32e0a45b8f903eb740896b02
Original-Change-Id: Ic95382126a6b8929d0998d1c9adfcbd10e90663f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210903
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8905
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Instead of sprinkling the pad configuration and pinmux
selection throughout the code allow for a data-driven
initialization sequence. Most of the calls in the
original pinmux functions require 12 bytes per pad
plus the support code. This implementation allows for
4 bytes per pad in addition to the support code.
BUG=chrome-os-partner:29981
TEST=Built and booted into depthcharge on rush.
Change-Id: I22c243a5f9891a97e14b78d8c8064e36adaf50b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9329c17bbadcaab803b38842e38e1704d262817d
Original-Change-Id: I3a119b4068e880b74a0a1597f143d7c4e108a6c1
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210833
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8875
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Update VBOOT_STUB_DEPS to include monotonic_timer.c
BUG=chrome-os-partner:30784
BRANCH=None
TEST=Compiles successfully for rush
Original-Change-Id: I3cc559fa21c444da1a7976e4952ea4941c2a1428
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209972
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 8096ae56c4df4013cfc798944b98dd1078c8b451)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I68c13617b96fd872d1eaa9278de6647eccb795c3
Reviewed-on: http://review.coreboot.org/8674
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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Add support for mmu initialization and enabling caches. mmu_operations provides
functions to add mmap_regions using memrange library and then calls mmu_init for
armv8.
BUG=chrome-os-partner:30688
BRANCH=None
TEST=Compiles rush successfully and boots until depthcharge load. Goes past
all the earlier alignment errors.
Original-Change-Id: I57c2be80427fa77239093c79ece73e31fd319239
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208762
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit a6141d13d40cfa5a493bde44e69c588dda97e8fd)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I33bf4b2e28b85a3117b566cb8497f2bd5aabb69b
Reviewed-on: http://review.coreboot.org/8647
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
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With this memory resource, the payload loading code should be
able to create a bounce buffer and load the payload successfully.
Adapted from tegra124 soc.c
BUG=None
BRANCH=None
TEST=Built and booted to ramstage on rush.
Original-Change-Id: I2e336ce93c1b0236104e63d3785f0e3d7d76bb01
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208121
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 20765da0b15ee8c35a5bbfe532331fc6b1cef502)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I267ced473ad0773b52f889dfa83c65562444c01f
Reviewed-on: http://review.coreboot.org/8644
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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Provide a default Trust Zone region size of 1MiB, and
correctly account for it in the AVP and the arm64 cores.
The different path between the arm64 cores and the AVP
is because the AVP cannot access the Trust Zone region
registers. Therefore the AVP needs to account for the
Trust Zone region.
BUG=chrome-os-partner:30572
BRANCH=None
TEST=Built and ran. Noted Trust Zone region being accounted for.
Original-Change-Id: Ie0f117ec7a5ff8519c39778d3cdf88c3eee57ea5
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208062
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 22f2fa05c009c58f53b99b9ebe1b6d01fdac5ba7)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I28506b4401145d366b56126b2eddc4c3d3db7b44
Reviewed-on: http://review.coreboot.org/8639
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
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In order to make sharing of the location of MTS microcode easier
provide a Kconfig option that is the path to the files.
BUG=chrome-os-partner:30569
BRANCH=None
TEST=Built rush coreboot.
Original-Change-Id: I36775d0018fc8591d5e77c2943e28a51381713f5
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207839
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 6f1de0e7fd312c1d6798e65d4b43d586f0994337)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I660cb9d8bd13c765c89b54b0807b5b3ee836e807
Reviewed-on: http://review.coreboot.org/8614
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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The preboot MTS microcode needs to be supplied within the
bct so the BootROM can load it. The size of the bootblock
space in SPI needed to be extended to accomodate the extra
length.
BUG=chrome-os-partner:29059
BUG=chrome-os-partner:29060
BRANCH=None
TEST=Built rush with updated cbootimage with t132 support.
Original-Change-Id: Iafc1837cd81cc1165a9be5da6ec7425cec2e2ffc
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/204940
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 22e054496465c74fc12afd865d14b87c5858d889)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I5e46c408a7215ecc789b0a0f35070ef9036a7d11
Reviewed-on: http://review.coreboot.org/8466
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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Enabled CBMEM support for t132 platforms. Some of the existing
code is moved around to avoid dependencies in the other stages
that need it.
BUG=None
BRANCH=None
TEST=Built and booted a rush with cbmem support.
Original-Change-Id: I78a31b58ab9cc01a7b5d1fffdb6c8ae0c446c7dd
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207163
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit f552197dbda06c754b5664c3bed4ed361154229a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8fa2919714b467cc976e5bb5c4716e5b7979694b
Reviewed-on: http://review.coreboot.org/8589
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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The startup sequence for cpu0 is implemented while also
providing a trampoline for transitioning to 64-bit mode because
the denver cores on t132 come out of cold reset in 32-bit mode.
Mainboard callbacks are provided for providing the board-specific
bits of the bringup sequence.
BUG=chrome-os-partner:29923
BRANCH=None
TEST=Built and booted through ramstage.
Original-Change-Id: I50755fb6b06db994af8667969d8493f214a70aae
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207263
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit 17f09bf4bdb43986c19067ca8fd65d4c5365a7c6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I14d99c24dd6e29a4584c8c548c4b26c92b6ade97
Reviewed-on: http://review.coreboot.org/8586
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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1) In order to avoid stack from overflowing during ramstage decompression,
initialize stack right at the beginning of romstage.
2) Declare different Kconfig options for stack at each stage.
3) Provide a macro that does stack seeding if required and calls appropriate
function.
BUG=None
BRANCH=None
TEST=Compiles and runs successfully on rush.
Original-Change-Id: I55d6ce59ea91affba3e86d68406921497c83fb52
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/206880
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 5e32d73803a2a9d222fcc4ca5f58efd3abe95d34)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ib833a1badb170a33cbf20d232019425b59db60cd
Reviewed-on: http://review.coreboot.org/8583
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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The armv8 cores need to have microcode loaded before they can
be taken out of reset. Locate and load the MTS microcode at the
fixed address of 0x82000000. The ccplex, once enabled, will
decode and transfer the microcode to the carveout region.
BUG=chrome-os-partner:29922
BRANCH=None
TEST=Built and ran. Confirmed dump of MTS region after loading code.
Original-Change-Id: Ie5ab72e5363cbdb251d169356f718020d375fce6
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/206290
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 6726d8862c08b155b9218aa5e2e39428a105089e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I425c2e2fd1eaec49d81bef1ff4bf4f36da9296df
Reviewed-on: http://review.coreboot.org/8580
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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There's no reason to duplicate code in the mainboards. Therefore,
drive the flow of romstage boot in the SoC. This allows for
easier scaling with multiple devices.
BUG=None
BRANCH=None
TEST=Built and booted to same place as before.
Original-Change-Id: I0d4df84034b19353daad0da1f722b820596c4f55
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205992
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie74f0eb1c983aff92d3cbafb7fe7d9d7cb65ae19
Reviewed-on: http://review.coreboot.org/8575
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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Add support for initializing dram within romstage. This is an essential before we
move to the armv8 core.
BUG=None
BRANCH=None
TEST=Compiles succesfully for rush. Tried writing to and reading value from the
base of sdram and it worked fine. Also tested with primitive_memtest CL:
https://chromium-review.googlesource.com/#/c/186309/5
Original-Change-Id: I67ec04c766e249c9727b0cf2ba216522c862c2f5
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205823
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 33c468b16e7ccd8cf9266d6a9ca30c02da104821)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I4baface2c109ca74f85f43a25508677c46c64159
Reviewed-on: http://review.coreboot.org/8574
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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Pull in mainboard specific bootblock_init function from nyan into
rush. Additionally, pull in all files required for proper compilation of rush
after adding the bootblock_init function
BUG=None
BRANCH=None
TEST=Compiles successfully for rush
Original-Change-Id: I69c736275f66eca3ad92f97d166e91d4c2301364
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205583
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit e7aac547026717d7380f71593010e3ea34ecea51)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie26f91f8caaa06af3b195246febcdc70b9fe9795
Reviewed-on: http://review.coreboot.org/8570
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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Enable adding of clock.c to romstage and ramstage in addition to bootblock. Code
for enabling armv8 core is not included yet. clock_init added to bootblock.c
BUG=None
BRANCH=None
TEST=Compiles successfully for rush.
Original-Change-Id: I858c41a83d665da2c406707586b5e35a732177d4
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205581
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 61dbf1db72307815c4abdc218799479c334a4882)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I688e1e1373dea26557a84507a8e92d3055862801
Reviewed-on: http://review.coreboot.org/8569
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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BUG=None
BRANCH=None
TEST=Compiles successfully
Original-Change-Id: Ia9420cfec5333dd5477f04cf080bdad8a37db025
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203143
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit a1037f203c6a07cb116eeb1632cb7200ad022cd3)
This cherry-pick was modified to match the tegra124 uart.c, which
uses the idx and base address calculations instead of Kconfig settings.
This driver could use the 8250MEM driver when the ARM vs x86 IO
calling convention is worked out.
Change-Id: I6e439359b8bb541db4679ac144c519cf251ffed6
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8517
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
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It's not very useful to try to link a host tool into
the bootblock image.
Change-Id: Id3b6496c061d41184fbb516d56746855b455b0c3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/8473
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
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Builds with cbootimage.
BUG=None
BRANCH=None
TEST=build test
Original-Change-Id: I796f171031bacf17106878d4a554e8f1cbfe93f8
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203145
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 4778ae4d08a25306407f0fd2fe47976d63463f9d)
Increase the bootblock area for the larger BCT that is generated by
the coreboot version of the cbootimage tool.
Change-Id: I42b8208504bf4936a9fa14f820d665590f6a3754
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8413
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add basic support for tegra132 soc.
BUG=None
BRANCH=None
TEST=Compiles successfully for rush board using tegra132 soc
Original-Change-Id: If2a3de80026e7729ac6da8484ff6c56607c52a63
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197398
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 4746bff6e9f4b20abc44d0b6fce9691aea63583c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: If2a3de80026e7729ac6da8484ff6c56607c52a63
Reviewed-on: http://review.coreboot.org/8040
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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