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2024-09-12soc/mediatek: Remove redundant struct pad_func and PAD_* definitionsYidi Lin
Clean up redundant `struct pad_func` and `PAD_*` definitions. This patch also refactors the PAD_* macros by, - Repurposing PAD_FUNC and dropping PAD_FUNC_SEL. - Adding PAD_FUNC_DOWN and PAD_FUNC_UP to avoid the implicit initialization. BUG=none TEST=emerge-{elm, kukui, asurada, cherry, corsola, geralt, rauru} coreboot Change-Id: I12b8f6749015bff52988208a7c3aa01e952612c6 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84222 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-09soc/mediatek/common: Move common GPIO definitions to gpio_defs.hYidi Lin
BUG=none TEST=emerge-{asurada, cherry, corsola, geralt, rauru} coreboot Change-Id: If35dcc4d88732f92c7c43a5eed0478ec52cf1802 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84221 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-06soc/mediatek/mt8196: Add EINT supportYidi Lin
Add support to configure GPIOs to pull for external interrupts (EINT). BUG=b:334723688 TEST=Talk with Ti50 TPM using IRQ flow. Change-Id: Ibeb2dafcd9909b4afbfa81728700718f01d3818f Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84026 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-02mb/google/cherry: Complete PCIe reset in romstageYidi Lin
De-assert PERST# at romstage to reduce the waiting time in ramstage. Before ``` [INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done, de-assert PERST# now [INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries) ``` After ``` [INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done, de-assert PERST# now [DEBUG] wait_perst_asserted: 457568 us elapsed since assert PERST# [DEBUG] wait_perst_done: 163413 us elapsed since de-assert PERST# [INFO ] mtk_pcie_domain_enable: PCIe link up success (1 tries) ``` BUG=none TEST=boot from NVMe Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84118 Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-09-02soc/mediatek: Add mtk_pcie_deassert_perst for early PCIe resetYidi Lin
Even we assert PRSET# early to save the delay between PERST# assertion and de-assertion. MediaTek PCIe driver still takes 47ms waiting for PCIe link up. (1ms delay for each try) ``` [INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries) ``` Refactor common/pcie.c and add mtk_pcie_deassert_perst for early PCIe reset. So we can de-assert PERST# at early stage to improve the boot time. BUG=b:361728592 TEST=emerge-cherry coreboot Change-Id: I008e95263bfaf0119353382c2d2ce5ce29c6a382 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84117 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
2024-09-02soc/mediatek: Add EARLY_INIT_PCIE_RESET to early_init_typeYidi Lin
Add EARLY_INIT_PCIE_RESET for early PERST# de-assertion. BUG=b:361728592 TEST=emerge-cherry coreboot Change-Id: I7ab85694e85a4c3f77fefc22efe16734c347a716 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
2024-09-02soc/mediatek/common: Move mtk_pcie_reset to common/pcie.cYidi Lin
mtk_pcie_reset can be shared with MT8196. So move it to common/pcie.c. BUG=b:361728592 TEST=emerge-cherry coreboot Change-Id: Ib540cf9cc568206a1e78306624f4df7c5631c128 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-09-02soc/mediatek/common/pcie: Use clr/setbits32pYidi Lin
Use clr/setbits32p to make code cleaner. BUG=none TEST=emerge-cherry coreboot Change-Id: Id99d5aafdf4d687dbe3a0bef29b148537cf58dd8 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
2024-09-02soc/mediatek/common/pcie: Add DEVTREE_CONST qualifierYidi Lin
Currently pcie.c is built into ramstage only, where DEVTREE_CONST is an empty macro, so there's no problem with that. However, if we would like to include that file in pre-ramstage, then DEVTREE_CONST would be 'const', leading to the following build error: ``` src/soc/mediatek/common/pcie.c:104:26: error: assignment discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers] 104 | root_dev = pcidev_path_on_root(devfn); | ^ ``` BUG=none TEST=emerge-cherry coreboot Change-Id: Ia7c95424019ec0dca50bbc6be7f81b6180d06d6e Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84113 Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-08-30soc/mediatek/mt8196: Enable VBOOT_DEFINE_WIDEVINE_COUNTERSYu-Ping Wu
To support Widevine DRM, enable VBOOT_DEFINE_WIDEVINE_COUNTERS. BUG=b:357976379 TEST=emerge-rauru coreboot BRANCH=none Change-Id: I3760c30b175338165f8e11b59c7cfa830070a19e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-08-29soc/mediatek/mt8196: Add USB host supportMingjin Ge
Add USB host function support. TEST=read usb data successfully. BUG=b:317009620 Signed-off-by: Mingjin Ge <mingjin.ge@mediatek.corp-partner.google.com> Change-Id: Ia4efcddac9bf5e04e688648a5c22384075a0b026 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-08-24soc/mediatek/mt8196: Add I2C driver supportHao Han
Add I2C controller driver. TEST=build pass BUG=317009620 Change-Id: I617ad8a43ce8b492b1a0e5dc06c1f0ffe7d92b5e Signed-off-by: ot_hao.han@mediatek.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/83927 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-08-24soc/mediatek/mt8196: Initialize watchdogJarried Lin
Add watchdog support for MT8196. TEST=build pass and WDT uart log BUG=b:317009620 Change-Id: I9d5e71aa27d469855c2bd65abc5309d69a018750 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-08-24soc/mediatek/mt8196: Enable MMU operation for L2C SRAM and DMAJarried Lin
- Turn off L2C SRAM and reconfigure as L2 cache: Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. - Configure DMA buffer in DRAM: Set DRAM DMA to be non-cacheable to load blob correctly. TEST=build pass, register(disable_l2c) read ok BUG=b:317009620 Change-Id: I6a3cb63d3418f085f5d8d08b282dd59ea431c294 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83925 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-08-24soc/mediatek: Refactor MMU operation for L2C SRAM and DMAJarried Lin
Refactor mmu operation by - moving mtk_soc_disable_l2c_sram to l2c_ops.c - keeping mtk_soc_after_dram in mmu_cmops.c Change-Id: I14bd8a82e0b5f8f00ce2b52e5aee918e130912d4 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83937 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-24soc/mediatek/mt8196: Add NOR-Flash supportJarried Lin
Add NOR-Flash drivers for flash read/write. TEST=read nor flash data successfully. BUG=b:317009620 Change-Id: Id0a19f0520020f16c4cf9d62da4228a5b0371b91 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83923 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-24soc/mediatek: Move SNFC pad_func into MediaTek common directoryJarried Lin
To reduce duplicate pad_func of MediaTek SoCs, move the pad_fun to a common directory. TEST=Build pass BUG=b:317009620 Change-Id: I145233ef887a38251e8fc129b8357f236c5f7a2b Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-08-24soc/mediatek: Require MCU and DRAM blobs to existYu-Ping Wu
When the config of MCU firmware blob such as CONFIG_SPM_FIRMWARE is non-empty, we should always expect the file to exist. Similarly, since the device is unlikely to boot without the DRAM blob (assuming MRC_CACHE doesn't contain valid memory training data), dram.elf should always exist as well. Therefore, remove the check for the existence of the blobs. Build would fail if any of the blobs is missing. Change-Id: I755e7c5a70b34b0c3d3915ab339c65263688aad7 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84053 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-23soc/mediatek/mt8196: Add GPIO driverJarried Lin
Add GPIO driver for other modules to control GPIO pins. TEST=build pass BUG=b:317009620 Change-Id: I6d1e6ef17660308c8de908697ffba6b5f17ff9ae Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83922 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-23soc/mediatek/common: Move GPIO definition to the common directoryJarried Lin
To reduce duplicate gpio_base.h in each SoC folder, move gpio_base.h to mediatek/common folder. TEST=Build pass BUG=b:317009620 Change-Id: I815df8a3083cf04b821165ec834ca98ee71a0c78 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-08-23soc/mediatek/common: Print error if GPIO raw_id is not in the rangeJarried Lin
TEST=build pass BUG=317009620 Change-Id: I5dffdb9f3e4e7e0d49209e6012893cd246948ee8 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83987 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-08-10soc/mediatek/common: Refactor EINT driverYidi Lin
Refactor EINT driver by - Move `pos_bit_calc_for_eint` to `common/gpio_eint_v1.c` and rename to `gpio_calc_eint_pos_bit`. - Implement `gpio_get_eint_reg` to obtain EINT base address. This change is prepared for the driver change in MT8196. BUG=b:334723688 TEST=EINT works on Geralt Change-Id: Ie53abc23971bfa39250ebd7dd48e28d6b91c5973 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83703 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-29soc/mediatek/mt8196/memlayout: Fix the location of BOOTBLOCK commentYu-Ping Wu
The comment for the BOOTBLOCK region should be written right above the BOOTBLOCK declaration. BUG=b:317009620 TEST=none BRANCH=none Change-Id: I7afdf74844a9d97169b4e4a23c3c9c6060e886d9 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83649 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-26soc/mediatek/mt8188/memlayout: Add a space in SRAM_L2C_START commentYu-Ping Wu
Change-Id: I1888fedcc66ae13c76331d3f2f4465197ae51d35 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-07-23soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoCJarried Lin
Add new folder and basic drivers for Mediatek SoC 'MT8196'. Refer to MT8196_Chromebook_Application_Processor_Datasheet_V1.0 for MT8196 SPEC detail. This patch also enables UART and ARM arch timer. TEST=saw the coreboot uart log to bootblock BUG=b:317009620 Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-07-22soc/mediatek: Move memmory macros into MediaTek common directoryJarried Lin
To reduce duplicate memmory macros of MediaTek SoCs, move the header file to a common directory. TEST=Build geralt pass BUG=b:317009620 Change-Id: Iea4add8fe3735085c13438a2e177bec177913191 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83571 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22soc/mediatek: Move symbols.h into MediaTek common directoryJarried Lin
To reduce duplicate region declarations of MediaTek SoCs, move the header file to a common directory. BUG=b:317009620 TEST=Build geralt pass. Change-Id: Iad1c9f520cdc5c6ad2b55e8f4ec6149fa47b17b1 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83570 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21soc/mediatek/mt8188: Respect ARM64_BL31_OPTEE_WITH_SMC optionYu-Ping Wu
Since BL31_MAKEARGS is already handled in arm64/Makefile.mk, remove the duplication from mt8188/Makefile.mk. In addition, reserve the memory range for running OP-TEE only if ARM64_BL31_OPTEE_WITH_SMC is enabled. BUG=b:347851571 TEST=emerge-geralt coreboot BRANCH=geralt Change-Id: I88a9a07a685a6c9fe9739b6101ccb8a5ce23fd8b Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-06-07soc/mediatek/mt8173/i2c.c: Remove unused macroElyes Haouas
Change-Id: I90fbd7ce0e1c6cd15d73cb73dc774df2de56b346 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-06-04soc/mediatek/common: Prefer include <soc/gpio.h> via <gpio.h>Elyes Haouas
Change-Id: I50e874790dedcb6bf3b3ac8368821f22611aa3b7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82894 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29tree: Remove unused <string.h>Elyes Haouas
Change-Id: I9ed1a82fcd3fc29124ddc406592bd45dc84d4628 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-29tree: Use <stdio.h> for snprintfElyes Haouas
<stdio.h> header is used for input/output operations (such as printf, scanf, fopen, etc.). Although some input/output functions can manipulate strings, they do not need to directly include <string.h> because they are declared independently. Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29tree: Remove unused <stddef.h>Elyes Haouas
Change-Id: I7d7ad562eeff7247b7377b6570d489faee0aeda0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82669 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-28soc/mediatek/mt8188: Decrease OP-TEE image size from 80 MB to 70 MBGavin Liu
The secure buffer shrank from 42 MB to 32 MB, decreasing the total OP-TEE image size from 80 MB to 70 MB. BUG=b:246837563 TEST=emerge-geralt coreboot build coreboot and verify SVP works well Change-Id: I6729e65f83ef994fe59b5bd4ed098e6d3a847695 Signed-off-by: Gavin Liu <gavin.liu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-05-09soc/mediatek/mt8188: devapc: set devapc permission for MFGFei Yan
In order to support SVP Feature, EMI-MPU has to give MFG permissions to allow MFG to access secure buffer by secure read and write. Currently MFG is in domain 0, which include many other masters. Move MFG to domain 6. Set MFG remap, so that MFG can switch to protect mode by MFG register. Change MFG permission from NO_PROTECTION to SEC_RW_ONLY for domain 0, so that only AP in secure mode can access MFG_S_S-2 and MFG_S_S-5. BUG=b:313855815 TEST=emerge-geralt coreboot Change-Id: Ic6fb7d85bf9d4d92946a045a274b274abc440e1d Signed-off-by: Fei Yan <fei.yan@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-03mb/google/corsola: Initialize USB port 0Wentao Qin
The default MT8186 platform is to initialize USB3 port 1. Use option bit 27 in fw_config to enable initialization of USB2 port 0 to support devices mounted on it. BUG=b:335124437 TEST=boot to OS from USB-A boot to OS from SD Card BRANCH=corsola Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82089 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-12tree: Drop duplicated <device/{path,resource}.h>Elyes Haouas
<device/device.h> is supposed to provide <device/{path,resource}.h> Change-Id: I2ef82c8fe30b1c1399a9f85c1734ce8ba16a1f88 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-11tree: Drop unused <halt.h>Elyes Haouas
Change-Id: Icd00f30a96c53f70babdcb8a77c4b6c2868619d8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-11tree: Drop unused <stdlib.h>Elyes Haouas
Change-Id: Ie7e36cfa5a09d94bb58f12f9bd262255a630424c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81819 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-11tree: Drop unused <string.h>Elyes Haouas
Change-Id: I0e216cbc4acf9571c65c345a1764e74485f89438 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81818 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09tree: Drop unused <delay.h>Elyes Haouas
Change-Id: I265e427254ce9f735e65b0631c43f98bc778a34f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81812 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-09tree: Drop unused <console/console.h>Elyes Haouas
Change-Id: Ib1a8fc50217c84e835080c70269ff50fc001392c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81811 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09soc/mediatek/common/include/soc: Include header file for check_memberRuihai Zhou
To fix the build error below when include i2c_common.h, we should include the necessary header for check_member. """ src/soc/mediatek/common/include/soc/i2c_common.h:24:42: error: expected ')' before numeric constant 24 | check_member(mt_i2c_dma_regs, dma_tx_len, 0x24); | ^~~~~ | ) """ TEST=abuild -t google/geralt -b ciri -a Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I266571686e452e2b7514afee42ff0a48f8891831 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81684 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-28soc/mediatek: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I0ce2b61329efede1ba8a02446610e3eb635ceedc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81462 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-15treewide: Move stdlib.h to commonlibMaximilian Brune
This patch moves commonlib/stdlib.h -> commonlib/bsd/stdlib.h, since all code is BSD licensed anyway. It also moves some code from libpayloads stdlib.h to commonlib/bsd/stdlib.h so that it can be shared with coreboot. This is useful for a subsequent commit that adds devicetree.c into commonlib. Also we don't support DMA on arm platforms in coreboot (only libpayload) therefore `dma_malloc()` has been removed and `dma_coherent()` has been moved to architecture specific functions. Any architecture that tries to use `dma_coherent()` now will get a compile time error. In order to not break current platforms like mb/google/herobrine which make use of the commonlib/storage/sdhci.c controller which in turn uses `dma_coherent` a stub has been added to arch/arm64/dma.c. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I3a7ab0d1ddcc7ce9af121a61b4d4eafc9e563a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/77969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-02-26soc/mediatek: Add `MEDIATEK_DRAM_ADAPTIVE` config to support dram adaptiveYidi Lin
Starting from MT8195, MediaTek platform supports "dram adaptive" to automatically detect dram information, including channel, rank, die size..., and can automatically configure EMI settings. So we can just pass a placeholder param blob to `mt_mem_init_run` by enabling this option. Platforms (MT8173, MT8183, MT8192) which do not support "dram adaptive" need to implement `get_sdram_config` to get onboard DRAM configuration info. TEST=emerge-geralt coreboot && emerge-asurada coreboot TEST=CONFIG_MEDIATEK_DRAM_ADAPTIVE is set to y on geralt TEST=CONFIG_MEDIATEK_DRAM_ADAPTIVE is no set on asurada Change-Id: I05a01b1ab13fbf19b2a908c48a540a5c2e1ccbdc Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-02-18soc: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ie7bc4f3ae00bb9601001dbb71e7c3c84fd4f759a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80596 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-08soc/mediatek/mt8188: Enable CROS_WIDEVINE_SMCYi Chou
BUG=b:248612503 TEST=Test with crrev.com/c/4756330 BRANCH=none Signed-off-by: Yi Chou <yich@google.com> Change-Id: I3dded9042abd85a948598f98475c21a1af9b4d80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80315 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-02-02lib: Move IP checksum to commonlibJulius Werner
This patch moves the IP checksum algorithm into commonlib to prepare for it being shared with libpayload. The current implementation is ancient and pretty hard to read (and does some unnecessary questionable things like the type-punning stuff which leads to suboptimal code generation), so this reimplements it from scratch (that also helps with the licensing). This algorithm is prepared to take in a pre-calculated "wide" checksum in a machine-register-sized data type which is then narrowed down to 16 bits (see RFC 1071 for why that's valid). This isn't used yet (and the code will get optimized out), but will be used later in this patch series for architecture-specific optimization. Change-Id: Ic04c714c00439a17fc04a8a6e730cc2aa19b8e68 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80251 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-01-31include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard
Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-24soc/*: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6f502b97864fd7782e514ee2daa902d2081633a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80074 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-17soc/mediatek/mt8188: Enable EARLY_MMU_INITYidi Lin
The boot time is improved by 65ms. (762ms -> 697ms) BUG=b:320381143 TEST=check timestamps in cbmem Change-Id: I74191ab8cbefa08b7e296312645ea40b46fabf77 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79991 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-17soc/mediatek: Add EARLY_MMU_INIT kconfig optionYidi Lin
Accessing RAM before mmu initialized is time consuming. During mmu initialization, `mmu_init()` and `mmu_config_range()` write logs to the console buffer and contribue the extra boot time. This patch adds a kconfig option to move `mtk_mmu_init()` to `bootblock_soc_early_init()`. When `EARLY_MMU_INIT` is enabled, mmu is initialized before `console_init()` ready. So `mmu_init()` and `mmu_config_range()` won't write logs to the console buffer and save the boot time. It saves about 65ms on Geralt with EARLY_MMU_INIT enabled. Before: 0:1st timestamp 239,841 (0) 11:start of bootblock 239,920 (79) 12:end of bootblock 323,191 (83,271) After: 0:1st timestamp 239,804 (0) 11:start of bootblock 239,884 (80) 12:end of bootblock 258,846 (18,962) BUG=b:320381143 TEST=check timestamps in cbmem Change-Id: I7f4c3c6c836f7276119698c6de362794cf4222a6 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-01-10mb/google/cherry: Use common mtk_display_init()Yidi Lin
TEST=check FW screen on dojo Change-Id: Ie870899226588ac2a2e80f77e434455f4913d387 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-01-10mb/google/corsola: Use common mtk_display_init()Yidi Lin
TEST=check FW screen on Steelix, Tentacruel and Starmie Change-Id: I429218d59389a6ab86b522dd597c07fa5b8ea821 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79777 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-10soc/mediatek: Add common implementation to configure displayYidi Lin
The sequences of configure_display() are similar on MediaTek platforms. The sequences usually involve following steps: 1. Setup mtcmos for display hardware block. - mtcmos_display_power_on() - mtcmos_protect_display_bus() 2. Configure backlight pins 3. Power on the panel - It also powers on the bridge in MIPI DSI to eDP case. 4. General initialization for DDP(display data path) 5. Initialize eDP/MIPI DSI accordingly, - For eDP path, it calls mtk_edp_init() to get edid from the panel and initializes eDP driver. - For MIPI DSI path, the edid is retrieved either from the bridge or from CBFS (the serializable data), and then initializes DSI driver. 6. Set framebuffer bits per pixel 7. Setup DDP mode 8. Setup panel orientation This patch extracts geralt/display.c to mediatek/common/display.c and refactors `struct panel_description` to generalize the display init sequences. configure_display() is also renamed to mtk_display_init(). TEST=check FW screen on geralt. Change-Id: I403bba8a826de5f3fb2ea96a5403725ff194164f Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79776 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-04soc/mediatek/mt8188: devapc: Allow APU to access BND_NORTH_APB2_SNina Wu
Update BND_NORTH_APB2_S's domain 5 permission to allow the access from APU. The APU requires certain information saved in BND_NORTH_APB2_S for voltage tuning. If this information cannot be retrieved, the APU may operate at a high frequency with low voltage. Consequently, the APU may not function as expected. Change-Id: I967b138dc5517e54da7fbf94b9e502e478c991b5 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79348 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-01soc/mediatek/mt8188: Support loading OP-TEE via an SMCkiwi liu
This patch adds compilation flags to BL31 to support loading OP-TEE via an SMC from rootfs. This patch also reserves 80MB memory space for running the OP-TEE image. BUG=b:246837563 TEST=emerge-geralt coreboot Change-Id: Ic38c8beb59c090ae56c5be6821dd8625435609e9 Signed-off-by: Kiwi Liu <kiwi.liu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78801 Reviewed-by: Kiwi Liu <kiwi.liu@mediatek.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-20device/device.h: Rename pci_domain_scan_busArthur Heymans
On all targets the domain works as a host bridge. Xeon-sp code intends to feature multiple host bridges below a domain, hence rename the function to pci_host_bridge_scan_bus. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4e65fdbaf0b42c5f4f62297a60d818d299d76f73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78326 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-10-11memlayout.ld: Increase RAMSTAGE size to more than 1MB everywherePatrick Georgi
This is in preparation of a larger heap. I went for 2MB because why not? Change-Id: I51f999a10ba894a7f2f5fce224d30bf914107c38 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-10-09soc/mediatek: PCI: Fix translation windowJianjun Wang
Dojo fails to boot from NVMe with CONFIG_RESOURCE_ALLOCATION_TOP_DOWN enabled. The root cause is using __fls() will get a smaller value when the size is not a power of 2, for example, __fls(0x3000000) = 25. Hence the PCIe translation window size is set to 0x2000000. Accessing addresses higher than 0x2300000 will fail. Fix translation window by splitting the MMIO space to multiple tables if its size is not a power of 2. Resolves: https://ticket.coreboot.org/issues/508. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, it can boot with and without the CONFIG_RESOURCE_ALLOCATION_TOP_DOWN option. BUS=b:298255933 BRANCH=cherry Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78044 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-02soc/mediatek/mt8188: devapc: Add SCP domain settingJason Chen
Configure the SCP to operate within domain 8, allowing it to access only the necessary registers. Any unauthorized access will be prevented by the DAPC. - Set SCP domain from domain 0 to domain 8. - Lock register settings down to prevent unexpected modification. BUG=b:270657858 TEST=scp bootup successful with dapc settings Change-Id: I049486c997542d91bd468e0f4662eafbca4c17e0 Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77883 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-10-02soc/mediatek/mt8188: devapc: Set master domainsNina Wu
Currently, all the masters controlled by DAPC are in domain 0. With this setting, there is a potential security problem. For example, if a certain master is somehow hacked, it may attempt to access registers that it is not supposed to, with successful results. This is due to the fact that, in the current setting, all masters are in domain 0 and can access almost all registers. To prevent this problem, we assign masters to different domains and restrict access to registers based on each domain. This patch sets domains for masters: SSPM - domain 3 CPUEB - domain 14 PCIE0 - domain 2 SPM - domain 9 Change-Id: Ie3e1d5055e72824257b66d6257982652eeb05953 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77862 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-02soc/mediatek/mt8188: devapc: Update permission for master domain setupNina Wu
Currently, all the masters controlled by DAPC are in domain 0. With this setting, there is a potential security problem. For example, if a certain master is somehow hacked, it may attempt to access registers that it is not supposed to, with successful results. This is due to the fact that, in the current setting, all masters are in domain 0 and can access almost all registers. To prevent this problem, we assign masters to different domains and restrict access to registers based on each domain. This patch updates the permission settings for domains 2, 3, 4, 5, 7, 8, 9, and 14, as these domains will be assigned masters in the upcoming patch. BUG=b:270657858 TEST=build pass Change-Id: I6e95ddb5d84a09ff865d7615596430e25b69d3fc Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77861 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-09-22soc/mediatek: Move common devapc definitions to common/Nina Wu
Move following definitions to common/ 1) the definition of the bit fields for domain remap 2) the definition of the structure for the permission of all domains Change-Id: Iac84ebc908ae384a6280388af4120f6349a32ed4 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77860 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24soc/mediatek/mt8188: Remove GPT timer initYidi Lin
GPT timer init is no longer needed after DRAM blob is switching to ARM arch timer. BUG=b:229800119 TEST=boot to kernel Change-Id: Iec1f93c96e791220feed4225959ef15c074ba577 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77388 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-23soc/mediatek/mt8188: Simplify pmif init flowSen Chu
Based on "MediaTek_EFUSE_MT8188_Confidential A_Technical Doc.docx", MT8188G used in ChromeOS project does not support clock hardware monitor. Thus, we can simplify the initialization flow by removing the hardware default value check. BUG=b:292866009 TEST=emerge-geralt coreboot BRANCH=none Change-Id: I07cd753f153da5b0aea1518a04a818214f986aeb Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77334 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-08-14soc/mediatek/mt8173/mt6391: Remove space before semicolonElyes Haouas
Change-Id: I88668d8c69da68cc28bae287f573f650f28da32e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-08-06soc/mediatek/mt8188: Support ARM arch timerYidi Lin
Use ARM architectual timer by initializing frequency to 13 MHz. Since system timer is the source of the architectual timer, we also call `timer_prepare` in `init_timer`. BUG=b:229800119 TEST=run `suite:faft_bios` to verify the firmware stability. check timestamps by cbmem. Cq-Depend: chromium:4747539 Change-Id: I8b1348044e4c92984510604b7f61611e13284d86 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76919 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14soc/mediatek/common/dsi: Add actual values to the log messagesRuihai Zhou
Per the suggestion in CB:76218, print actual values to the error messages, which may be helpful for debugging. Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: Id3a7a8c76b6ad15e7cf71225d8529f3e034935ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/76442 Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-07-10mb/google/corsola: Add support for AW37503 Power ICRuihai Zhou
The AW37503 is designed to supply positive/negative supply for driving the MIPI panel. It doesn't integrate non-volatile memory(EEPROM), so we need to program the registers at boot. We program the target positive/negative output voltage via I2C and enable the power rails by pulling up ENP and ENN pins. On Starmie, we need +/-6V power supply for the MIPI panel. We program the AW37503 registers in coreboot so that kernel can control AW37503 via fixed regulators without additional settings(what we did for TPS65132). Since we distinguish AW37503 and TPS65132 by reading the vendor ID, we need to initialize I2C bus as early as possible. Therefore, we move mtk_i2c_bus_init() to mainboard_init(). BUG=b:289482828 TEST=emerge-staryu coreboot chromeos-bootimage TEST=Test the sequence the voltage Change-Id: I9ccd4db19c93a032226f006eab0427f78f7b6dc8 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76219 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-26soc/mediatek: Enable DRAM scramble on fast calibration flowXi Chen
No matter what DRAM calibration is performed, DRAM scramble should be enabled as long as MEDIATEK_DRAM_SCRAMBLE is set to y. Currently, DRAM scramble is enabled only if full calibration is performed. Correct the behavior by adding DRAMC_CONFIG_SCRAMBLE to the header config in fast calibration flow. BUG=b:285474337 TEST=Check the scramble feature is disabled on serial build Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I907bccd4e68e040179e1971db6bf7a57b88dec1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75818 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-21soc/mediatek: Add a prompt string for MEDIATEK_DRAM_SCRAMBLEXi Chen
Make the default MEDIATEK_DRAM_SCRAMBLE value overridable by adding a prompt string. BUG=b:285474337 TEST=build pass and check scramble feature is disabled on serial build Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I703ac9aa3ccc4dd9d0fef9949c6b0d49449971a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75815 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-12soc/mediatek/mt8188: Support 4K resolution displayHsiao Chien Sung
The original clock rate 416MHz is insufficient for 4K resolution and causing the screen to glitch. Set the clock rate to 594MHz to support 4K resolution. BUG=b:236328487 TEST=Glitching screen was fixed after applying this patch Change-Id: Ic40dd28264d03ef7218ff4edd8d4182e0fe74ea3 Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75661 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-12soc/mediatek/common: Disable DRAM scramble by defaultYidi Lin
Geralt SoC does not support 'persist certain regions' across reboots. Considering the impact of missing ramoops for debugging, set MEDIATEK_DRAM_SCRAMBLE to default n to disable this feature in production FW image. BUG=b:269049451,b:278478563 TEST=emerge-geralt coreboot and confirm CONFIG_MEDIATEK_DRAM_SCRAMBLE=n Signed-off-by: Yidi Lin <yidilin@chromium.org> Change-Id: I109634d811a928e3e6f7f56e706a5b61a52a21ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/75562 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-12soc/mediatek/mt8195: Fix typo for SPIM2_MIYidi Lin
Fix a typo in an enum type name, "PIM2_MI" -> "SPIM2_MI". TEST=emerge-cherry coreboot Signed-off-by: Yidi Lin <yidilin@chromium.org> Change-Id: Ib43a044dc69a93ad1dcaa5e65c66a82046a40777 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2023-06-06mb/google/geralt: Fix MIPI panel power on/off sequenceRuihai Zhou
Based on the power sequence of the panel [1], the power on T2 sequence VSP to VSN should be larger than 1ms, and the power off T2 sequence VSP to VSN should be larger than 0ms. We modify the power sequence to meet the datasheet requirement. [1] B5 TV110C9M-LL0 Product Specification Rev.P0 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I4ccb5be04062a0516f84a054ff3f40afbf5279be Reviewed-on: https://review.coreboot.org/c/coreboot/+/75512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-06-01soc/mediatek/common: Add support for power supply TPS65132SRuihai Zhou
The TPS65132S is designed to supply positive/negative driven application. It communicates through standard I2C compatible interface, and it intergrates a EEPROM whose contents will be loaded into the register at startup. Since TPS65132S is used in staryu and geralt projects, we move the implementation to mediatek/common. The datasheet: TPS65132-Single-Inductor-Dual-Output-Power-Supply.pdf BUG=b:282902297 TEST=boot starmie to firmware screen Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: Iad2c9bdea5824455efcef18b44876111061cfa1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75488 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-26treewide: Remove 'extern' from functions declarationElyes Haouas
"extern" is automatically implied with function declaration. Change-Id: Ic40218acab5a009621b6882faacfcac800aaf0b9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71890 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-05-13soc/mediatek/mt8195/apusys_devapc.c: Fix unsigned comparisonArthur Heymans
Clang warns about unsigned comparison below 0. Use the enum value itself to fix this warning. Change-Id: I12fccff2fb7d43fd4582afd518a7eab632908a5f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74553 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-12soc/mediatek/mt8183: Fix set but unused variablesArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I1c995d942fa25a9268fbf716034335937df57714 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75036 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-04-24soc/mediatek/mt8183: Fix set but unused variableArthur Heymans
This fixes a clang warning. Change-Id: I017ed8601e6ec4c66487e9a6f31e93251515e686 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-04-24soc/mediatek/dptx.c: Remove set but unused variablesArthur Heymans
This fixes clang warning about set but unused variables. Change-Id: I3a3345e33380862d6939b61485f6d1eefa3d1815 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74547 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
2023-04-14soc/mediatek: Add assert for regulator VRF12Cong Yang
Add assert for MT6366_VRF12, define a constant macro for 1200000. BUG=none TEST=build board starmie with mt8186. Change-Id: I6d6a969ae993afcda0596a19928e8f98f343d589 Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74394 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-04-14soc/mediatek: Add support for regulator VIO18Cong Yang
To provide power to MIPI panel STA_HIMAX83102_J02, add support for regulator VIO18. BUG=b:272425116 TEST=test firmware display pass for STA_HIMAX83102_J02 on Starmie. Change-Id: I3c3aa105e648b87fc39f881d762002f67b4422b5 Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74341 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
2023-04-10soc/mediatek/mt8188: Set pin drive strength to 8mA for NORJason Chen
Set NOR pin drive to 8mA to comply with HW requirement. This implementation is according to chapter 5.8 and 5.19 in MT8188 Functional Specification. BUG=b:270911452 TEST=boot with following logs [DEBUG] mtk_snfc_init: got pin drive: 0x3 [DEBUG] mtk_snfc_init: got pin drive: 0x3 [DEBUG] mtk_snfc_init: got pin drive: 0x3 [DEBUG] mtk_snfc_init: got pin drive: 0x3 Change-Id: If8344449f5b34cefcaaee6936e94f7f669c7148b Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74064 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10soc/mediatek/mt8188: Add GPIO driving functionsJason Chen
Add GPIO driving functions to adjust pin driving. This implementation is according to chapter 5.2 in MT8188 Functional Specification. BUG=b:270911452 TEST=build pass Change-Id: I87cb8dc00c90fd5b3c0b8bdf5acb92b6f7393a73 Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74063 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10soc/mediatek/mt8186: Move GPIO driving-related functions to commonJason Chen
Move GPIO driving-related functions to common for code reuse. BUG=b:270911452 TEST=build pass Change-Id: I234a2b7ef5075313144a930332bed10ffec00c6c Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74068 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10soc/mediatek/mt8186: Reduce GPIO code size in bootblockJason Chen
Create a new GPIO driving info table that contains only the pins used in the bootblock. The GPIO driving info table is downsized from 1480 bytes to 24 bytes. BUG=b:270911452 TEST=build pass Change-Id: I24775ba93cd74ae401747c2f5a26bbf1c8f6ac0a Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74062 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10soc/mediatek/mt8188: Reduce lastbus configuration size by 1280 bytesYidi Lin
Original lastbus configuration consumes constant memory size by allocating 16 and 8 members arrays and the utilization is bad. Refactor the lastbus structs to save memory usage. BRANCH=none BUG=none TEST=bootblock.raw.bin size is reduced from 60328 bytes to 59048 bytes. Change-Id: I07ff9ff7c75f03219e1792b92b62814293ef43fe Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74061 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15soc/mediatek/mt8186: Shut down PMIC on power key long pressSen Chu
Currently on power key long press, PMIC will be reset. It would cause an unwanted reset pulse in the power-off sequence. To match expected sequence, change PMIC behavior to "force shutdown". BUG=b:271771606 TEST=long-pressing power key doesn't trigger PMIC_AP_RST_L pulse BRANCH=corsola Change-Id: I9ab35d82e57f43bac99fa8bd7bb69fcf52250311 Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Signed-off-by: jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73705 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-15soc/mediatek/mt8188: Shut down PMIC on power key long pressSen Chu
Currently on power key long press, PMIC will be reset. It would cause an unwanted reset pulse in the power-off sequence. To match expected sequence, change PMIC behavior to "force shutdown". BUG=b:271771606 TEST=long-pressing power key doesn't trigger PMIC_AP_RST_L pulse Change-Id: I1626892fd582dfab8fe1c1ede1da00549bc97142 Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Signed-off-by: jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73704 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-10soc/mediatek/mt8188: Enable lastbus debug hardwareot_zhenguo.li
Lastbus is a bus debug tool. When the bus hangs, the bus transmission information before resetting will be recorded. The watchdog cannot clear it and it will be printed out for bus hanging analysis. There are two versions for lastbus: Version 1 for MT8186, and version 2 for MT8188. BUG=b:263753374 TEST=build pass. Change-Id: Ibaf510481d1941376bd8da0168ef17c99a0fb9a2 Signed-off-by: ot_zhenguo.li <ot_zhenguo.li@mediatek.corp-partner.google.com> Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73624 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-03-05mb/google/geralt: Add MAX98390 support for GeraltTrevor Wu
Add a config "USE_MAX98390" to enable MAX98390 support. MAX98390 is an I2S smart amplifier used in Geralt. It is also the default speaker for Geralt reference board. BUG=b:250459803 BRANCH=none TEST=Verify beep function through CLI in depthcharge successfully. Change-Id: I814f440cc5ac2a13404d01fb3baafeec092b1e74 Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73412 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-03-05soc/mediatek/mt8188: Add bus protection for audio/video mtcmosgarmin chang
Bus protection is a HW mechanism to avoid bus hang and incomplete bus transactions. Bus protection HW must be enabled while the receiver of the transaction is not able to respond. BUG=b:264204465 TEST=build pass Change-Id: I14aa63c4934073a14552cef64f40657d0197bbe1 Signed-off-by: garmin chang <garmin.chang@mediatek.corp-partner.google.com> Signed-off-by: jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73375 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-02soc/mediatek: Add config to control DRAM scrambleXi Chen
The DRAM scramble feature enhances DRAM data protection. When it's enabled, the written DRAM data will be scrambled and hence can prevent the data from being hacked. This feature would make debugging more difficult (for example ramoops would be lost after reset). Therefore, add a new config to allow enabling or disabling the feature from coreboot, without having to maintain two versions of the DRAM calibration blob. BUG=b:269049451 TEST=build pass and check scramble enable or disable successfully Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: Ib4279bc1cc960fae9c9f5da39f4448a5627288d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-23soc/mediatek: Add "DRAM" to Kconfig MEDIATEK_BLOB_FAST_INIT nameYu-Ping Wu
In the current Kconfig option MEDIATEK_BLOB_FAST_INIT, the meaning of "BLOB" is unclear. Add "DRAM" to the name. BUG=b:204226005 TEST=./util/abuild/abuild -t GOOGLE_STEELIX -x Change-Id: Ida7bda770f1d1a40cae205b08c8cb22f2329e49f Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73155 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-22soc/mediatek/mt8188: Fix audio sampling rateJohnson Wang
The current clock register definition is wrong, which results in wrong audio sampling rate. Fix it by adjusting the POSTDIV registers of APLL1-APLL5. TEST=build pass BUG=b:250459803, b:250464574 Change-Id: I7a627169593f41906856777d738c6b13ff72d5a0 Signed-off-by: Johnson Wang <johnson.wang@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73134 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-22soc/mediatek/mt8188: Fix USB2 detection issueShaocheng Wang
MT8188 supports port0/port1 download. The hardware needs a trapping pin to select the port to use. When port1 is selected, the phy of port1 will be switched to port0. That is, port1 connector will be the physical line of port0. Since port0 phy isn't initialized in coreboot, switch back to port1 phy. BUG=b:269059211 TEST=can detect USB2 devices in depthcharge. Change-Id: Ic97d0bd9d0233883196b2e73ac2a22cd8ea9466b Signed-off-by: Shaocheng Wang <shaocheng.wang@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-02-09mb/google/geralt: Add power-on sequence for BOE_TV110C9M_LL0Rex-BC Chen
For Geralt, we use BOE_TV110C9M_LL0 as MIPI firmware display, so add the power-on sequence for BOE_TV110C9M_LL0. BUG=b:244208960 TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt. Change-Id: I3ef0b2e26d8cc0dc35c2985363ee4c3557dac8a9 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72749 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 20:22:40 +0000