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2020-05-20soc/mediatek/mt8183: Set CA and DQ vref range to correct valueHuayang Duan
The CA vref should alway select range[1]. But in fast calibration flow, we missed the range selection and caused the CA vref to use the range[0] value. The DQ vref should select correct range that corresponds to current frequency, that is for 1600Mbps, 2400Mbps to select range[1], for 3200Mbps and 3600Mbps to select range[0]. Refer to the 'JESD209-4 - Low Power Double Data Rate 4X(LPDDR4X).pdf', used MR12 to set Vref(CA) levels, used MR14 to set VREF(DQ) levels. MR12 range[0] values from 15.0% to 44.9%, range[1] values from 32.9% to 62.9%, MR14 range[0] and range[1] values same as MR12. BUG=b:153614919 BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: Ie7680b1bf0c29c946d18e3b27626ce6f31c4216b Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40525 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18soc/mediatek: dsi: adjust hfp_byte and hbp_byte if too smallPaul Ma
If panel has too small hfp or hbp, hfp_byte or hbp_byte may become very small value or negative value. When very small value or negative value is used, the panel will be scrolling or distorted. This patch adjusts their values so that they are greater than the minimum value and keep total of them unchanged. DSI transfer HBP or HFP, There are some extra packet. ex. packet header(4byte) and eof(2byte) and (next)hs packet header(4 byte). the hfp_byte = HFP * BPP - packet header(4byte) and eof(2byte) and (next)hs packet header(4 byte). So the min hfp_byte is 2 when HFP = 4. This is equivalent to the Linux kernel DSI change in: https://chromium-review.googlesource.com/c/chromiumos/third_party/ kernel/+/2186872 BUG=b:144824303 BRANCH=kukui TEST=boot damu board with panel CMN N120ACA-EA1 (12" panel and its hbp only 6), the panel can display without scrolling or distortions. Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> Change-Id: I608c01d41ae93c8d5094647bbf3e0ae4a23d814c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41163 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13src/mainboard: Remove unused 'include <stdlib.h>'Elyes HAOUAS
Found using following commande: diff <(git grep -l '#include <stdlib.h>' -- src/) <(git grep -l ' memalign\|malloc\|free' -- src/) |grep -v vendorcode |grep '<' Change-Id: Ib2ee840a10de5c10d57aa7a75b805ef69dc8da84 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41241 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13src: Remove unused '#include <stddef.h>'Elyes HAOUAS
Unused includes found using following commande: diff <(git grep -l '#include <stddef.h>' -- src/) <(git grep -l 'size_t\|ssize_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\ |MAYBE_STATIC_NONZERO\|MAYBE_STATIC_BSS\|zeroptr' -- src/)|grep '<' |grep -v vendor |grep -vF '.h' Change-Id: Ic54b1db995fe7c61b416fa5e1c4022238e4a6ad5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41150 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13soc/mediatek: improve ca53 frequency change procedureWeiyi Lu
To change frequency, the SOC PLL team suggests procedure below: First, we need to enable the intermediate clock and switch the ca53 clock source to the intermediate clock. Second, disable the armpll_ll clock output. Third, raise armpll_ll frequency and enable the clock output. The last, switch the ca53 clock source back to armpll_ll and disable the intermediate clock. BUG=b:154451241 BRANCH=jacuzzi TEST=Boots correctly on Jacuzzi. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: Ib9556ba340da272fb62588f45851c93373cfa919 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41077 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-09src/: Replace GPL boilerplate with SPDX headersPatrick Georgi
Used commands: perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) Change-Id: Ia01908544f4b92a2e06ea621eca548e582728280 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41178 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
This replaces GPLv2-or-later and GPLv2-only long form text with the short SPDX identifiers. Commands used: perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-30Revert "soc/mediatek/mt8183: Force retraining memory if requested"Julius Werner
This reverts commit 285975dbba8c7f3bbb9f9950e79a30bb983d5123. Reason for revert: VB2_RECOVERY_TRAIN_AND_REBOOT was never meant to have any special effect on memory training behavior. It was just supposed to be a "reboot automatically after reaching kernel verification" recovery reason. On x86 devices this was used to prime the separate recovery MRC cache in the factory (make sure it is initialized before shipping). This isn't used on Kukui anyway, but in order to make sure nobody copies this code and keep the behavior consistent between platforms, let's remove it. Change-Id: I5df5e00526e90cb573131de3c8bac9f85f4e3a5f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40623 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-23rules.h: Rename ENV_VERSTAGE to ENV_SEPARATE_VERSTAGEJulius Werner
When CONFIG_SEPARATE_VERSTAGE=n, all verstage code gets linked into the appropriate calling stage (bootblock or romstage). This means that ENV_VERSTAGE is actually 0, and instead ENV_BOOTBLOCK or ENV_ROMSTAGE are 1. This keeps tripping up people who are just trying to write a simple "are we in verstage (i.e. wherever the vboot init logic runs)" check, e.g. for TPM init functions which may run in "verstage" or ramstage depending on whether vboot is enabled. Those checks will not work as intended for CONFIG_SEPARATE_VERSTAGE=n. This patch renames ENV_VERSTAGE to ENV_SEPARATE_VERSTAGE to try to clarify that this macro can really only be used to check whether code is running in a *separate* verstage, and clue people in that they may need to cover the linked-in verstage case as well. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I2ff3a3c3513b3db44b3cff3d93398330cd3632ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/40582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-05soc/mediatek: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I7c3c75eaf2d7a64e7d833541bcf168b93921a142 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-31security/vboot: Decouple measured boot from verified bootBill XIE
Currently, those who want to use measured boot implemented within vboot should enable verified boot first, along with sections such as GBB and RW slots defined with manually written fmd files, even if they do not actually want to verify anything. As discussed in CB:34977, measured boot should be decoupled from verified boot and make them two fully independent options. Crypto routines necessary for measurement could be reused, and TPM and CRTM init should be done somewhere other than vboot_logic_executed() if verified boot is not enabled. In this revision, only TCPA log is initialized during bootblock. Before TPM gets set up, digests are not measured into tpm immediately, but cached in TCPA log, and measured into determined PCRs right after TPM is up. This change allows those who do not want to use the verified boot scheme implemented by vboot as well as its requirement of a more complex partition scheme designed for chromeos to make use of the measured boot functionality implemented within vboot library to measure the boot process. TODO: Measure MRC Cache somewhere, as MRC Cache has never resided in CBFS any more, so it cannot be covered by tspi_measure_cbfs_hook(). Change-Id: I1fb376b4a8b98baffaee4d574937797bba1f8aee Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-03-18soc/mediatek/mt8183: Fix wrong setting of DRS configHuayang Duan
Update setting of DRS config. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: Id38fc224b54c3947af8bbc5c1a4a8d70eb53d5fb Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-03-18soc/mediatek/mt8183: Improve the AC timing of DRAMCHuayang Duan
Set more AC timing items to make the system more stable. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: Ibd003582a3ffab1ae91f6378651c2c9e585c4676 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-03-12vboot: remove extraneous vboot_recovery_mode_memory_retrainJoel Kitching
Just call get_recovery_mode_retrain_switch() directly. BUG=b:124141368 TEST=make clean && make test-abuild BRANCH=none Change-Id: Icb88d6862db1782e0218276984e527638b21fd3a Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-06soc/mediatek/mt8183: Improve the DRAMC runtime config flowHuayang Duan
Move channel loop at the top level to deduplicate the logic. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: Iea623d1bd1f7d736e81f66f191a1bf8476d30404 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-03-06soc/mediatek/mt8183: Do TX tracking for DRAM DVFS featureHuayang Duan
The TX window will offset to edge during DVFS switch, which may cause TX data transmission error and random kernel crash. Therefore, use the standard dqsosc (DQS Oscillator) for TX window tracking. BUG=b:142358843 BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: Idcf9213a488e795df3faf64b03588cfe55cb2f81 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-03-06soc/mediatek/mt8183: Correct EMI bandwidth threshold for DVFS switchHuayang Duan
Because eMCP and discrete DDR devices have different DVFS tables, their EMI bandwidth thresholds should also be different. When the EMI total bandwidth reaches the threshold, the system will notify DVFS module to perform DVFS switch for system performance in low power states. This patch increases the threshold from 0xa to 0xd for eMCP DDR devices so that DVFS switch will be less likely to happen. The register table of EMI_BWCT0 is incorrect in the datasheet. According to the hardware design, BW_2ND_INT_BW_THR should be in bits [30:24] instead of [22:16]. However, the logic in DRAM driver is correct, aligned with the hardware design, so we don't need to correct it. BRANCH=kukui BUG=b:142358843 TEST=bootup pass Change-Id: I82c3c70bcd90df3fdd613c0353aba0f176bc82bc Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39034 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-26treewide: capitalize 'USB'Elyes HAOUAS
Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39100 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-25soc/mediatek/mt8183: Fix programming error of DRAMC settingHuayang Duan
1. The ac timing of 2400Mbps should use diff params with 1600Mbps. 2. Fix the typo error of save shuffle function for DVFS. BRANCH=kukui BUG=none TEST=emerge-kukui coreboot Change-Id: I5edac32938def50836f386426e7deb652b80d42d Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-02-25soc/mediatek: Fix typos in commentsElyes HAOUAS
Also add missing whitespace. Change-Id: I3361122d5232072e68d018e84219a262acf34001 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2020-02-17soc/mediatek: dsi: Correct bits_per_pixel for MIPI_DSI_FMT_RGB666Yu-Ping Wu
The number of bits per pixel for MIPI_DSI_FMT_RGB666 should be 24 instead of 18. BRANCH=none BUG=none TEST=none Change-Id: I9574502b2dec4b5a042df3886922ddd8c755da1a Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jitao Shi <jitao.shi@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-02-17soc/mediatek: dsi: reduce the hbp and hfp for phy timingJitao Shi
The extra data transfer in DSI, namely, lpx, hs_prepare, hs_zero, hs_exit and the sof/eof of DSI packets, will enlarge the line time, which causes the real frame on dsi bus to be lower than the one calculated by video timing. Therefore, hfp_byte is reduced by d_phy to compensate the increase in time by the extra data transfer. However, if hfp_byte is not large enough, the hsync period will be increased on DSI data, leading to display scrolling in firmware screen. To avoid this situation, this patch changes the DSI Tx driver to reduce both hfp_byte and hbp_byte, with the amount proportional to hfp and hbp, respectively. Refer to kernel's change in CL:1915442. Also rename 'phy_timing' to 'timing' to sync with kernel upstream. Since the phy timing initialization sequence has been corrected, the m value adjustment in the analogix driver can be removed. BUG=b:144824303 BRANCH=kukui TEST=emerge-jacuzzi coreboot TEST=Boots and sees firmware screen on krane and juniper TEST=No scrolling issue on juniper AUO and InnoLux panels Change-Id: I10a4d8a4fb41c309fa1917cf1cdf19dabed98227 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-02-17soc/mediatek: dsi: Increase pcw precisionYu-Ping Wu
When configuring MIPI DSI Tx, the value of pcw was calculated from data rate in MHz, leading to loss of precision. This patch changes to use data rate in Hz for the calculation so that the resulting value should be consistent with the one in kernel (CL:1786327). In addition, change the type of data rate to u32, and calculation of data rate from pixel clock is changed to use DIV_ROUND_UP for consistency with kernel (CL:1761843). Also remove unused variable txdiv. BRANCH=kukui BUG=b:149051882 TEST=emerge-jacuzzi coreboot TEST=No scrolling issue on Juniper AUO and InnoLux panels Change-Id: I23220d446833b956431006027bbc8cb20fc696a5 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38827 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-28drivers/spi/spi_flash: remove spi flash namesAaron Durbin
The names of each spi flash cause quite a bit of bloat in the text size of each stage/program. Remove the name entirely from spi flash in order to reduce overhead. In order to pack space as closely as possible the previous 32-bit id and mask were split into 2 16-bit ids and masks. On Chrome OS build of Aleena there's a savings of >2.21KiB in each of verstage, romstage, and ramstage. Change-Id: Ie98f7e1c7d116c5d7b4bf78605f62fee89dee0a5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-01-10soc/mediatek/mt8183: Restore vcore after DRAM calibrationHuayang Duan
DRAM calibration sets vcore to different voltages at different frequencies. After DRAM calibration, vcore should be restored to the default voltage, which is 800mV for both eMCP and discrete DDR devices. BRANCH=kukui BUG=b:146618163 TEST=bootup pass Change-Id: Ia87b4ac78a32dbd4c4ab52e84d307cb46525afa1 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2019-12-20soc/mediatek/mt8183: Use DDR clock to compute Tx delay cellHuayang Duan
The delay cell result should use DDR clock PLL rate for computation, and should not be divided by 2. This helps to improve DRAM stability. BUG=b:80501386,b:142358843 BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-12-20src: Replace min/max() with MIN/MAX()Elyes HAOUAS
Change-Id: I63b95144f2022685c60a1bd6de5af3c1f059992e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37828 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19soc/{amd,cavium,mediatek,sifive}: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: I83322e246fe81b97188be17a3fdda16d36df0678 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33688 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19src: Remove unneeded 'include <delay.h>'Elyes HAOUAS
Change-Id: Ibf91c35aa389a91116463616a778212bb386756e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34230 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-12soc/mediatek/mt8183: skip fast calibration for high frequency of TX RX windowHuayang Duan
For low frequency (e.g., 1600 or 2400 Mbps) we can do fast calibration for TX and RX window. However, for high frequency (e.g., 3200 or 3600 Mbps) a full calibration is needed. BUG=b:80501386,b:142358843 BRANCH=kukui TEST=Boots correctly on Kukui Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I00d563ece4cf91ef5e8e12b6cf7f777849375a24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36921 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-04Change all clrsetbits_leXX() to clrsetbitsXX()Julius Werner
This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-11-26soc/mediatek/mt8183: disable BBLPM of DCXO coreWeiyi Lu
When we only enable XO_SOC and mask most BBLPM requests, the BBLPM HW arbiter will have DCXO core to enter Baseband Low-Power Mode(BBLPM). Under BBLPM mode, inaccurate(about 1.5KHz offset) 26MHz clocks from crystal is provided and crystal voltage will drop from 1.8V to 0.7V or lower. In order to ensure the stability by always outputting an accuarate system clock when system is running. We should disable BBLPM when only XO_SOC enabled. BRANCH=kukui TEST=accurate 26MHz provided and correct crystal voltage swing Change-Id: Iea72a964507a19735cf92e3774cd8a94c06545b2 Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37136 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-18include: Make stdbool.h a separate fileJulius Werner
This patch moves the traditional POSIX stdbool.h definitions out from stdint.h into their own file. This helps for using these definitions in commonlib code which may be compiled in different environments. For coreboot everything should chain-include this stuff via types.h anyway so nothing should change. Change-Id: Ic8d52be80b64d8e9564f3aee8975cb25e4c187f5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-16soc/mediatek/mt8183: Get more space for PreRAM memconsoleHung-Te Lin
Leave more space for PreRAM memconsole especially for seeing complete logs when doing DRAM full calibration (that outputs in 200+k to UART): - Shrink Full-K mem space (the ELF blob today needs ~132K) - Move PRERAM_CBFS_CACHE to L2C since it's no used after DRAM is up - Shrink TIMESTAMP to 1k (all other non-MTK ARM SOCs use only 1k) - Incease PRERAM_CBMEM_CONSOLE to 63k-4 - Reordered few sections to align at better locations BUG=b:144542023 TEST=emerge-kukui coreboot chromeos-bootimage; boot and see logs Change-Id: I8696fb01653c0a581cf62e687dc523cb6fed9a32 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-14lib/fmap: Add optional pre-RAM cacheJulius Werner
This patch adds an optional pre-RAM cache for the FMAP which most platforms should be able to use, complementing the recently added post-RAM FMAP cache in CBMEM. vboot systems currently read the FMAP about half a dozen times from flash in verstage, which will all be coalesced into a single read with this patch. It will also help future vboot improvements since when FMAP reads become "free" vboot doesn't need to keep track of so much information separately. In order to make sure we have a single, well-defined point where the new cache is first initialized, eliminate the build-time hardcoding of the CBFS section offsets, so that all CBFS accesses explicitly read the FMAP. Add FMAP_CACHEs to all platforms that can afford it (other than the RISC-V things where I have no idea how they work), trying to take the space from things that look like they were oversized anyway (pre-RAM consoles and CBFS caches). Change-Id: I2820436776ef620bdc4481b5cd4b6957764248ea Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Joel Kitching <kitching@google.com>
2019-11-11soc/mediatek: Add missing '#include <console/console.h>'Elyes HAOUAS
Change-Id: I2e79ff3352fe974a070b7b3f5e4b5570ed2b294c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-03arch/arm64: Pass cbmem_top to ramstage via calling argumentArthur Heymans
This solution is very generic and can in principle be implemented on all arch/soc. Currently the old infrastructure to pass on information from romstage to ramstage is left in place and will be removed in a follow-up commit. Nvidia Tegra will be handled in a separate patch because it has a custom ramstage entry. Instead trying to figure out which files can be removed from stages and which cbmem_top implementations need with preprocessor, rename all cbmem_top implementation to cbmem_top_romstage. Mechanisms set in place to pass on information from rom- to ram-stage will be replaced in a followup commit. Change-Id: I86cdc5c2fac76797732a3a3398f50c4d1ff6647a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-01lib/cbmem_top: Add a common cbmem_top implementationArthur Heymans
This adds a common cbmem_top implementation to all coreboot target. In romstage a static variable will be used to cache the result of cbmem_top_romstage. In ramstage if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is set a global variable needs to be populated by the stage entry with the value passed via the calling arguments. if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is not set the same implementation as will be used as in romstage. Change-Id: Ie767542ee25483acc9a56785ce20a885e9a63098 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-01soc/{mediatek,sifive}: Remove unused 'include <arch/barrier.h>'Elyes HAOUAS
Change-Id: Ia15824effc8f846ff1143abe698c5a0546df7868 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36489 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-31soc/mediatek/mt8183: Disable DRAM DVFS in recovery modeYu-Ping Wu
Currently full calibration with DVFS (which implies tripling memory training time for multiple frequencies) will be run in recovery mode, which takes up to 30 seconds with serial console enabled. However, in recovery mode the system should be running only the recovery programs with minimal services. DVFS should be not needed. In order to improve stability and system boot time, we want to disable DVFS training in recovery mode. BRANCH=kukui BUG=b:142358843 TEST=emerge-kukui coreboot Change-Id: I4f1b1b020eba9bfce21655169bcb31b98d54b010 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36456 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-28soc/mediatek/mt8183: Pass MR values as function argumentsYu-Ping Wu
To make data flow more explicit, global variables 'MR01Value' and 'MR13Value' are replaced with local variables, which are passed as function arguments. BRANCH=kukui BUG=none TEST=1. emerge-kukui coreboot 2. Fast calibration succeeded Change-Id: Id21483092c86c3ae7dbb1173a2b943defe41a379 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-24soc/mediatek/mt8183: Add udelay after setting voltagesYu-Ping Wu
The SOC DRAM team suggested to delay at least 1us after setting new voltage in PMIC wrapper so the new value can be effective. BRANCH=kukui BUG=b:142358843 TEST=emerge-kukui coreboot Change-Id: I19d236769c3c0c87513ea4a0a3f64b83e3a844c2 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36254 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24soc/mediatek/mt8183: Improve DRAM calibration logsYu-Ping Wu
- Add macro dramc_err. - Some log levels are changed. - Some messages are improved for readability. BRANCH=kukui BUG=none TEST=emerge-kukui coreboot Change-Id: If0c9e61c0f81a06e9264784f682a6c373574e06b Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35767 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24soc/mediatek/mt8183: Correct continuation line indentYu-Ping Wu
BRANCH=kukui BUG=none TEST=emerge-kukui coreboot Change-Id: I9d01d24d3494f2eb28cfb411e13adf3b6717d191 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36285 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24soc/mediatek/mt8183: Force retraining memory if requestedHung-Te Lin
To allow retraining memory without hotkey (for example in manufacturing process), we want to enforce re-training when the recovery reason is set to VB2_RECOVERY_TRAIN_AND_REBOOT (which can be done by running "crossystem recovery_request=0xc4"). The special reason was created for X86 MRC cache, for ensuring RO calibration data is filled (the underlying implementation was in vboot, not coreboot); and on MT8183 we have only RW calibration, but it seems totally fine to extend that for RW. BRANCH=kukui BUG=None TEST=boots; crossystem recovery_reason=0xc4; reboot Change-Id: Iaa5275f0e0eb90f6ab3a7d4579977a6655d59bd9 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-23soc/mediatek/mt8183: Fix incorrect usage of sizeofYu-Ping Wu
BRANCH=kukui BUG=none TEST=emerge-kukui coreboot Change-Id: Ic2f6bfaf42aed642e1d7d6aba5db373944eb8ef6 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-10-23soc/mediatek/mt8183: add dphy reset after setting lanes numberJitao Shi
Add dphy reset after setting lanes number to avoid dphy fifo error. BUG=b:139150763 BRANCH=kukui TEST=Boots correctly on kukui Change-Id: Ib83576f3700ef98c90f0b4dd101dcaa237d562f9 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-23soc/mediatek/mt8183: fine tune the phy timingJitao Shi
To fix MIPI D-PHY test failure, the hs-prepare should be less than LimitMin from spec, and we have to enlarge TEOT margin. BUG=b:138344447 BRANCH=kukui TEST=Boots correctly on kukui Change-Id: If91e7a546866299f02432be27fe778be5d7bdc5f Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-21src/{device,drivers,mb,nb,soc,sb}: Remove unused 'include <console/console.h>'Elyes HAOUAS
Change-Id: I0c965e598e260ff8129aa07fb9fc5bf6e784e1d8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-21soc/mediatek/mt8183: Force DRAM retraining if hotkey pressedYu-Ping Wu
Similar to MRC cache on x86 platforms, when a hotkey is pressed during boot, the calibration data cache saved in the flash will be cleared, consequently triggering DRAM retraining (full calibration) in the next boot. BRANCH=kukui BUG=b:139099592 TEST=emerge-kukui coreboot Change-Id: I2f9225f359e1fe5733e8e1c48b396aaeeb9a58ab Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-21soc/mediatek/mt8183: Skip fast calibration in recovery modeYu-Ping Wu
SoC DRAM team suggested always running full calibration mode in recovery mode because it is possible to get unstable memory even if the complex memory test has been passed. Since the recovery mode runs from RO and we only have training data cache for RW, the trained calibration data can't be saved since RO and RW may be running different firmware. Also revised few message to make it more clear for what calibration mode (fast, full, or partial) has been executed. BRANCH=kukui BUG=b:139099592 TEST=emerge-kukui coreboot Change-Id: I29e0df71dc3357462e15ce8fc2ba02f21b54ed33 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-20src: Remove unused 'include <string.h>'Elyes HAOUAS
Change-Id: I2a94c3b6282e9915fd2b8136b124740c8a7b774c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-18soc/mediatek/mt8183: Compress calibration blob with LZ4Hung-Te Lin
The DRAM calibration blob can be compressed using pre-RAM algorithm (currently LZ4), which will save ~12ms in boot time. On Kodama, boot time difference: Before: 1,082,711 After: 1,070,309 BUG=b:139099592,b:117953502 TEST=build and boot, cbfstool coreboot.rom print -v (see dram compressed) BRANCH=kukui Change-Id: Ic3bd49d67ee6f80a0e4d8f6945744642611edf64 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-18soc/mediatek/mt8183: Pass impedance data as a function argumentYu-Ping Wu
To make data flow more explicit, global variable 'impedance' is replaced with a local variable, which is passed as a function argument. BUG=none BRANCH=kukui TEST=Krane boots correctly Change-Id: I0f6dacc33fda013a3476a10d9899821b7297e770 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-18soc/mediatek/mt8183: Run calibration with multiple frequencies for DVFS switchHuayang Duan
The patch adds config MT8183_DRAM_DVFS to enable DRAM calibration with multiple frequencies to support DVFS switch. BUG=b:80501386,b:142358843 BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I97c8e513dc3815a2d62b2904a246a1d8567704a4 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-18soc/mediatek/mt8183: Adjust DRAM voltages for each DRAM frequencyHuayang Duan
This patch supports voltage adjustment for each DRAM frequency, which is neccesary to support DVFS switch. BUG=b:80501386,b:142358843 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-18soc/mediatek/mt8183: Allow modifying vddq voltageHsin-Hsiung Wang
DRAM DVFS needs to be calibrated with different vddq voltages to get correct parameters. A new API is added to allow changing vddq voltage. BUG=b:80501386 BRANCH=none TEST=measure vddq voltage with multimeter Change-Id: I5f0d82596a1709bf0d37885f257646133f18f210 Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35147 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18soc/mediatek/mt8183: Allow modifying vdram1 voltageHsin-Hsiung Wang
DRAM DVFS needs to be calibrated with different vdram1 voltages to get correct parameters. A new API is added to allow changing vdram1 voltage. BUG=b:80501386 BRANCH=none TEST=measure vdram1 voltage with multimeter Change-Id: Ia15ab3a2e1668e5b4873d317b57a38ebee037709 Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33186 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18soc/mediatek/mt8183: Share console for calibration blob outputHung-Te Lin
Most coreboot debug messages are sent to UART and cbmem console, and we also want to collect DRAM calibration module output, especially for cbmem console (so we can see the logs after kernel is up). Instead of sharing whole cbmem/cbtable/cbmemconsole implementations, we want to simplify that by a simple function pointer so output can be preserved by do_putchar, which internally sends data to all registered consoles (usually cbmem console and UART). BUG=b:139099592 TEST=make; boots properly for full-k, with and without serial console. BRANCH=kukui Change-Id: I1cf16711caf3831e99e17b522b86694524425116 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36056 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-17soc/mediatek/mt8183: Verify checksum of cached calibration dataYu-Ping Wu
The checksum is stored in the header of calibration data and saved to SPI flash. After reading the data from flash, checksum is used to verify the integrity of the calibration parameters. BUG=b:139099592 BRANCH=kukui TEST=Calibration data successfully loaded from flash Change-Id: Ie4a0688ed6e560d4c0c6b316f44e52fd10d71a9d Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-17soc/mediatek/mt8183: Remove unnecessary DRAM register settingsYu-Ping Wu
In broadcast mode we only need to set registers for channel 0 instead of all channels. BUG=none BRANCH=kukui TEST=emerge-kukui coreboot Change-Id: I22a4b69fd40d1978fa7b12e8edaba00ce5d7787d Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-17soc/mediatek/mt8183: Fix DDR phy config numberYu-Ping Wu
Some typos are fixed to make DVFS switch work. BUG=b:142358843 BRANCH=kukui TEST=emerge-kukui coreboot Change-Id: I064d4a2c46187ac5780352da742bd56e82c22c14 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-17soc/mediatek/mt8183: Refactor DRAM init by bit fields APIHung-Te Lin
Replace the magic clrsetbits_le32, read32, write32 by SET_BITFIELDS and other bit field helpers. Change-Id: I327297dd10718fbef7275fe95c95d00d3ab6ac84 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35471 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-17soc/mediatek/mt8183: Improve code formattingYu-Ping Wu
This patch contains some minor changes including: - Use lowercase hex literals - Combine short lines - Remove unnecessary curly braces - Simplify struct initialization - Leverage macro _SELPH_DQS_BITS - Ensure whitespaces around binary operators - Remove extra whitespaces after commas - Change log level and remove unnecessary debug logs BUG=none BRANCH=kukui TEST=emerge-kukui coreboot Change-Id: I33616e6142325920c2fd7e6dc1dc88eb29c5cf34 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-17soc/mediatek/mt8183: Handle memory test failureYu-Ping Wu
If DRAM calibration fails or mem test fails using the cached calibration results stored in flash, rerun DRAM full calibration. If partial calibration fails or the mem test following it fails, hang forever. Partial calibration acts as a fallback approach in case of full calibration failure. Therefore, if it fails, there would be no other ways to initialize DRAM. Instead of falling into reboot loop and draining out of battery, it is better to just hang so that the end user may notice that and send to RMA. BUG=b:80501386,b:139099592 BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I8e1d4f5bc7b45f45a8bfef74e86ec0ff6a556af4 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35481 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-09soc/mediatek/mt8183: Change argument type of mt_set_emiYu-Ping Wu
Since struct dramc_param has been defined, we can pass the struct directly from mt_mem_init(). BUG=b:139099592 BRANCH=none TEST=emerge-kukui coreboot Change-Id: If7333fb579eff76dd9d1c2bf6fdfe7eccb22050f Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35846 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-09soc/mediatek/mt8183: Run DRAM full calibrationHuayang Duan
Load the calibration params from flash first and check the correctness of the params. If the params have correct format, perform DRAM fast calibration with these params to reduce bootup time. Otherwise, load the DRAM blob and perform DRAM full calibration. Bootup time of DRAM partial calibration: - 1,349,385 usecs with low frequency - 924,698 usecs with middle frequency - 1,270,089 usecs with high frequency 3,544,172 usecs in total. Bootup time of DRAM fast calibration: - 216,663 usecs with low frequency - 328,220 usecs with middle frequency - 322,612 usecs with high frequency 867,495 usecs in total. BUG=b:139099592 BRANCH=none TEST=emerge-kukui coreboot Change-Id: I8de29b14b1fb24b3b4f351c855c5c4d8f350cc34 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-09soc/mediatek/mt8183: Use cached calibration result for faster bootupHuayang Duan
Load calibration params from flash. If the format of the params is correct, use these calibration params for fast calibration to reduce the bootup time. Bootup time of DRAM partial calibration: - 1,349,385 usecs with low frequency - 924,698 usecs with middle frequency - 1,270,089 usecs with high frequency 3,544,172 usecs in total. Bootup time of DRAM fast calibration: - 216,663 usecs with low frequency - 328,220 usecs with middle frequency - 322,612 usecs with high frequency 867,495 usecs in total. BUG=b:139099592 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I9ef4265dd369a1c276bb02294696556df927e7bc Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35164 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-09soc/mediatek/mt8183: Add the shared 'dramc_param' moduleYu-Ping Wu
The dramc_param module simplifies the communication between coreboot and MTK DRAM full calibration blob, and is shared by both implementations to ensure the same format of parameters. BUG=b:139099592 BRANCH=none TEST=emerge-kukui coreboot Change-Id: I4cfd634da1855a76706aab0b050197251e2ed4dd Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-09soc/mediatek/mt8183: Simplify usage of dramc_engine2_endYu-Ping Wu
Since we always write to &ch[chn].ao.dummy_rd after calling dramc_engine2_end(), this write could be merged into dramc_engine2_end() to simplify code. BUG=none BRANCH=none TEST=emerge-kukui coreboot Change-Id: Ibb4bd5ed016118811ad2097098417c19f00f4263 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35749 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02mediatek/mt8183: Rename fields of struct sdram_paramsYu-Ping Wu
Two fields of struct sdram_params are renamed for future CL of DRAM full calibration. Field 'impedance' is also removed. BUG=none BRANCH=none TEST=emerge-kukui coreboot Change-Id: I2f9673fd5ea2e62ee971f0d81bdd12aaf565e31c Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35738 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-01mediatek/mt8183: Allow modifying vcore voltageHsin-Hsiung Wang
Because vcore is the power of ddrphy in the soc, DRAM DVFS needs to be calibrated with different vcore voltages to get correct parameters. A new API is added to allow changing vcore voltage. BUG=b:80501386 BRANCH=none TEST=measure vcore voltage with multimeter Change-Id: Ic43d5efe7e597121775dc853a3e2a08ebc59657d Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33391 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30mediatek/mt8183: Init SPM driverDawei Chien
To support mt8183 power saving during suspend to RAM, this patch loads SPM firmware to support SPM suspend. SPM needs its own firmware to do these power saving in the right timing under correct conditions. After linux PM suspends, SPM is able to turn off power for the last CPU and do more power saving for the SoC such as DRAM self-refresh mode and turning off 26M crystal. BUG=none BRANCH=none TEST=suspend/resume passes for LPDDR4 3200 Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien <dawei.chien@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-24mediatek/mt8183: Use different DRAM frequencies for eMCP DDRHuayang Duan
Devices using eMCP may run at a high DRAM frequency (e.g., 3600Mbps) while those with discrete DRAM can only run at 3200Mbps. This patch enables 3600Mbps for eMCP DDR for better system performance. BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test passes on Kukui Change-Id: Iab6a9c2c390feeb9497b051a255b29566909e656 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-20mediatek/mt8183: Support more DRAM frequency bootupHuayang Duan
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps. BUG=b:80501386 BRANCH=none TEST=Memory test passes on eMCP platform Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-20mediatek/mt8183: Implement the dramc init settingHuayang Duan
This patch implements the dram init setting by replacing the hard-coded init sequence with a series of functions to support calibration for more frequencies. These functions are modified from MediaTek's internal DRAM full calibration source code. BUG=b:80501386 BRANCH=none TEST=1. Kukui boots correctly 2. Stress test (/usr/sbin/memtester 500M) passes on Kukui Change-Id: I756ad37e78cd1384ee0eb97e5e18c5461d73bc7b Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-19cpu,mb,soc: Init missing lb_serial struct fieldsJacob Garber
Initialize the input_hertz and uart_pci_addr fields of the lb_serial struct to prevent later undefined reads in lb_add_serial(). This was done for exynos5420 in commit ff94e00362 (soc/samsung/exynos5420/uart.c: Init new serial struct variables), and this patch finishes the rest. Note that not all of the drivers can have the UART PCI address configured at build time, so a follow-up patch will be needed to correct those ones. Change-Id: I733bc8185e2f2d28a9823495b53d6b09dce4deb1 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1354778 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34548 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-16mediatek/mt8183: Add soc ARM Trusted Firmware supportkenny liang
Set BL31 platform to mt8183 to link with ARM Trusted Firmware. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui with more patches in ATF. Change-Id: Ia988d2b4ed646027c04c7c6ff0e50ed7a0b14da3 Signed-off-by: kenny liang <kenny.liang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-09-14arm64: Uprev Arm TF and adjust to BL31 parameter changesJulius Werner
This patch uprevs the Arm Trusted Firmware submodule to the new upstream master (commit 42cdeb930). Arm Trusted Firmware unified a bunch of stuff related to BL31 handoff parameters across platforms which involved changing a few names around. This patch syncs coreboot back up with that. They also made header changes that now allow us to directly include all the headers we need (in a safer and cleaner way than before), so we can get rid of some structure definitions that were duplicated. Since the version of entry point info parameters we have been using has been deprecated in Trusted Firmware, this patch switches to the new version 2 parameter format. NOTE: This may or may not stop Cavium from booting with the current pinned Trusted Firmware blob. Cavium maintainers are still evaluating whether to fix that later or drop the platform entirely. Tested on GOOGLE_KEVIN (rk3399). Change-Id: I0ed32bce5585ce191736f0ff2e5a94a9d2b2cc28 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-10mediatek/mt8183: Add new option for eMCP DDRHuayang Duan
Devices using eMCP may run at a high DRAM frequency (e.g., 3600Mbs) while those with discrete DRAM can only run at 3200Mbps. A new option MT8183_DRAM_EMCP is added to Kconfig for a mainboard to select, depending on whether it supports eMCP or not. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I9b73c8b512db5104896ea0d330d56e63eb50a44b Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-06soc/mediatek: Fix USB enumeration issueChangqi Hu
Some USB 3.0 devices fail to be enumerated after USB reset, and xhci port status register shows the device is disconnected. After measuring the USB signal, we found that the USB disconnect threshold was lower and that the disconnect event was triggered unexpectedly. USB designers suggest changing discth to 15. BUG=b:122047652 TEST=emerge-kukui coreboot chromeos-bootimage Change-Id: I0e8556035b49d693a42cbe1099a6882a1c0ed0d1 Signed-off-by: Changqi Hu <changqi.hu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-04mediatek/mt8183: postpone dcxo low power mode settingWeiyi Lu
Consider the association between modem[1] and DCXO, this patch is a fix for eb5e47d("mediatek/mt8183: update dcxo output buffer setting") [2] We should not disable XO_CEL and block the bblpm request when modem is still ON. For power-saving, we still could disable unused XO_CEL and mask request to disable unused power mode when modem is no longer be used. [1] https://review.coreboot.org/c/coreboot/+/32666 [2] https://review.coreboot.org/c/coreboot/+/32323 BRANCH=none TEST=Boots correctly on Krane. Change-Id: I047ebed615e874977ca211aafd52b5551c71b764 Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-02mediatek/mt8183: Remove unnecessary parenthesesYu-Ping Wu
Parentheses are unnecessary for conditions like '(a == b) || (c == d)'. Change-Id: I0c554bf1577b40286f7a51a8fc5804bdbb7c8bd1 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35142 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Huayang Duan <huayang.duan@mediatek.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-30arm64: Rename arm_tf.c/h to bl31.c/hJulius Werner
This patch renames arm_tf.c and arm_tf.h to bl31.c and bl31.h, respectively. That name is closer to the terminology used in most functions related to Trusted Firmware, and it removes the annoying auto-completion clash between arm64/arm_tf.c and arm64/armv8. Change-Id: I2741e2bce9d079b1025f82ecb3bb78a02fe39ed5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-21mediatek/mt8183: add scp voltage initializationHsin-Hsiung Wang
Add scp voltage initialization. BUG=b:135985700 BRANCH=none Test=Boots correctly on Kukui and scp can boot up normally Change-Id: I5afb60af3c14490e20f28f1c089cfca42ddf7fcf Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-21mediatek/mt8183: Enlarge PRERAM_CBFS_CACHE regionTristan Shieh
Enlarge PRERAM_CBFS_CACHE region from (16K - 4) to (48K - 4) bytes to decompress and load more data from CBFS in romstage. BUG=b:134351649 BRANCH=none TEST=emerge-kukui coreboot Change-Id: Idc23a67c886718e910ca3c50468e5793f19c8d66 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34896 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21mediatek/mt8183: Overlap decompressor, verstage and romstageTristan Shieh
Since SRAM space is too small to fit all needed features, enable VBOOT_RETURN_FROM_VERSTAGE and overlap decompressor, verstage and romstage to gain more space. BUG=b:134351649 BRANCH=none TEST=emerge-kukui coreboot Change-Id: Ibe336cf93b01fa2ea57b4c2e0a89685424878c91 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34871 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21mediatek: Use GPIO based SPI CSYu-Ping Wu
Some boards (e.g., Kukui) need GPIO based CS for SPI0. This patch changes the pinmux and binds the pins to the correponding SPIs. When using GPIO based SPI CS, we need to manually make CS log/high before/after SPI transactions. BUG=b:132311067 BRANCH=none TEST=Verified that b/132311067 is irreproducible Change-Id: I61653fb19242b6ee6be9a45545a8b66e5c9c7cad Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-20arch/non-x86: Remove use of __PRE_RAM__Kyösti Mälkki
Change-Id: Id8918f40572497b068509b5d5a490de0435ad50b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-15soc/mediatek: Change DSI init commands to take flexible length arrayHung-Te Lin
The fixed size of init command in lcm_init_table is wasting lots of space and we should change to packed array since the command buffer already provides length information. With this change, BOE panel init commands have been reduced from 4848 bytes to 1309 bytes. BUG=b:80501386,b:117254947 TEST=emerge-kukui coreboot chromeos-bootimage; Boots properly Change-Id: I359dde8e6f2e1c0983f4677193bb47a7ae497ca6 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34778 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15soc/mediatek/mt8183: Add DSI driverHung-Te Lin
The MT8183 display serial interface (DSI) is based on MIPI Alliance Specification, supporting high-speed serial data transfer between host processor and peripheral devices such as display modules. DSI supports both video mode and command mode data transfer defined in MIPI spec, and it also provides bidirectional transmission with low-power mode to receive messages from the peripheral. Reference: MT8183 Application Processor Functional Spec, 6.7 Display Serial Interface (DSI) BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ic413f524ca0b36f0b01f723a71fe9745e2710cd2 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-15soc/mediatek: dsi: Support sending MIPI init commandsHung-Te Lin
For systems with real MIPI panels (8173/oak was using PS8640 eDP bridge), we have to send DCS commands to initialize panel. BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots Change-Id: Ie7c824873465ac82a95bcb0ed67b8b9866987008 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34773 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15soc/mediatek: dsi: Refactor video timing calculationHung-Te Lin
The video timing should be based on PHY timing. Some values can be ignored on 8173 because of fixed values in PHY but should be calculated for newer platforms like 8183. BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots Change-Id: Id3ad2edc08787414a74188f5050460e98222caf4 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-14soc/mediatek: dsi: Refactor PHY timing calculationHung-Te Lin
The PHY timing should be calculated by data rate (Mbps). However for 8173 some values were hard-coded so we want to introduce a new mtk_phy_timing structure and a weak function mtk_dsi_override_phy_timing that allows per-SOC customization to apply PHY timings. BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots Change-Id: I1176ca06dda026029ff431aca7f9e21479eed670 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-13soc/mediatek: dsi: Refactor MIPI TX configurationHung-Te Lin
The only platform-specific difference in mtk_dsi_phy_clk_setting is how to configure MIPI TX because those registers (and logic) are quite different across different SOCs. The calculation of data rate is actually the same so we should isolate it and move to common, and rename mtk_dsi_phy_clk_setting to a better name as mtk_dsi_configure_mipi_tx. BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots Change-Id: I894dc2c4c053267debf5a58313b2bb489bcf5f3a Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-13soc/mediatek: dsi: Unify format to bpp conversionHung-Te Lin
The 'bpp' was referred to both 'bits per pixel' and 'bytes per pixel' in MTK DSI driver and should be corrected. By this change we now always consider 'bpp' as 'bits per pixel', and rename the variables for other cases. BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots Change-Id: Ibd405220b73859e5592c68f498af07eef8d7edbc Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34770 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-13soc/mediatek: Create common DSI driver from mt8173Hung-Te Lin
The DSI initialization is almost the same for 8173 and 8183, so we want to move most of common functions into common/dsi.c. The major board-specific functions left are: - reset (controller register has different format) - pin_drv_ctrl (8183 does not need this) BUG=b:80501386,b:117254947 TEST=make -j # board=oak (mt8173) Change-Id: I8d4369a3c84db551287a9c9d1b22f552c5f7518d Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34769 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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