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Set up APU mbox's functional configuration registers.
BUG=b:203145462
BRANCH=cherry
TEST=boot cherry correctly
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: I5053d5e1f1c2286c9dce280ff83e8b8611b573b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58794
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tracker is a debugging tool, include AP/INFRA/PERI tracker.
When bus timeout occurs, the system reboots and latches some
values which could be used for debug.
Signed-off-by: Zhenguo Li <ot_zhenguo.li@mediatek.corp-partner.google.com>
Change-Id: If457f4a096cd63038bf6b40552aa3caaba33d5fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58243
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DFD (Design for Debug) is a debugging tool, which scans
flip-flops and dumps to internal RAM on the WDT reset.
After system reboots, those values could be showed for
debugging.
BUG=b:192429713
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ied63913db94b2e52ab394a66c70f7edfd507c99b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57980
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add HDMI low power setting to reduce power consumption.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ica91645789e5de3401131e7050d2b1ee06c535dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57042
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add basic devapc (device access permission control) drivers.
DAPC driver is used to set up bus fabric security and data protection
among hardwares. DAPC driver groups the master hardwares into different
domains and gives secure and non-secure property. The slave hardware can
configure different access permissions for different domains via DAPC
driver.
1. Initialize devapc.
2. Set master domain and secure side band.
3. Set domain remap.
4. Set default permission.
Change-Id: I3677657a117caed0d73526f78b0ebe8180148335
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Load SSPM firmware and boot up SSPM in ramstage.
This adds 23ms to the boot time.
TEST=Load SSPM blob ok, and we can see some logs of SSPM from AP.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia227ea9f7d58129068cb36ec2de7d9feb677006b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Load MCUPM firmware and boot up MCUPM in ramstage.
TEST=can see MCUPM log from AP console
Signed-off-by: alex.miao <alex.miao@mediatek.corp-partner.google.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I9e8c45ce7166644b94319ec2e7836d3d3c8008dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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UFS reference clock (refclk) is enabled by default, which will cause
the UFSHCI to hold the SPM signal and lead to suspend failure. Since
UFS kernel driver is not built-in, disable refclk in coreboot stage.
Change UFSHCI base register to 0x11270000.
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I1386e59f802a9e3c938a7e8dbeea547fbcb02709
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
the L2C SRAM as L2 cache.
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I8777b0c8471fe17ffffdcb6ad5b7c00fb1d35db1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52925
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=boot from SPI-NOR and show console message at bootblock stage.
Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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