coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2021-07-14	soc/mediatek/mt8195: Get DRAM size from DRAM calibration result	Ryan Chuang
	Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: Ic34f29d1692b94284b2cf6c5d91d323df736c76f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56204 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-13	soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC	Yidi Lin
	TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>