summaryrefslogtreecommitdiff
path: root/src/soc/mediatek/mt8192
AgeCommit message (Expand)Author
2021-03-08soc/mediatek/common: Move DRAM implementation from mt8192 to commonXi Chen
2021-02-25mb/google/asurada: Enable RTC for event logYu-Ping Wu
2021-02-19memlayout: Store region sizes as separate symbolsJulius Werner
2021-02-16soc/mediatek: Remove unused <string.h>Elyes HAOUAS
2021-02-15soc/mediatek: Remove unused <console/console.h>Elyes HAOUAS
2021-02-05soc/mediatek/mt8192: Use LZ4 compression for MCUsYu-Ping Wu
2021-02-04soc/mediatek/mt8192/spm.c: Add missing <string.h>Elyes HAOUAS
2021-02-01soc/mediatek/mt8192: Enlarge DRAM_INIT_CODE sizeYu-Ping Wu
2021-01-28mb/google/asurada: Improve boot time by raising little CPU frequencyYidi Lin
2021-01-28soc/mediatek/mt8192: Implement dram all channel calibrationHuayang Duan
2021-01-28soc/mediatek/mt8192: Add mt6315_romstage_initYidi Lin
2021-01-28soc/mediatek/mt8192: Add function to raise the CCI frequencyWeiyi Lu
2021-01-22soc/mediatek/mt8192: pmic: Set efuses manuallyHsin-Hsiung Wang
2021-01-20soc/mediatek/mt8192: pmic: unlock key protection before initial settingHsin-Hsiung Wang
2021-01-20soc/mediatek/mt8192: pmic: add scp voltage initializationHsin-Hsiung Wang
2021-01-19soc/mediatek/mt8192: pmic: enable pwrkey long-press shutdown settingHsin-Hsiung Wang
2021-01-19soc/mediatek/mt8192: pmic: update initial settingHsin-Hsiung Wang
2021-01-19soc/mediatek/mt8192: add clkbuf and srclken_rc MT6359P driverYuchen Huang
2021-01-19soc/mediatek/mt8192: Save dramc shuffle result after calibrationHuayang Duan
2021-01-19soc/mediatek/mt8192: Add dramc ac timing settingHuayang Duan
2021-01-19soc/mediatek/mt8192: Get DDR base information after calibrationHuayang Duan
2021-01-07soc/mediatek: rtc: Use `bool` as return typeYidi Lin
2020-12-31soc/mediatek/mt8192: Move flash_controller.c to common/Yidi Lin
2020-12-31soc/mediatek/mt8192: Add DDR mode register initHuayang Duan
2020-12-31soc/mediatek/mt8192: Do dramc duty calibrationHuayang Duan
2020-12-31soc/mediatek/mt8192: Add dramc 8 phase calibrationHuayang Duan
2020-12-31soc/mediatek/mt8192: Update initial settings of dramcHuayang Duan
2020-12-30soc/mediatek/mt8192: eint: unmask eint event mask registerG.Pangao
2020-12-29soc/mediatek/mt8192: Implement dramc base settings for each frequencyHuayang Duan
2020-12-28soc/mediatek/mt8192: add rtc MT6359P driverYuchen Huang
2020-12-28soc/mediatek/mt8192: devapc: add basic devapc driversNina Wu
2020-12-28soc/mediatek/mt8192: Do dramc pre-settings before calibrationHuayang Duan
2020-12-22soc/mediatek/mt8192: Do dramc software impedance calibrationHuayang Duan
2020-12-22soc/mediatek/mt8192: Do EMI init before dram calibrationHuayang Duan
2020-12-22soc/mediatek/mt8192: Do memory pll init before calibrationHuayang Duan
2020-12-16soc/mediatek/mt8192: Do the dramc pinmux selectionHuayang Duan
2020-12-16soc/mediatek/mt8192: Correct return value of VM18 voltageHsin-Hsiung Wang
2020-12-16soc/mediatek/mt8192: Keep CONN MCU in reset stateWeiyi Lu
2020-12-16soc/mediatek/mt8192: Do dramc init settingsHuayang Duan
2020-12-16soc/mediatek/mt8192: Enable DCMmtk15698
2020-12-16soc/mediatek/mt8192: ufs: Disable reference clockWenbin Mei
2020-12-16soc/mediatek/mt8192: Initialize audio pll tuner frequencyWeiyi Lu
2020-12-15soc/mediatek/mt8192: Define DRAM registers and APIsHuayang Duan
2020-12-14soc/mediatek/mt8192: Add ddp driverYongqiang Niu
2020-12-14soc/mediatek/mt8192: Enable dsi driverHuijuan Xie
2020-12-14soc/mediatek/mt8192: add i2c driver supportQii Wang
2020-12-10soc/mediatek/mt8192: Init SSPMTingHan.Shen
2020-12-10soc/mediatek/mt8192: Init DPMHuayang Duan
2020-12-10soc/mediatek/mt8192: Load MCUPM firmware and boot up MCUPMYidi Lin
2020-12-10soc/mediatek/mt8192: add spmfw loaderRoger Lu
2020-12-10soc/mediatek/common: Add common API for loading firmwaresYidi Lin
2020-12-02cbfs: Enable CBFS mcache on most chipsetsJulius Werner
2020-11-20mediatek/mt8192: memlayout: Add DRAM DMA regionYidi Lin
2020-11-20soc/mediatek/mt8192: Enable MT8192 auxadc driverPo Xu
2020-11-18mb/google/asurada: Implement board-specific regulator controlsYidi Lin
2020-11-18soc/mediatek/mt8192: add pmic MT6315 driverHsin-Hsiung Wang
2020-11-18soc/mediatek/mt8192: add pmic MT6359P driverHsin-Hsiung Wang
2020-11-18soc/mediatek/mt8192: add pmif driverHsin-Hsiung Wang
2020-11-16soc/mediatek/mt8192: Reserve 44K SRAM for MCUPM working bufferYidi Lin
2020-10-29soc/mediatek/mt8192: Do dram full calibrationHuayang Duan
2020-10-26soc/mediatek/mt8192: update descriptions for dram configXi Chen
2020-10-23soc/mediatek/mt8192: add dram log prefixXi Chen
2020-10-23soc/mediatek/mt8192: Turn off L2C SRAM and reconfigure as L2 cacheCK Hu
2020-10-22soc/mediatek/mt8192: enable CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWAREIkjoon Jang
2020-10-20soc/mediatek/mt8192: Do dram fast calibrationHuayang Duan
2020-10-12soc/mediatek/mt8192: Refactor USB code among similar SoCsZhanyong Wang
2020-10-09soc/mediatek: Add function to measure clock frequency of MT8192Weiyi Lu
2020-10-08soc/mediatek: Add function to raise the CPU frequency of MT8192Weiyi Lu
2020-09-17soc/mediatek/mt8192: Init PLL in bootblockCK Hu
2020-09-17soc/mediatek/mt8192: Add mtcmos init supportWeiyi Lu
2020-09-10soc/mediatek: Drop unneeded empty linesElyes HAOUAS
2020-09-08soc/mediatek/mt8192: Add SPI flash controller dual read functionCK Hu
2020-09-08soc/mediatek/mt8192: Add SPI flash controller DMA read functionCK Hu
2020-08-28soc/mediatek/mt8192: Use SPI-NOR as flash controllerCK Hu
2020-08-25soc/mediatek/mt8192: Add dramc param structHuayang Duan
2020-08-17soc/mediatek/mt8192: Initialize watch dog in bootblockCK Hu
2020-08-17soc/mediatek/mt8192: Initialize mmu in bootblockCK Hu
2020-08-13soc/mediatek/mt8192: Add spi driverQii Wang
2020-08-13soc/mediatek/mt8192: Add DRAM resource in ramstageCK Hu
2020-08-13soc/mediatek/mt8192: Initialize build rulesCK Hu
2020-08-13soc/mediatek/mt8192: Add a placeholder for the EMI driverCK Hu
2020-08-12soc/mediatek/mt8192: Add PLL and clock init supportWeiyi Lu
2020-08-12soc/mediatek/mt8192: Add gpio driverCK Hu
2020-08-08soc/mediatek/mt8192: Add initial config for new ARMv8 device MT8192CK Hu