Age | Commit message (Collapse) | Author | |
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2020-11-20 | mediatek/mt8192: memlayout: Add DRAM DMA region | Yidi Lin | |
SPM DMA hardware requires a non-cacheable buffer to load SPM firmware. TEST=verified with SPM WIP patch. SPM PC stays at 0x3f4 after SPM firmware is loaded. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: If6e803da23126419a96ffc0337d35edd0e181871 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> | |||
2020-10-23 | soc/mediatek/mt8192: Turn off L2C SRAM and reconfigure as L2 cache | CK Hu | |
Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: Icaf80bd9da3e082405ba66ef05dd5ea9185784a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46387 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |