coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2023-01-13	soc/mediatek: Include <gpio.h> instead of <soc/gpio.h>	Elyes Haouas
	<gpio.h> chain-include <soc/gpio.h>. Change-Id: If2af7f77e2d910a3f3470d15dbfc98775a2633b6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-03-27	soc/mediatek: Include 'console/console.h' when appropriate	Elyes HAOUAS
	Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\\|console_time_get_and_reset\\|do_putchar\\|vprintk\\|printk\\|console_log_level\\|console_init\\|get_log_level\\|CONSOLE_ENABLE\\|get_console_loglevel\\|die_notify\\|die_with_post_code\\|die\\|arch_post_code\\|mainboard_post\\|post_code\\|RAM_SPEW\\|RAM_DEBUG\\|BIOS_EMERG\\|BIOS_ALERT\\|BIOS_CRIT\\|BIOS_ERR\\|BIOS_WARNING\\|BIOS_NOTICE\\|BIOS_INFO\\|BIOS_DEBUG\\|BIOS_SPEW\\|BIOS_NEVER' -- src/) Change-Id: I93f930de5a2a477ec4c0d8e5c8c57b25f5e4252c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com>
2021-11-17	soc/mediatek: move i2c function to common folder	Rex-BC Chen
	Move mtk_i2c_max_step_cnt, mtk_i2c_check_ac_timing, mtk_i2c_speed_init and mtk_i2c_calculate_speed to common folder to share with MT8186. TEST=test on tomato ok TEST=emerge-asurada coreboot BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I4a702741c763bf9261cea90d0d71c08b6e28c261 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-10-02	soc/mediatek: add debug dump for ltiming and clock_div	Rex-BC Chen
	ltiming and clock_div are not support for MT8173, so we separate them to weak function: mtk_i2c_dump_more_info() Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I3228c6953be5fac18a76029702b878a34c7563f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58074 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16	soc/mediatek/mt8192: adjust i2c "tLOW" and "tSU,STO"	Daolong Zhu
	The i2c actiming with the default reg setting cannot meet spec, so we need to set some regs. 1. adjust the ratio of SCL high and low level, to adjust "tLOW". 2. modify ext_conf reg to adjust "tSU,STO". BUG=b:179000159 TEST=Test on asurada (MT8192), boot pass, timing pass. Signed-off-by: Daolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com> Change-Id: Ifbe97edbc38972af5b782fb93342ee0616127dd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51024 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14	soc/mediatek/mt8192: add i2c driver support	Qii Wang
	Add I2C controller for MT8192, and revise the common I2C driver to support I2C controller running in APDMA async mode. In that case we have to initiate a different handshake protocol and reset I2C differently. BUG=b:155715435 TEST=Asurada boots up to shell Signed-off-by: Qii Wang <qii.wang@mediatek.com> Change-Id: I13835e00eb674a93aa5496a9870d1e601e263368 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>