summaryrefslogtreecommitdiff
path: root/src/soc/mediatek/mt8188
AgeCommit message (Collapse)Author
2022-08-13soc/mediatek/mt8188: Initialize DFDRex-BC Chen
DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values can be shown for debugging using MTK internal parsing tools. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I6d19dc6f4e47ed69ba2ea87c79984020a413aee9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66586 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13soc/mediatek/mt8188: Fix the order of register address in addressmap.hRex-BC Chen
TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ie9d7b361dda8c5850bc0682c255bc20f9e26675c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66668 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13soc/mediatek/mt8188: Add tracker dumpRex-BC Chen
Tracker is a debugging tool. When bus timeout occurs, the system will reboot and latch some values of tracker registers which could be used for debugging. This function will be triggered only when it encounters the bus hanging issue. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I78f676c08ea44e9bb10bd99bbfed70e3e8ece993 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66584 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-13soc/mediatek/mt8188: replace SPDX identifiers to GPL-2.0-only OR MITMacpaul Lin
This replaces 'SPDX-License-Identifier' tags in all the files under soc/mediatek/mt8188 for better code re-use in other open source software stack. These files were originally from MediaTek and follow coreboot's main license: "GPL-2.0-only". Now MediaTek replaces these files to "GPL-2.0-only OR MIT" license. Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Change-Id: If61e8b252400e8e5ecd185b6806b1ca279065f15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66628 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-07-29soc/mediatek/mt8188: Add SPI supportLiya Li
The gpios and the tick delay register are different between MT8188 and previous MediaTek SoCs, so we need to add this patch to support SPI. TEST=build pass BUG=b:236331724 Signed-off-by: Liya Li <ot_liya.li@mediatek.corp-partner.google.com> Change-Id: I6065b9d285dfd36c191f274f500fdb694920276e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66185 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-29soc/mediatek/mt8188: Add clk_buf support in romstageSong Fan
TEST=build pass. BUG=b:233720142 Signed-off-by: Song Fan <ot_song.fan@mediatek.corp-partner.google.com> Change-Id: Ic300b70a38ac204b098ca9ab15cf7045b66fd76d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66182 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-29soc/mediatek/mt8188: Add RTC supportSong Fan
Add RTC header file for SoC-specific settings. Add RTC support in romstage. TEST=build pass. BUG=b:233720142 Signed-off-by: Song Fan <ot_song.fan@mediatek.corp-partner.google.com> Change-Id: I38115ce0c9a4e1c1b2b7c8e6d40f47e99f7f86b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66181 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-29soc/mediatek/mt8188: Add AUXADC supportHui Liu
TEST=get voltage as 340mV for channel 0 in MTK EVB. BUG=b:233720142 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: Idd1edcce6cb62fcf6991bb9342c409150989c5ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/66121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-26soc/mediatek/mt8188: Initialize SSPMRex-BC Chen
SSPM is "Secure System Power Manager" that provides power control in secure domain. The initialization flow is to load SSPM firmware to its SRAM space and then enable. It takes 21 ms to load sspm.bin. coreboot logs: CBFS: Found 'sspm.bin' @0x21680 size 0xa815 in mcache @0xffffeac4 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137348 bytes) TEST=we can see the sspm logs. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ib6443b64734048c1d71eeac650f36d7c4ac709cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/66067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-26soc/mediatek/mt8188: Initialize MCUPMRex-BC Chen
Load MCUPM firmware and boot up MCUPM in ramstage. It takes 41 ms to load mcupm.bin. coreboot logs: CBFS: Found 'mcupm.bin' @0x12580 size 0xf0c6 in mcache @0xffffead0 mtk_init_mcu: Loaded (and reset) mcupm.bin in 41 msecs (122184 bytes) TEST=we can see the mcupm logs after reset releases. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Id1e62d9d6ede1c453e03eeda0d9b16fafa9e2372 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-22soc/mediatek/mt8188: Add eMMC and SD card configurationsAndy-ld Lu
Geralt reference design has both eMMC and SD card interfaces, so we have to configure both in ramstage. Implement msdc.c (mass storage device class) to place the eMMC and SD card drivers. This implementation is based on chapter 5.9 in MT8188 Functional Specification. TEST=boot to kernel using emmc successfully. BUG=b:236331724 Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.corp-partner.google.com> Change-Id: I6594c8466a133d3fdb0084716acca8dcf785f94f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65975 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-21soc/mediatek/mt8188: Add VMCH, VMC support for MT8188Hui Liu
For MT8188, we need to enable and adjust VMCH and VMC to support SD cards. Therefore, we add VPA and VSIM1 voltage adjustment APIs. TEST=measure 3.0V in VMCH and VMC. BUG=b:236331724 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I03938f9ef17a0bdd615bcbbfc7b59fa5acb8fbfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65874 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-21soc/mediatek/mt8188: Add PMIF and PMIC init supportHui Liu
Add PMIF, SPI, SPMI and PMIC init code. These PMIC settings are used by MediaTek internally. We can find these registers in "MT6365_PMIC_Data_Sheet_V1.4.pdf" and "MT6315 datasheet v1.3.pdf". The setting values are provided by MeidaTek designers. TEST=build pass BUG=b:233720142 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I05a51894b130a59c28d957b64d6401c8bb9cee91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-13soc/mediatek/mt8188: add usb host supportShaocheng Wang
Add usb host function support. TEST=read usb data successfully. BUG=b:236331724 Signed-off-by: Shaocheng Wang <shaocheng.wang@mediatek.corp-partner.google.com> Change-Id: I3494b687b811466cb6b988164d3c5b6fecc3016a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65754 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-13soc/mediatek/mt8188: Enable mmu operation for L2C SRAM and DMARex-BC Chen
- Turn off L2C SRAM and reconfigure as L2 cache: Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. - Configure DMA buffer in DRAM: Set DRAM DMA to be non-cacheable to load blob correctly. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I10f1cb8c62dfa78f59a4a5ea6087609668a0c2aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65753 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-13soc/mediatek/mt8188: Add video/audio mtcmos settingRex-BC Chen
Add power domain data for video and audio. TEST=build pass BUG=b:233720142 Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Change-Id: Ic5fd496cbc6904b42eae28a62bf00a71f0ef508d Reviewed-on: https://review.coreboot.org/c/coreboot/+/65752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-13soc/mediatek/mt8188: Add PLL and clock init supportgarmin chang
Add PLL and clock init code, frequency meter and APIs for raising little CPU/CCI frequency. For usb clock setting, we also implement mt_pll_usb_clock_setting() to enable usb clock for all ports. TEST=build pass BUG=b:233720142 Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Change-Id: I03cb5a4c6fa5ddad7da6f955d0c6d0b3395503e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-12soc/mediatek/mt8188: Add I2C driver supportkewei.xu
Add I2C controller drivers. TEST=build pass BUG=b:233720142 Signed-off-by: kewei.xu <kewei.xu@mediatek.corp-partner.google.com> Change-Id: I7d19df3571e5588c7b20d9c7f26fa177b2221851 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-07soc/mediatek/mt8188: Add NOR-Flash supportRex-BC Chen
Add NOR-Flash drivers for flash read/write. TEST=read nor flash data successfully. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I4e84fc023111b86f7f4984020d24811e3361ba03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65621 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-06soc/mediatek/mt8188: Add GPIO driversGuodong Liu
Add GPIO drivers to let other module control GPIOs. TEST=build pass BUG=b:233720142 Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> Change-Id: I0a2a5178949e9ad3e033ac332e0f1e8565e39b3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/65619 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-06soc/mediatek/mt8188: Add timer supportBo-Chen Chen
Add timer drivers to Makefile. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I0e3e58c7118a18e738a5abba391db0be9cfd7bf9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65588 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-06soc/mediatek/mt8188: Initialize watchdogBo-Chen Chen
Add watchdog support for MT8188. This implementation is based on chapter 3.10.10 in MT8188 Functional Specification. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Iaf56c78d89af53d0272583b463c050e69bbeb07a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65587 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-04soc/mediatek/mt8188: Add a stub implementation of the MT8188 SoCRex-BC Chen
Add new folder and basic drivers for Mediatek SoC 'MT8188'. Difference of modules including in this patch between MT8188 and existing SoCs: Timer: Similar to MT8195 and MT8186, MT8188 uses v2 timer. EMI/PLL/SPI: Different from existing SoCs. The implementation is based on these files: MT8188G_Application Processor Technical Brief_v0.4.pdf MT8188G_Functional Specification v0.4.pdf MT8188 Application Processor Registers-1.pdf MT8188 Application Processor Registers-2.pdf TEST=saw the coreboot uart log to bootblock BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I3320f3d49a9b9ed781ceb812e4341e379db4ac20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65585 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 14:19:19 +0000