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Set NOR pin drive to 8mA to comply with HW requirement.
This implementation is according to chapter 5.8 and 5.19 in MT8188
Functional Specification.
BUG=b:270911452
TEST=boot with following logs
[DEBUG] mtk_snfc_init: got pin drive: 0x3
[DEBUG] mtk_snfc_init: got pin drive: 0x3
[DEBUG] mtk_snfc_init: got pin drive: 0x3
[DEBUG] mtk_snfc_init: got pin drive: 0x3
Change-Id: If8344449f5b34cefcaaee6936e94f7f669c7148b
Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74064
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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<gpio.h> chain-include <soc/gpio.h>.
Change-Id: If2af7f77e2d910a3f3470d15dbfc98775a2633b6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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This replaces 'SPDX-License-Identifier' tags in all the files under
soc/mediatek/mt8188 for better code re-use in other open source
software stack.
These files were originally from MediaTek and follow coreboot's main
license: "GPL-2.0-only". Now MediaTek replaces these files to
"GPL-2.0-only OR MIT" license.
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Change-Id: If61e8b252400e8e5ecd185b6806b1ca279065f15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66628
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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The gpios and the tick delay register are different between MT8188
and previous MediaTek SoCs, so we need to add this patch to support
SPI.
TEST=build pass
BUG=b:236331724
Signed-off-by: Liya Li <ot_liya.li@mediatek.corp-partner.google.com>
Change-Id: I6065b9d285dfd36c191f274f500fdb694920276e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66185
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add NOR-Flash drivers for flash read/write.
TEST=read nor flash data successfully.
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I4e84fc023111b86f7f4984020d24811e3361ba03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65621
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new folder and basic drivers for Mediatek SoC 'MT8188'.
Difference of modules including in this patch between MT8188 and
existing SoCs:
Timer:
Similar to MT8195 and MT8186, MT8188 uses v2 timer.
EMI/PLL/SPI:
Different from existing SoCs.
The implementation is based on these files:
MT8188G_Application Processor Technical Brief_v0.4.pdf
MT8188G_Functional Specification v0.4.pdf
MT8188 Application Processor Registers-1.pdf
MT8188 Application Processor Registers-2.pdf
TEST=saw the coreboot uart log to bootblock
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I3320f3d49a9b9ed781ceb812e4341e379db4ac20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65585
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
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