coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2022-10-21	soc/mediatek: Unify PLL function names	Rex-BC Chen
	For consistency with the PLL function naming: - Rename edp_mux_set_sel() to mt_pll_edp_mux_set_sel(). - Rename mux_set_sel() to pll_mux_set_sel(). BUG=none TEST=build pass. BRANCH=corsola Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ifc7b14bf0db5a5461037e2fbf41756d1542ca945 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68622 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14	soc/mediatek/mt8188: Set PLLs to hardware default values	Garmin Chang
	Some PLLs are not used in firmware, so we should keep them as hardware default values. If their modules want to set them, the corresponding drivers should set them in the kernel stage. BUG=b:233720142 TEST=build pass. Signed-off-by: Garmin Chang <Garmin.Chang@mediatek.com> Change-Id: I9bee18005ffed7fc1785c7fd3c0370c8293064ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/67547 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14	soc/mediatek/mt8188: Fix indention in pll.c	Garmin.Chang
	BUG=b:233720142 TEST=build pass. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Change-Id: I567d1ded1c3b5e36a25026cec697d43d92d5524c Reviewed-on: https://review.coreboot.org/c/coreboot/+/67546 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14	soc/mediatek/mt8188: Change vpp_sel default mux for 4k support	Garmin Chang
	vpp_sel and ethdr_sel are vdosys clock source select mux. Steps to change to support 4K source: 1. Change vpp_sel source to mainpll_d6 to run at 416MHz. 2. Change ethdr_sel source to univpll_d6 to run at 416MHz. BUG=b:233720142 TEST=build pass. Signed-off-by: Garmin Chang <Garmin.Chang@mediatek.com> Change-Id: I24f133b9b383fd019983cb29a213b47717148e97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67545 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14	soc/mediatek/mt8188: Fix some wrong settings for PLLs	Garmin Chang
	The observed CPU big core frequency is double compared with the current PLL setting. Therefore fix the wrong setting for PLL register APMIXED_ARMPLL_BL. Moreover, we also fix some wrong settings for other PLLs. TEST=CPU frequency of big core CPU is correct and bootup correctly. BUG=b:244215537 Signed-off-by: Garmin Chang <Garmin.Chang@mediatek.com> Change-Id: I9126f439d7a5136b2fb8d66f103ef427a0b08a99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67543 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-07	soc/mediatek/mt8188: Enable mfgpll properly and fix SPMI muxes	Johnson Wang
	Some of the pll settings are incorrect, which cause problems in GPU after booting into kernel. - MFGPLL opp_ck_en bit isn't located at MFGPLL_CON1, so we need to fix it to enable MFGPLL properly. - Switch SPMI clock muxes to 260M to avoid kernel hang while probing SPMI kernel driver. TEST=GPU bringup correctly. BUG=b:233720142 Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Change-Id: I971109a5f72e3307899daaf5a5f26022124b559b Reviewed-on: https://review.coreboot.org/c/coreboot/+/67355 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2022-08-13	soc/mediatek/mt8188: replace SPDX identifiers to GPL-2.0-only OR MIT	Macpaul Lin
	This replaces 'SPDX-License-Identifier' tags in all the files under soc/mediatek/mt8188 for better code re-use in other open source software stack. These files were originally from MediaTek and follow coreboot's main license: "GPL-2.0-only". Now MediaTek replaces these files to "GPL-2.0-only OR MIT" license. Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Change-Id: If61e8b252400e8e5ecd185b6806b1ca279065f15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66628 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-07-13	soc/mediatek/mt8188: Add PLL and clock init support	garmin chang
	Add PLL and clock init code, frequency meter and APIs for raising little CPU/CCI frequency. For usb clock setting, we also implement mt_pll_usb_clock_setting() to enable usb clock for all ports. TEST=build pass BUG=b:233720142 Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Change-Id: I03cb5a4c6fa5ddad7da6f955d0c6d0b3395503e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>