| Age | Commit message (Collapse) | Author |
|---|
|
Add PLL and clock init code, frequency meter and APIs for raising little
CPU/CCI frequency.
For usb clock setting, we also implement mt_pll_usb_clock_setting() to
enable usb clock for all ports.
TEST=build pass
BUG=b:233720142
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
Change-Id: I03cb5a4c6fa5ddad7da6f955d0c6d0b3395503e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Add watchdog support for MT8188.
This implementation is based on chapter 3.10.10 in MT8188 Functional
Specification.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Iaf56c78d89af53d0272583b463c050e69bbeb07a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65587
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Add new folder and basic drivers for Mediatek SoC 'MT8188'.
Difference of modules including in this patch between MT8188 and
existing SoCs:
Timer:
Similar to MT8195 and MT8186, MT8188 uses v2 timer.
EMI/PLL/SPI:
Different from existing SoCs.
The implementation is based on these files:
MT8188G_Application Processor Technical Brief_v0.4.pdf
MT8188G_Functional Specification v0.4.pdf
MT8188 Application Processor Registers-1.pdf
MT8188 Application Processor Registers-2.pdf
TEST=saw the coreboot uart log to bootblock
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I3320f3d49a9b9ed781ceb812e4341e379db4ac20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65585
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
|
