Age | Commit message (Collapse) | Author |
|
Refactor EINT driver by
- Move `pos_bit_calc_for_eint` to `common/gpio_eint_v1.c` and rename to
`gpio_calc_eint_pos_bit`.
- Implement `gpio_get_eint_reg` to obtain EINT base address.
This change is prepared for the driver change in MT8196.
BUG=b:334723688
TEST=EINT works on Geralt
Change-Id: Ie53abc23971bfa39250ebd7dd48e28d6b91c5973
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83703
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
To reduce duplicate memmory macros of MediaTek SoCs,
move the header file to a common directory.
TEST=Build geralt pass
BUG=b:317009620
Change-Id: Iea4add8fe3735085c13438a2e177bec177913191
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83571
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
To reduce duplicate region declarations of MediaTek SoCs,
move the header file to a common directory.
BUG=b:317009620
TEST=Build geralt pass.
Change-Id: Iad1c9f520cdc5c6ad2b55e8f4ec6149fa47b17b1
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83570
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I7d7ad562eeff7247b7377b6570d489faee0aeda0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82669
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
The default MT8186 platform is to initialize USB3 port 1.
Use option bit 27 in fw_config to enable initialization of USB2 port 0
to support devices mounted on it.
BUG=b:335124437
TEST=boot to OS from USB-A
boot to OS from SD Card
BRANCH=corsola
Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82089
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
Change-Id: Icd00f30a96c53f70babdcb8a77c4b6c2868619d8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
Change-Id: Ib1a8fc50217c84e835080c70269ff50fc001392c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81811
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I0ce2b61329efede1ba8a02446610e3eb635ceedc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81462
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Starting from MT8195, MediaTek platform supports "dram adaptive" to
automatically detect dram information, including channel, rank, die
size..., and can automatically configure EMI settings. So we can just
pass a placeholder param blob to `mt_mem_init_run` by enabling this
option.
Platforms (MT8173, MT8183, MT8192) which do not support "dram adaptive"
need to implement `get_sdram_config` to get onboard DRAM configuration
info.
TEST=emerge-geralt coreboot && emerge-asurada coreboot
TEST=CONFIG_MEDIATEK_DRAM_ADAPTIVE is set to y on geralt
TEST=CONFIG_MEDIATEK_DRAM_ADAPTIVE is no set on asurada
Change-Id: I05a01b1ab13fbf19b2a908c48a540a5c2e1ccbdc
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Change-Id: Ie7bc4f3ae00bb9601001dbb71e7c3c84fd4f759a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80596
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Macros can be confusing on their own; hiding commas make things worse.
This can sometimes be downright misleading. A "good" example would be
the code in soc/intel/xeon_sp/spr/chip.c:
CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev,
This appears as CHIP_NAME() being some struct when in fact these are
defining 2 separate members of the same struct.
It was decided to remove this macro altogether, as it does not do
anything special and incurs a maintenance burden.
Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
|
The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.
This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I6f502b97864fd7782e514ee2daa902d2081633a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80074
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
TEST=check FW screen on Steelix, Tentacruel and Starmie
Change-Id: I429218d59389a6ab86b522dd597c07fa5b8ea821
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79777
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This is in preparation of a larger heap. I went for 2MB because why not?
Change-Id: I51f999a10ba894a7f2f5fce224d30bf914107c38
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Move following definitions to common/
1) the definition of the bit fields for domain remap
2) the definition of the structure for the permission of all domains
Change-Id: Iac84ebc908ae384a6280388af4120f6349a32ed4
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77860
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The TPS65132S is designed to supply positive/negative driven
application. It communicates through standard I2C compatible interface,
and it intergrates a EEPROM whose contents will be loaded into the
register at startup. Since TPS65132S is used in staryu and geralt
projects, we move the implementation to mediatek/common.
The datasheet: TPS65132-Single-Inductor-Dual-Output-Power-Supply.pdf
BUG=b:282902297
TEST=boot starmie to firmware screen
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: Iad2c9bdea5824455efcef18b44876111061cfa1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75488
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add assert for MT6366_VRF12, define a constant macro for 1200000.
BUG=none
TEST=build board starmie with mt8186.
Change-Id: I6d6a969ae993afcda0596a19928e8f98f343d589
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74394
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
To provide power to MIPI panel STA_HIMAX83102_J02, add support for
regulator VIO18.
BUG=b:272425116
TEST=test firmware display pass for STA_HIMAX83102_J02 on Starmie.
Change-Id: I3c3aa105e648b87fc39f881d762002f67b4422b5
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74341
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
|
|
Move GPIO driving-related functions to common for code reuse.
BUG=b:270911452
TEST=build pass
Change-Id: I234a2b7ef5075313144a930332bed10ffec00c6c
Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74068
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Create a new GPIO driving info table that contains only the pins used
in the bootblock. The GPIO driving info table is downsized from 1480
bytes to 24 bytes.
BUG=b:270911452
TEST=build pass
Change-Id: I24775ba93cd74ae401747c2f5a26bbf1c8f6ac0a
Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74062
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Currently on power key long press, PMIC will be reset. It would cause
an unwanted reset pulse in the power-off sequence. To match expected
sequence, change PMIC behavior to "force shutdown".
BUG=b:271771606
TEST=long-pressing power key doesn't trigger PMIC_AP_RST_L pulse
BRANCH=corsola
Change-Id: I9ab35d82e57f43bac99fa8bd7bb69fcf52250311
Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Signed-off-by: jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73705
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Lastbus is a bus debug tool. When the bus hangs, the bus transmission
information before resetting will be recorded.
The watchdog cannot clear it and it will be printed out for bus hanging
analysis.
There are two versions for lastbus:
Version 1 for MT8186, and version 2 for MT8188.
BUG=b:263753374
TEST=build pass.
Change-Id: Ibaf510481d1941376bd8da0168ef17c99a0fb9a2
Signed-off-by: ot_zhenguo.li <ot_zhenguo.li@mediatek.corp-partner.google.com>
Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73624
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
In the current Kconfig option MEDIATEK_BLOB_FAST_INIT, the meaning of
"BLOB" is unclear. Add "DRAM" to the name.
BUG=b:204226005
TEST=./util/abuild/abuild -t GOOGLE_STEELIX -x
Change-Id: Ida7bda770f1d1a40cae205b08c8cb22f2329e49f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73155
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
<gpio.h> chain-include <soc/gpio.h>.
Change-Id: If2af7f77e2d910a3f3470d15dbfc98775a2633b6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
TCPA usually refers to log described by TPM 1.2 specification.
Change-Id: I896bd94f18b34d6c4b280f58b011d704df3d4022
Ticket: https://ticket.coreboot.org/issues/423
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
dapc_init flow is the same on MT8186, MT8188 and MT8195. So move this
function to common/devapc.c
TEST=emerge-corsola coreboot; emerge-cherry coreboot;
emerge-geralt coreboot
TEST=devapc log is shown as expected and the system boots to kernel
Change-Id: I979c3a3721a82d40c9e2db7fbe62e14a9bbd53d8
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71137
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
The DSI CMDQ offset of MT8186 is different from previous SoCs.
Therefore, we define two versions for DSI register header files. The v1
is for MT8173/MT8183/MT8192 and the v2 is for MT8186/MT8188.
BUG=b:244208960
TEST=build pass
BRANCH=corsola
Change-Id: I3d13ca03b72554ab7be2b194db32a4f961f38dad
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70183
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic875708697f07b6dae09d27dbd67eb8b960749f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
For consistency with the PLL function naming:
- Rename edp_mux_set_sel() to mt_pll_edp_mux_set_sel().
- Rename mux_set_sel() to pll_mux_set_sel().
BUG=none
TEST=build pass.
BRANCH=corsola
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ifc7b14bf0db5a5461037e2fbf41756d1542ca945
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68622
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
On MT8186T, the big cores are powered on by MT6315 via PMIF. This
patch adds the following changes.
- Add MT6315 settings.
- Configure PMIC PMIF for MT6315.
BUG=b:249436110
TEST=build pass.
BRANCH=corsola
Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Id01931e564b0b5002b8d6b9d13d4f32cdf0ae708
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68620
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
For MT8186, PMIF_SPMI mode is the hardware default setting, so we don't
need to configure PMIF SPMI IO pins. Add a config to control that.
BUG=b:249436110
TEST=build pass.
BRANCH=corsola
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I92b54e8379a5dec55ef95cbd72ce03abd3a4954b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68578
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
On MT8186, PMIC interface supports PWRAP and PMIF_SPMI while other
MediaTek SoCs support PMIF_SPMI and PMIF_SPI.
BUG=b:249436110
TEST=build pass.
BRANCH=corsola
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I20efa6d84975d781972af9143c0c7e3a272653e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68577
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
MT8186 has two slightly different versions: MT8186G and MT8186T
(turbo version). Add get_cpu_id() to identify different CPUs.
BUG=b:249436110
TEST=cpu id is correct.
BRANCH=corsola
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I0612dd589e11853dbddc1d99526e9c9bf170acec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68576
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add DEVAPC permission settings for ADSP and set its domain number to 6.
TEST=SOF driver is functional.
BUG=b:204229221
Change-Id: I37bfea70386af953e89f3c38ac51e41af6aafa6e
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68290
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
To use SOF correctly, we need to initialize ADSP in coreboot stage.
TEST=SOF driver is functional.
BUG=b:204229221
Change-Id: I45db587252ccdcdf75e0be2029743034a79925c5
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68289
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
To use SOF correctly, we need to enable power domain of ADSP.
TEST=SOF driver is functional.
BUG=b:204229221
Signed-off-by: Mandy Liu <mandyjh.liu@mediatek.com>
Change-Id: I39d1357af5f901a91379fdf7e595f16952b962de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68288
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
To use SOF correctly, we need to enable ADSP clock.
TEST=SOF driver is functional.
BUG=b:204229221
Signed-off-by: Mandy Liu <mandyjh.liu@mediatek.com>
Change-Id: Ia17db889829df2668cf2af1b71c6468230de68e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68287
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Issue:
Camera APP is not functional after CB:67434 applied.
Root cause and solution:
SCP hardware needs to access H264 encoder registers, so we need to
remove the DEVAPC protection of H264 encoder for SCP.
BUG=b:247743696
TEST=camera APP is functional.
Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com>
Change-Id: I95946346018bff6a8f2dc02b1ff3e24ad079fc90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67787
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Lastbus is a bus debug tool. When the bus hangs, the bus transmission
information before resetting will be recorded.
The watchdog cannot clear it and it will be printed out for bus hanging
analysis.
TEST=build pass.
BUG=none
Signed-off-by: ot_zhenguo.li <ot_zhenguo.li@mediatek.corp-partner.google.com>
Change-Id: Iff39486dfad556a3104b2f2b6811c34c2ded6954
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Enable the protection for DEVAPC registers of AO domain.
TEST=build pass.
BUG=b:244250435
Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com>
Change-Id: I8535438d4c7da29c9dcd97be9a2af05ea4690064
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67434
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
In the previous patch (CB:60317), only basic settings were added. Now
complete DEVPAC settings on MT8186.
1. Update permission setting
2. Update master domain setting:
- domain 4: SCP
- domain 5: SPM
3. Set domain remap
- MMSYS (4-bit to 2-bit)
TEST=test on kernel correctly.
BUG=b:204229221
Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com>
Change-Id: I40a9b115fb21b6b955fde358241f4483b85e3db3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67433
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
1. There are two power sources for CPU:
- Logic power (VPROC).
- SRAM power (VSRAM_PROC).
2. There is a constraint between VPROC and VSRAM_PROC:
- 0mV <= VSRAM_PROC - VPROC <= 250mV.
With software control, the constraint might not always hold. Therefore,
we enable hardware tracking from PMIC MT6366 to ensure the constraint
is met automatically.
BUG=b:236353282, b:241615706
TEST=meet the constrain correctly when adjusting the voltage.
Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Change-Id: I6012c57e60c009f1d599b57aab1c2526ee789208
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67436
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The implementations of register_reset_to_bl31() are the same for
MedaiTek platforms, so we extract them to soc/common/bl31.c.
BUG=None
TEST=build pass
Change-Id: I297ea2e18a6d7e92236cf415844b166523616bdf
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Some functions are the same in spm.c for MT8192, MT8195, MT8186 and
MT8188, so we move them to common/spm.c.
TEST=build pass.
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I29ddefc47d8bd156fa1ca0cedd4deaed676ae7e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Some enums and functions are the same in DEVAPC driver for MT8195,
MT8186, and MT8188, so we move them to common folder.
TEST=build pass.
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia7d2145780780fd54b76952db96424b8ea477594
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
The emi.c is the same for MT8186 and MT8188, so we could move it to
the common folder and reuse it.
TEST=build pass
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I225f1d07c973129172f01bf7f4d7f5d5abe7c02b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66328
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
spm_set_power_control() is already called in spm_init(). It is not
necessary to call spm_set_power_control() again in the mtk_mcu reset
callback.
TEST=check SPM PC value (0x250) after SPM is loaded.
[INFO ] SPM: spm_init done in 54 msecs, spm pc = 0x250
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Change-Id: I7ee517e1eb6485c52155a69d05781a61ddfe4cad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66785
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
We use the same dump address and size for DFD in all MediaTek SoCs, so
we move them to dfd_common.h and rename dfd_common.h to dfd.h.
TEST=build pass
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I162bbb0a82e3b55c8cfbbd20e28a54ad01fd6b0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66585
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
When powering down SSUSB, the system needs to wait the ACK from SSUSB.
We found that the setting of USB PAD top macro is not correct and
it will cause timeout waiting for the ACK from SSUSB.
To resolve this, we add mt_pll_set_usb_clock() in pll.c to enable usb
macro control for powering down SSUSB.
TEST=timeout of ssusb powerdown ack does not occur.
BUG=b:239634625
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.corp-partner.google.com>
Change-Id: I58ba86e0467284e9947bfda1005c151a3e0c8881
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66600
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Some definitions are the same in dramc_soc.h for MT8192, MT8195 and
MT8186, so we move them to dramc_soc_common.h
TEST=build pass
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I3095333e62abf98de1f2d27033baeeba7a4cad79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66276
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
MT8188 SPI tick delay setting is moved to `spi_cmd_reg` register which
is different from previous SoCs, so we define a macro to get the
designated register.
TEST=build pass.
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia30e94a8688c0e1c1d4b3d15206f28e5bd8c9bd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66184
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Move the common definitions to rtc_reg_common.h, so we can reuse those
definitions on MT8188.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia1d916a88b7cb875b35ee5813b7b52d9e98f5009
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66180
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The AUXADC register definitions are the same for all MediaTek SoCs, so
we move struct mtk_auxadc_regs to auxadc_common.h.
TEST=build pass.
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I48978a93137a7de42f8ea2873be3130cb8f534f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
From comments of CB:65875, we replace *_vol to *_voltage.
s/mainboard_set_regulator_vol/mainboard_set_regulator_voltage/
s/mainboard_get_regulator_vol/mainboard_get_regulator_voltage/
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Iadf0408e8914d6e32915464f93979978c4634eaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
FLASH_DUAL_READ is a common configuration for all MediaTek SoCs, so we
move it to common folder and select it in SoCs' Kconfig.
As suggested in CB:58837, we also rename FLASH_DUAL_READ to
FLASH_DUAL_IO_READ to reduce confusion.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: If267a332519412a7919c5b7817047fabe4a564c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65620
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
gpio_set_pull(), gpio_set_pull_pu_pd() and gpio_set_spec_pull_pupd()
can be reused for mt8192, mt8195 and mt8186, so move it to new file
"gpio_op.c" in common folder.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I81ab9b01ee20fccf3ef29c5902597b5045d3e36a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65641
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
timer_prepare() is the same for MT8195 and MT8186, so move it to
common folder.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I91a6f4ecc665a058cb7a0ba96c15b27d6dc97d13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65602
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There are more and more variables which are SoC-specific, so add
soc/wdt.h for each SoC and rename common/wdt.h to
common/wdt_common.h.
wdt_set_req() is almost the same for mt8192, mt8195 and mt8186, so
move it to a common file wdt_req.c.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I7a334b3e7cd4f24a848dd31aca546dc7236d5fb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65636
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Change-Id: I668a39c603870329fd1528ddc5f3a42a379e1e76
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65267
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Clean up Makefile.inc by sorting entries and moving common entries to
all-y. In this way it is more clear to know what drivers have been
involved in each stage and the hardware differences between each SoC.
BUG=none
TEST=emerge-corsola coreboot
TEST=emerge-asurada coreboot
TEST=emerge-cherry coreboot
Change-Id: Idfc7de36ebf36650f7c6bd1584ef77e2a540cde9
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65315
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There is a lot of going back-and-forth with the KiB arguments, start
the work to migrate away from this.
Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
With a combined bootblock+romstage ENV_ROMSTAGE might no
longer evaluate true.
Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63376
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
To simplify the calling sequence for mtk_wdt_preinit() and we always
adjust request setting in mtk_wdt_preinit(), we rename
mtk_wdt_preinit() to mtk_wdt_set_req() and call it in mtk_wdt_init().
From this modification, we can also enable thermal hardware reset
feature (CB:64676, CB:64675) in MT8192 and MT8195.
BUG=none
TEST=build pass
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I1904ff9387f7677a077068f2c3df923bd642ea3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ied8eb0fb51d0521eedd8ff77b1083813d3843570
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
Under the current watchdog setting, the system will not reboot when the
temperature is too high. To enable thermal hardware reset, we need to
enable thermal control request and set it to reboot mode.
Note that because thermal throttle (by lowering cpu frequency) is
currently enabled, the thermal hardware reset shouldn't be triggered
under normal circumstances.
This feature is only for new hardware structure for thermal. Therefore,
we only need to apply it on MT8192/MT8195/MT8186.
This setting is based on thermal and watchdog section of MT8186
Function Specification.
BUG=none
TEST=emerge-corsola coreboot
TEST=thermal hardware reset is working.
Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com>
Change-Id: Id2ed55e6d4f4eec450bf7c849f726a389eeb6694
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64659
Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
PMIC_CPSDSA4[4:0] controls the power-down at the specified time slot.
Setting it to 0xA would cause an extra delay of 20ms compared to 0xF.
The value of time slot is from 0x0 to 0x1F which represents the delay
when reset occurs.
To avoid the delay, change the value from 0xA to 0xF.
This modification is based on chapter 3.7 in the MT8186 functional
specification.
BUG=b:218630683, b:218630684
TEST=the power-off waveform is correct.
Signed-off-by: zhiyong tao <zhiyong.tao@mediatek.corp-partner.google.com>
Change-Id: I537fe87740f0f8c25b923d7d536e81503b71762b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64038
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The per-file hash for CBFS_VERIFICATION, stored as a CBFS file
attribute, would increase the total RO metadata size by 75% (3796->6656
for corsola). Therefore, in order to make RO metadata cache fit into
CBFS_MCACHE, enlarge it from 8K to 16K.
Adjust the memlayout by decreasing the DRAM_INIT_CODE from 196K to 184K
(only 160K needed for now), and moving VBOOT2_WORK region to L2C. Also
shuffle the regions in SRAM with better comments.
BUG=b:229670703
TEST=emerge-corsola coreboot
TEST=Enabled CBFS_VERIFICATION and booted kingler into kernel
BRANCH=none
Change-Id: I8e07eb9fae1644a0fbfbdc599ca0a0e11bbe54b5
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
The MT8186 platform fails to suspend due to premature wakeup by USB.
In MT8186, we use low level latch to keep USB wakeup signal. However,
hardware could latch a wrong signal if it debounces more than one time.
As a result, it would enable wakeup function too early.
To prevent this issue, we do the following modification:
- Delay about 100 us to enable wakeup function in kernel drivers [1].
- To guarantee 100 us is enough, we need to disable the USB debounce by
default in coreboot.
According to section register 0x404 and 0x420 in
"(CODA) MT8169_PERICFG_REG.xls" which is only for MediaTek internal use:
The current default value of debounce register for MT8186 USB IP0 and
IP1 is incorrect. The reason we add in coreboot is that the default
value should be correct when SoC is booting up.
This modification is only for MT8186. The subsequent SoCs will adjust
the wakeup function to correct register value by default.
[1]: 0d8cfeeef3f5 (usb: xhci-mtk: fix random remote wakeup)
TEST=after stress test, not found premature wakeup by USB
BUG=b:228773975
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I296c4491c5959670a39fa8bd6ef987557bbc459f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63858
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
To save the power consumption, we disable the unused power of
optional components in coreboot.
BUG=none
TEST=the value of power consumption is as expected.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic0c7c2d1b6a4c26980a3029b60051ab1406406ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
The feature "USE_CBMEM_DRAM_INFO" is supported in MT8186.
Therefore, we select this configuration to enable it.
BUG=none
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ieaaf57aaee79c9dce69cc1acaa092207f0f906de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63114
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The current pmif register setting for low power mode is incorrect,
which is causing suspend failure. The issue of suspend failure is that
SRCLKENA0 will not be pulled down. EC will not be informed AP is
suspending now becuase of this. Therefore, add pmif_spmi_set_lp_mode()
to correct the setting.
This implementation is based on chapter 3.7 in MT8186 Functional
Specification.
BUG=b:215639203
TEST=test of suspend and resume pass.
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Change-Id: I2d02198f19f9cb052fba612c02404a6af1a10adb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
Originally, dram size is hard-coded to 4GB by default. To support
different dram size, calculate it from the mem chip info stored
in CBMEM.
BUG=b:206014043
TEST=Output "dram size: 0x100000000" on Kingler
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
In MT8186, we need to disable spm_thermal to prevent it from
influencing other wdt status.
There are two hardware pathes which are used for asserting watchdog
from thermal. We can disable status of path 1 because status of
path 2 is used.
1. Thermal -> SPM -> WDT
2. Thermal -> WDT
Spm_thermal (path 1) is a flexible option for software control, and
the hardware designer suggests that we should disable it if we don't
use it.
BUG=none
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I0ffde6bad3000a64e3b5782edaa72c62da034302
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62890
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Without setting the set_resources field for soc_ops, we will get an
error during device initialization:
[ERROR] CPU_CLUSTER: 0 missing set_resources
Because the set_resources field is considered mandatory, explicitly set
it as no-op noop_set_resources.
BUG=b:224419346
TEST=emerge-corsola coreboot
TEST=Did not see the error on krabby
BRANCH=none
Change-Id: Ic82b86f0482a9de09e942c1674be5f0ac615851f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
The pmic hwcid dumping should not be a warning, so we modify it to info.
BUG=none
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I4a930b69bd45d5f0d84c3d269ca721b287dbadea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
The mainboard may not be able to disable the internal cap, so we want
to set 0xe0 for all boards to minimize the internal cap. And a
mainboard implementation may choose XTAL with higher cload if the
frequency requirement is met, and the total capacitance can be tuned
externally for different boards.
BUG=b:218439447
TEST=set capid to 0xe0.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62563
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Set NOR pin drive to 8mA to comply with HW requirement.
This implementation is according to chapter 5.1, 5.6 and 5.8 in MT8186
Functional Specification.
BUG=b:218775654, b:216462313, b:212375511
TEST=SPI SI tests for AP to NOR pass for both kingler and krabby.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Add GPIO driving functions to adjust pin driving.
The value of drive strength is different for each SoC, so we define
GPIO_DRV0 to GPIO_DRV7 which are corresponding to 2/4/6/8/10/12/14/16mA
in MT8186.
This implementation is according to chapter 5.1 in MT8186 Functional
Specification.
BUG=b:218775654, b:216462313, b:212375511
TEST=build pass
Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com>
Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62471
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The XTAL 26MHz test failed on krabby, so we adjust RTC capid from
default value 0x88 to 0xC0 for MT8186. We also add a new log message
to show the capid value which is read from MT6366.
This implementation is according to chapter 5.13 in MT8186 Functional
Specification.
BUG=b:218439447
TEST=set capid to 0xc0.
TEST=XTAL 26MHz test passed.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I16ab46a5697d304e8001de231ffc9b7b7a2f9282
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
RTC_GPIO_USER_MASK is not used in any drivers, so we remove them.
BUG=none
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I0a15d5da142bb38feb595610d69566330e31fedd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
The ddr_base_info struct, which stores basic DDR information, should be
platform independent. Currently the struct is defined in each SoC's
dramc_parah.h. To prevent code duplication, move it as well as other
related structs and enums to a common header.
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I99772427f9b0755dc2c778b5f4150b2f8147bcc3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
VSRAM_CORE is not used on kingler/krabby, so we disable it.
This implementation is according to chapter 3.7 in MT8186 Functional
Specification.
BUG=b:220071688
TEST=the rail steadily shows 0V in either S0, S3, and S5.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I5256f6a2c0ca5a951dc79f564575b526a84463fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62253
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The current SPI NOR speed mainpll_d7_d2 (78MHz) is too fast for MT8186's
HW design, which is capable of up to 52MHz. Therefore, lower the speed
to univpll_d3_d8 (52MHz).
BUG=b:218775654
TEST=emerge-corsola coreboot
TEST=Boot time didn't increase significantly
BRAHCH=none
Change-Id: I5a03e41d4ce47d45b97a805b9b98877ef0dac7b7
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
The implementation of clearing watchdog status is wrong in CB:58835.
The value written to the 'wdt_mode' register should be
'wdt_mode | 0x22000000' instead of 'wdt_status | 0x22000000'.
BUG=b:204229208
TEST=check watchdog status is cleared.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I8c5dbaab2ac43d3867037bc4160aa5af2d79284f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
For most MediaTek SoCs (MT8183, MT8192, MT8195) we rely on an external
program (e.g., the "DRAM blob") to do the full DRAM calibration first,
then store and and apply the generated parameters to the reference
"fast DRAM calibration" in the vendor/mediatek folder for normal system
boot.
Starting with MT8186 the implementation of fast calibration may need
to be changed, and a "DRAM blob" only path is introduced for devices
that have to do both full and fast calibration using the external blob.
TEST=fast calibration pass on kingler/krabby
BUG=b:204226005
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: If25a7dd6aa6261ecff79a1b4df8b1f2e53d896dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Some registers of PMIC init settings are protected, so we failed to
set the correct value for init_setting. We disable protection before
setting PMIC init setting and enable it afterward.
BUG=b:216263707
TEST=PMIC setting value is set correctly.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I94d73d9c8a137444988e65c3709d29a3a4c03c5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61390
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Replace (1 << x) with BIT(x) in pmic_wrap.h.
BUG=none
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I463589f02065a228a8af74447b4586e5b54e0b3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61351
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There is no wakeup source when we test function of suspend and resume.
The root cause is that the monitor enable bit of PWRAP is not configured
correctly.
BUG=b:213255218, b:214978483
TEST=receive wakeup source from MT6366 successfully
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I324d18fa5d3cd745c35fcf0f207e1b444b5e898b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61330
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
To be shared with different SOCs, move the dramc_param_header struct
as well DRAMC_PARAM_FLAG and DRAMC_PARAM_CONFIG enums to a common
header file dramc_param_common.h.
TEST=fast calibration pass
BUG=b:204226005
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I087971799803e47e34c30063b2b0bd0cfc5795ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61132
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ic87e41a9b317cc7d0b36ece5ffd1d32068e6a33a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
We need to protect debugsys for firmware image without serial console.
Original settings for protecting debugsys is wrong which will cause some
hardware modules to fail to set their registers correctly.
We move the setting from MM_AO_APC to INFRA_AO_APC because the setting
of debugsys is defined in INFRA_AO_APC and set the debugsys index to
correct value of 94.
BUG=b:213125558
TEST=all modules work normally using image without serial console.
Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com>
Change-Id: Ibce626386ac1f8de42f8717c4ad9ba403640b3ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60833
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
DFD (Design for Debug) is a debugging tool, which scans flip-flops
and dumps to internal RAM on the WDT reset. After system reboots,
those values can be shown for debugging using MTK internal parsing
tools.
BUG=b:202871018
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7b711755022b5d9767019611151fea65e71edc66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60828
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The current CBFS mcache size (roughly 7KiB) is insufficient for mt8186,
so we need to increase it by 1KiB (and decrease the stack by 1KiB).
Error logs:
CBFS ERROR: mcache overflow, should increase CBFS_MCACHE size!
CBFS: mcache @0x0010e004 built for 63 files, used 0xde4 of 0xdfc bytes
BUG=b:202871018
TEST=no cbfs error logs.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I1e627ede3774665575006f752f89101e3c5bde9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60529
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I8f88541dce457e978a2cbea036d4f6eae387963f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
To provide power to PS8640, the eDP bridge IC on krabby, add control
of VRF12 and VCN33 to set voltage from MT6366.
TEST=measure 1.2V from VRF12 and 3.3V from VCN33.
BUG=b:210806060
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I55a9ca16e1e335e9355d0a1b30c278a9969db197
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Enable DSI for display.
BUG=b:209930699
TEST=Firmware display looked good
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Idb6bd3a1d32ac96a9d1a2553b8a70db4e59eec16
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Add DDP (display controller) driver that supports main path to
eDP panel. The output goes to display interface DSI.
BUG=b:209930699
TEST=saw firmware display
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic4fb40832b5dc7a815b37266259b2e3281ee79f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Use common SoC drivers for DRAM calibration support.
TEST=build pass.
BUG=b:202871018
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: Ie1a1e04da0cce9aaf86588a94c64d2242e7cb4b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
Remove emi.h because emi.h is defined in common/include/soc.
Add dramc_param.h and dramc_soc.h to prepare for implementation of
DRAM full calibration.
TEST=build pass.
BUG=b:202871018
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: If8662ed43088ea5aa1fe6cb5b2c4bda2338c4387
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60385
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
PS8640 is a low power MIPI-to-eDP video format converter.
VRF12 does not provide power to PS8640 on krabby.
In original patch, VRF12 is not used, and is set to hardware control
for low power. We change the setting to remove hardware control.
Therefore, if we want to control VRF12 by software, we can control
it directly.
BUG=b:210806060
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I87d6a94b6fb343590d563ac1554ff87b11c01549
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|