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2021-11-15soc/mediatek/mt8186: add USB supportRex-BC Chen
1. Enable and setup USB drivers. 2. Pull up to a weak resistor for USB3_HUB_RST_L and we reset the hub via GPIO149. TEST=boot kernel from USB ok BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ifcc11d51b0c1e495477957111e6021ef8275f629 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek/mt8186: add SPM register definitionsRex-BC Chen
Add SPM register definitions so that other drivers can use them. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Iec2b493e464be9d617226cc8a9875ee3ddb759de Reviewed-on: https://review.coreboot.org/c/coreboot/+/59248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek/mt8186: Enable mmu operation for L2C SRAM and DMARex-BC Chen
1. Turn off L2C SRAM and reconfigure as L2 cache Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. 2. Configure DMA buffer in DRAM Set DRAM DMA to be non-cacheable to load blob correctly. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If56d29cdd7d9dfaed05e129754aa1f887a581482 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek/mt8186: Add support for PMIC MT6366James Lo
Add basic support for VCORE/VDRAM1/VDDQ of MT6366. TEST=build pass BUG=b:202871018 Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com> Change-Id: I22e30421560a32f4a9e15899e8150376b1414494 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek: change help text of FLASH_DUAL_READRex-BC Chen
Change help text to "dual IO read mode" to reduce noun confusion. Suggestion from this comment: https://review.coreboot.org/c/coreboot/+/58837/comment/40a98af1_dce6bb2b/ Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I54b81cdeba3b693451f66e003fb470c9f8c19ad9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-08soc/mediatek/mt8186: Add SPI driver supportRuwen Liu
Add SPI controller drivers. TEST=build pass BUG=b:202871018 Signed-off-by: Ruwen Liu <ot_ruwen.liu@mediatek.com> Change-Id: I59a885c4fa31b6e2921698eaa3b97dbdc3144946 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-05soc/mediatek/mt8186: Enable and initialize EINTRex-BC Chen
EINT event mask register is used to mask EINT wakeup source. All wakeup sources are masked by default. Since most MediaTek SoCs do not have this design, we can't modify the kernel EINT upstream driver to solve the issue 'Can't wake using power button (cros_ec) or touchpad'. So we add a driver here to unmask all wakeup sources. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I84946c2c74dd233419cb94f013a42c734363baf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-05soc/mediatek/mt8186: Add timer supportRex-BC Chen
Add timer drivers to use timer function. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I6524e4dec4cbe7f7eb75a7940c329416559a03c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-05soc/mediatek/mt8186: Add PLL and clock init supportChun-Jie Chen
Add PLL and clock init code, frequency meter and APIs for raising little CPU/CCI frequency. TEST=build pass BUG=b:202871018 Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Change-Id: Id46d0708e7ba0c1a4043a5dce33ef69421cb59c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-05soc/mediatek/mt8186: add NOR-Flash GPIO setting in soc folderRex-BC Chen
The NOR-Flash can be configured on SPI0 or TDM-RX GPIOs so we have to provide an init function in SoC for the mainboard to select right configuration. TEST=boot to romstage BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I285ec64ace8b72a48ef1d481d366bd67cb9b0337 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-04soc/mediatek/mt8186: Add NOR-Flash supportRex-BC Chen
Add NOR-Flash drivers to pass verification of flash at verstage. TEST=boot to romstage BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If51d765e1fd4895f97898710ec6fa1374e1048fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58837 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/mediatek/mt8186: Add GPIO driversGuodong Liu
Add GPIO drivers to let other module control GPIOs. TEST=build pass BUG=b:202871018 Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> Change-Id: Ice342ab94397db8bc0fbbeb8fb5ee7e19de871ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/58836 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/mediatek/mt8186: Initialize watchdogRex-BC Chen
MT8186 requires writing speical value to mode register to clear status register. The flow of clear status is different from other platforms, so we override mtk_wdt_clr_status() for MT8186. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I290b69573a8e58db76814e16b5c17c23413f1108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58835 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoCRex-BC Chen
Add new folder and basic drivers for Mediatek SoC 'MT8186'. Difference of modules including in this patch between MT8186 and existing SoCs: Timer: Similar to MT8195, MT8186 uses v2 timer. EMI/PLL/SPI: Different from existing SoCs. TEST=boot from SPI-NOR and show uart log on MT8186 EVB BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58640 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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