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path: root/src/soc/mediatek/mt8186/mt6366.c
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2022-05-09soc/mediatek/mt8186: Change the power-down time slot from 0xA to 0xFzhiyong tao
PMIC_CPSDSA4[4:0] controls the power-down at the specified time slot. Setting it to 0xA would cause an extra delay of 20ms compared to 0xF. The value of time slot is from 0x0 to 0x1F which represents the delay when reset occurs. To avoid the delay, change the value from 0xA to 0xF. This modification is based on chapter 3.7 in the MT8186 functional specification. BUG=b:218630683, b:218630684 TEST=the power-off waveform is correct. Signed-off-by: zhiyong tao <zhiyong.tao@mediatek.corp-partner.google.com> Change-Id: I537fe87740f0f8c25b923d7d536e81503b71762b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64038 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-29soc/mediatek/mt8186: Fix pmif setting for low power modeZhiyong Tao
The current pmif register setting for low power mode is incorrect, which is causing suspend failure. The issue of suspend failure is that SRCLKENA0 will not be pulled down. EC will not be informed AP is suspending now becuase of this. Therefore, add pmif_spmi_set_lp_mode() to correct the setting. This implementation is based on chapter 3.7 in MT8186 Functional Specification. BUG=b:215639203 TEST=test of suspend and resume pass. Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Change-Id: I2d02198f19f9cb052fba612c02404a6af1a10adb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-15soc/mediatek/mt8186: change pmic hwcid from warning to infoRex-BC Chen
The pmic hwcid dumping should not be a warning, so we modify it to info. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I4a930b69bd45d5f0d84c3d269ca721b287dbadea Reviewed-on: https://review.coreboot.org/c/coreboot/+/62775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-02-23soc/mediatek/mt8186: disable VSRAM_CORERex-BC Chen
VSRAM_CORE is not used on kingler/krabby, so we disable it. This implementation is according to chapter 3.7 in MT8186 Functional Specification. BUG=b:220071688 TEST=the rail steadily shows 0V in either S0, S3, and S5. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I5256f6a2c0ca5a951dc79f564575b526a84463fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62253 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-29soc/mediatek/mt8186: Add register protect control for MT6366Rex-BC Chen
Some registers of PMIC init settings are protected, so we failed to set the correct value for init_setting. We disable protection before setting PMIC init setting and enable it afterward. BUG=b:216263707 TEST=PMIC setting value is set correctly. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I94d73d9c8a137444988e65c3709d29a3a4c03c5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61390 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-01soc/mediatek/mt8186: Add support for regulator VRF12/VCN33Rex-BC Chen
To provide power to PS8640, the eDP bridge IC on krabby, add control of VRF12 and VCN33 to set voltage from MT6366. TEST=measure 1.2V from VRF12 and 3.3V from VCN33. BUG=b:210806060 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I55a9ca16e1e335e9355d0a1b30c278a9969db197 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-28soc/mediatek/mt8186: Enable VRF12 software control for MT6366Rex-BC Chen
PS8640 is a low power MIPI-to-eDP video format converter. VRF12 does not provide power to PS8640 on krabby. In original patch, VRF12 is not used, and is set to hardware control for low power. We change the setting to remove hardware control. Therefore, if we want to control VRF12 by software, we can control it directly. BUG=b:210806060 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I87d6a94b6fb343590d563ac1554ff87b11c01549 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26soc/mediatek/mt8186: fix variable typeRex-BC Chen
The types of pwrap_read_field()'s return value and pwrap_write_field()'s `val` argument are u16, so correct the usage in MT6366. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ie05ab65ecd9b8ea1379ef74393285c4f5d2db8a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26soc/mediatek/mt8186: Add support for regulator VPROC12/VSRAM_PROC12Rex-BC Chen
To raise little CPU frequency, add support for VPROC12 and VSRAM_PROC12 of MT6366. TEST=build pass BUG=b:202871018 Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com> Change-Id: I718fdf36d34969a6e21ddc8c1ec6f525e0e20904 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek/mt8186: Add support for regulator VMCH and VMCRex-BC Chen
Add support for VMCH and VMC of MT6366. TEST=measure voltage 3.3V for VMCH and VMC BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Id8d98b6d827abd4713ee5c216941a9621422c7eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/59254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek/mt8186: Add support for PMIC MT6366James Lo
Add basic support for VCORE/VDRAM1/VDDQ of MT6366. TEST=build pass BUG=b:202871018 Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com> Change-Id: I22e30421560a32f4a9e15899e8150376b1414494 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>