coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2019-06-21	mediatek/mt8183: Add infra group DCM setting	Weiyi Lu
	Add infra group DCM (Dynamic Clock Management) settings, which slows down OR gate clocks while hardware is in idle state. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I4741dfb7b984deb92171f370e5fb2593829d74c2 Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: You-Cheng Syu <youcheng@google.com>
2019-04-29	mediatek: Add function to raise the CPU frequency	Tristan Shieh
	Implement mt_pll_raise_ca53_freq() in MT8183 to raise the CPU frequency. Move the function declaration to common header. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui Change-Id: Ide8d767486d68177fa2bfbcc5b559879eca1bcda Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-29	mediatek/mt8183: Init audio related clock	Jiaxin Yu
	Enable audio clock, intbus clock, infra clock and mtkaif 26m clock.Needed by audio playback in firmware. BUG=b:117254418 BRANCH=none TEST=Build pass and verified on kukui p1 board Change-Id: I88060d9796cc23ad7f524943f36869e1ec85073d Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-03-04	device/mmio.h: Add include file for MMIO ops	Kyösti Mälkki
	MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-26	mediatek/mt8183: Modify I2C source clock	Qii Wang
	This patch change i2c source clock to TOPCKGEN. BUG=b:80501386 BRANCH=none TEST=Boot correctly on kukui. Change-Id: I49e0acda22dba449d0873a95ba5fae79a9cef569 Signed-off-by: Qii Wang <qii.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-10-10	mediatek/mt8183: Init PLLs for DRAM	Tristan Shieh
	Set up DRAM related PLLs. And update post divider table to fulfill all freqency settings. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ic197cef7d31f75ffe4e7d9e73c9cc544719943ab Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-on: https://review.coreboot.org/28667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2018-07-11	mediatek/mt8183: add PLL and clock init support	Weiyi Lu
	Add PLL and clock init code. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Checked with frequency meter in SOC. Change-Id: I1f561f66bcf12de6a95c2f64eecd9508bd9bb26c Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-on: https://review.coreboot.org/27031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>