aboutsummaryrefslogtreecommitdiff
path: root/src/soc/mediatek/mt8183/include
AgeCommit message (Expand)Author
2019-01-24mediatek/mt8183: Move some initialization into mt8183_early_initYou-Cheng Syu
2019-01-03mediatek/mt8183: Add DDR driver of runtime config partHuayang Duan
2018-12-11mediatek/mt8183: Add DDR driver of tx rx window perbit cal partHuayang Duan
2018-12-05mediatek: Share GPIO external interrupts (EINT) code among similar SoCsChuanjia Liu
2018-11-29mediatek/mt8183: Add DDR driver of rx dqs gating calibration partHuayang Duan
2018-11-29mediatek/mt8183: Add MT6358 PMIC supportHsin-Hsiung Wang
2018-11-29mediatek/mt8183: Add PMIC wrapper supportHsin-Hsiung Wang
2018-11-08mediatek/mt8183: Add DDR driver of cmd bus training partHuayang Duan
2018-11-08mediatek/mt8183: Add DDR driver of pre-calibration partHuayang Duan
2018-11-05mediatek/mt8183: Add DDR driver of software impedance partHuayang Duan
2018-11-02mediatek/mt8183: Add AUXADC driverPo Xu
2018-10-26mediatek/mt8183: Correct MPU ctrl register addressHuayang Duan
2018-10-24mediatek/mt8183: Initialize DRAM with a sequence in constant arrayHuayang Duan
2018-10-18mediatek/mt8183: Add EMI init for DDR driver initHuayang Duan
2018-10-18mediatek/mt8183: Add register definitions of DRAM controllerTristan Shieh
2018-10-17mediatek/mt8183: Add USB supportJumin Li
2018-10-10mediatek/mt8183: Init PLLs for DRAMTristan Shieh
2018-07-27mediatek/mt8183: Add SPI supportmengqi.zhang
2018-07-26mediatek/mt8183: Enable bootblock self-decompressionHung-Te Lin
2018-07-20mediatek/mt8183: Add GPIO supportPo Xu
2018-07-11mediatek/mt8183: add PLL and clock init supportWeiyi Lu
2018-07-11mediatek/mt8183: Add MMU operation supportTristan Shieh
2018-07-02mediatek/mt8183: Add mtcmos init supportTristan Shieh
2018-06-21mediatek/mt8183: Remove DRAM_DMA sectionTristan Shieh
2018-06-21mediatek/mt8183: Add watchdog timer supportTristan Shieh
2018-06-11mediatek/mt8183: Add a stub implementation of the MT8183 SOCTristan Shieh
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-17 07:38:14 +0000