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This patch changes the mapping of SRAM from non-secure to secure.
Without this patch, mmu_config_range() can not work when MMU is
enabled. The new config is still in non-secure cache since TTB section
is allocated in SRAM which is mapped as non-secure.
BUG=b:80501386
TEST=Boots correctly on Kukui and Elm
Change-Id: Ia5b8716cfcca64d1d716a177225ea2f7ac2920a6
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Refactor MMU operation code which will be reused among similar SOCs.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm
Change-Id: Id8173da0a02e57e863263fcd89c91a9c089e8a0f
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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NOR flash has a hardware limitation that it can't access SRAM region
after 4GB mode is enabled. We add a DRAM DMA region after 0x40000000
for NOR flash driver. So that the NOR flash driver can use this region
after 4GB mode is enabled.
BRANCH=none
BUG=chormoe-os-partner:49229
TEST=Boot to kernel on rev4 w/ 2GB ram and rev3 w/ 4GB ram.
And check /proc/meminfo.
Change-Id: I4a86f0028b26509589ec8d09e2d077920446ece1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dc61ec55187959101a9e891fe5e93928e9b8176e
Original-Change-Id: Ifedc9e2dfba5d294297b3a28134997ac1dd38f94
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327962
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331177
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13989
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Remove DRAM_SIZE_MB Kconfig setting and use sdram_size_mb() to detect
the DRAM size at runtime.
BUG=chrome-os-partner:49427
BRANCH=none
TEST=Boot to kernel
Change-Id: I0c3245db73335fb4f1c89c1debde715fc96ecba7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 00f6f2bbed0e7d23181337b9274191b31e73e223
Original-Change-Id: I409163fe527e966c184f28d7d9bbc809ae2308ed
Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com>
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327961
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331176
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13988
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The DRAM size can not be determined before DRAM is initialized. Since
mt8173 only support 2GB and 4GB DRAM models. We map 0x0 to the end of
2GB DRAM address before DRAM is initialized.
BRANCH=none
BUG=none
TEST=boot to kernel
Change-Id: I27a00106b0aa91c3dacfcd2bcd9208f08b108dc5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9720e67c86f0d37a08f7c32e900996c75d60288a
Original-Change-Id: I87d9c6ac11486decde102b7821f550c2f1a51f1c
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327960
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331175
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13987
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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BRANCH=none
BUG=none
TEST=build pass
[pg: split into multiple commits]
Change-Id: Ib46b243102969e2860479070e19640fb6cb9bdd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3ee2a20ec56359e917bb8f4825846c54d4f6276a
Original-Change-Id: Iedc81a85569b00524620e9ba128e7d77f17b0405
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292666
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12614
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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