summaryrefslogtreecommitdiff
path: root/src/soc/intel
AgeCommit message (Collapse)Author
2020-10-29mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg'Subrata Banik
List of changes: 1. Split mem_cfg for DDR4 and LPDDR4 as per board_id 2. Move dq_pins_interleaved into board-specific memory configuration information TEST=Able to build and boot DDR4 and LPDDR4 ADLRVP SKUs. Change-Id: I6ef19209767c810426bba0c8bc48178bf2e2a110 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46873 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-28soc/intel: deduplicate ACPI timer emulationMichael Niewöhner
The code for enabling ACPI timer emulation is the same for the SoCs SKL, CNL, ICL, TGL, JSL and EHL. Deduplicate it by moving it to common code. APL differs in not having the delay settings. However, the bits are marked as "spare" and BWG mentions there are no "reserved bit checks done". Thus, we can write them unconditionally without any effect. Note: The ACPI timer emulation can only be used by SoCs with microcode supporting CTC (Common Timer Copy) / ACPI timer emulation. Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-28src/soc/intel/xeon_sp: Fill in the cache information in SMBIOS type 7Morgan Jang
TEST=Execute "dmidecode -t 7" to check if cache error correction type and cache sram type is correct for each cache level Change-Id: Ibe7c6ad03a83a6a3b2c7dfcfafaa619e690a418d Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28soc/intel/xeon_sp/cpx: Set SLEEP_BUTTON flag in ACPI FADTMorgan Jang
Keep SLEEP_BUTTON flag in ACPI FADT to indicate that no sleep button is present on Cooperlake platform. Change-Id: I2ce435a7bda780b2d2ed00be3f3a8a080c4434ab Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28mb/ocp/deltalake: Rename motherboard_fill_fadt()Jingle Hsu
Rename motherboard_fill_fadt() to the common override mainboard_fill_fadt() function to override FADT. Tested=On OCP Delta Lake, verify FADT PM Profile is set to Enterprise Server. Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Change-Id: Ie9ea7cc6e712d0aca57bbeac1a4154921d123be4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26Revert "soc/intel/jasperlake: Allow mainboard to override chip configuration"Karthikeyan Ramasubramanian
This reverts commit 5acea15d63e821a1bc416d206162ed030cd5d57c. This change got accidentally merged. There is no need for mainboard to override chip configuration. BUG=None TEST=Build and boot Drawlat to OS. Change-Id: I166ba7e5ee50a6329032eae8e17b9a554b094e2e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26soc/intel/icl: enable common CPU codeMichael Niewöhner
Enable CPU_INTEL_COMMON to make common CPU code available to CNL, which gets used in CB:45535 and CB:45536 for CPPC entries generation. Note: This also retrieves the VMX Kconfig and enables it by default, like done for SKL and CNL already. Since FSP always set the feature config lock, SET_IA32_FC_LOCK_BIT gets selected statically by the SoC to reflect this in menuconfig. Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45826 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`Michael Niewöhner
The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-10-26soc/intel/skl: replace conditional on dt option reading CPUID for CPPCMichael Niewöhner
Check ISST (Intel SpeedShift) availability via CPUID.06H:EAX[7], instead of relying on the devicetree option `speed_shift_enable`, that is going to be dropped. Test: GCPC and _CPC entries still get generated on Supermicro X11SSM-F Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46461 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26soc/intel: drop unneeded ISST configuration codeMichael Niewöhner
The code configuring ISST (Intel SpeedShift Technology) sets the ISST capability bits in CPUID.06H:EAX. It does *not* activate HWP (Hardware P-States), which shall be done by the OS only. Since the capability is enabled by default (opt-out), there is nothing to do for us in the enabled-case. Practically speaking, there is no value at all in disabling the capability, since one can configure the OS to not enable HWP if that is desired. The two other bits for EPP and HWP interrupt that were set by the code are not set anymore, too. It was tested, on three platforms so far (CML-U, KBL-H, SKL-U), that these are set as well by default in the MSRs reset value (0x1cc0). To reduce complexity and duplicated code without actual benefit, this code gets dropped. The remaining dt option will be dropped in CB:46462. Test: Linux on Supermicro X11SSM-F detects and enables HWP: [ 0.415017] intel_pstate: HWP enabled Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46460 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26soc/intel/common/block/smbus: Add define for I2C_ENPatrick Rudolph
Change-Id: Iecccc363f492985555019f2390bd53472a000ba9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26soc/intel/common/block/smbus: Add Cannonpoint PCH-H PCI IDPatrick Rudolph
This is required to make sure the defined SMBUS_BASE address is valid even after PCI enumeration. Tested on Prodrive Hermes. Change-Id: Ibd40e556fd890000836d23682d4e9e3aa5200c54 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46562 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26src: Include <arch/io.h> when appropriateElyes HAOUAS
Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45404 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26soc/intel/xeon_sp/acpi: Add pch.aslMarc Jones
Add ASL for the PCH. Initially, this only contains soc/intel/common/block/acpi/acpi/lpc.asl. Additional PCH ASL may be added in the future. Change-Id: I70cb790355430f63f25e0dbc9fccc22462fe3572 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45836 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-25soc/intel/broadwell: Merge `chip.c` into `systemagent.c`Angel Pons
Prepare to break down Broadwell into CPU, northbridge and southbridge. Change-Id: Ic844cc3bbff760fa0eed9d81208bbeef39577e9d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46698 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-25soc/intel/broadwell: Drop `broadwell_pci_ops`Angel Pons
This is essentially a duplicate of `pci_dev_ops_pci`. Change-Id: I06a21ebd759c35910cd753d3079ea7902868e89d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46697 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-25soc/intel/alderlake/romstage: Skip GPIO configuration from FSPSubrata Banik
Set GpioOverride UPD to 1 to skip GPIO configuration in FSP phases TEST=Able to build and boot ADLRVP to OS. Change-Id: Ie965a85d9da9b6a23b385536313b852e66909cf4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-24soc/intel/broadwell/gma.c: Align `igd_setup_panel` with HaswellAngel Pons
Rename it, add a print and factor out refclock value into a variable. Change-Id: I7248e0b54cd6310cf74eadc5d976a8868cf822f2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46688 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24soc/intel/broadwell: Use get_{pmbase,gpiobase}Angel Pons
This is to align Broadwell and Lynx Point. Change-Id: I9facaec2967616b07b537a8e79b915d6f04948a7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45717 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24{cpu,soc}/intel: deduplicate cpu codeMichael Niewöhner
Move a whole bunch of copy-pasta code from soc/intel/{bdw,skl,cnl,icl, tgl,ehl,jsl,adl} and cpu/intel/{hsw,model_*} to cpu/intel/common. This change just moves the code. Rework is done in CB:46588. Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46274 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23soc/intel/broadwell: Add ECC config reportingAngel Pons
This has been taken from Haswell, and is just to reduce differences. Change-Id: Ib872cbcd20d6e212b1f55400aa350dc6ba44dc2a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23soc/intel/broadwell: Remove unnecessary arrayAngel Pons
The MAD_DIMM registers can be read within the loop just fine. Change-Id: Id0c79aaa506f7545826445bc5b065408105b46ba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23soc/intel/broadwell: Fix copy-pasted copy-paste errorAngel Pons
The code with this error was copy-pasted from Haswell. It was fixed with commit dab81a4 (northbridge/intel/haswell: Fix copy paste error) for Haswell. Do the same for Broadwell. Given that LP SKUs only support one DIMM per channel, this change makes no difference in practice. Change-Id: I2a7bee617354870aa4334b6c0e6b49d831e64c23 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-10-23soc/intel/broadwell: Align raminit-related code with HaswellAngel Pons
Use Haswell MCHBAR register names and align cosmetics of functions. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: Ie8f369a704b833da86c2eb5864dffe2e8c4bb466 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46364 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23soc/intel/broadwell: Relocate `report_memory_config` functionAngel Pons
This allows us to make it static, like it is on Haswell. Change-Id: I8f782ce6ac390082c56a881c6b26d82b548205d9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23soc/intel/broadwell/romstage/pch.c: Drop reg-script usageAngel Pons
Change-Id: I0e83eb724edc41514928482afe1bc90fb782e852 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23soc/intel/broadwell/romstage/romstage.c: Clean up includesAngel Pons
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: Ibbffe152e511065dc265155555c56446fbb70405 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46358 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23soc/intel/tigerlake: Add Acoustic featuresShaunak Saha
Expose the following FSP UPD interface into coreboot: - AcousticNoiseMitigation - FastPkgCRampDisable - SlowSlewRateFor BUG=b:153015585 BRANCH=none TEST= Measure the change in noise level by changing the UPD values. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: I1924a3bac8beb16a9d841891696f9a3dea0d425f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-23soc/intel/broadwell: Move `fill_postcar_frame` to memmap.cAngel Pons
Other Intel northbridges have this function in this file. Change-Id: I9f084e760ec438d662484455212b5c40a8448928 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23soc/intel/broadwell: Drop reg-script usage from bootblock PCH initAngel Pons
Change-Id: I87145215ccec86e391d0dbd9171b08d7fd73ad9a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46352 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23soc/intel/broadwell: Define RCBA register LCAPAngel Pons
This register has a name. Use it. Change-Id: I952584c4aa92fc917d2fc0ef174ee12ae3eeee81 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-10-23soc/intel/broadwell/finalize.c: Use register namesAngel Pons
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: Ida1266f52fcc06577bd876f2cf3e3324ced6ab9d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23soc/intel/broadwell: Sort SA registers in ascending orderAngel Pons
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: Ifc3ac5e1d17d5aa45dc7e912cbc210d89af7cd2b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46337 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23soc/intel/broadwell: Drop reg-script to finalize SAAngel Pons
There's no need to use reg-script to do this. Since Haswell does not use reg-script, drop it here to ease comparisons between both platforms. Change-Id: I28323e891661758c23542c23ad9409d7fafbadf6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46525 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23soc/intel/broadwell: Revise SA lockdown sequenceAngel Pons
The MC_LOCK register was written twice and SA PM no longer has a lock bit. Update the sequence as per the Broadwell BIOS Specification, but keep the registers sorted by type. Change-Id: I91cd0aa61ba6bc578c892c1a5bc973bf4c28d019 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46324 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23haswell/broadwell: Fix typos of `BCLK`Angel Pons
Change-Id: Ifed3c8250d5c9869493285d0b87580b70ff37965 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-10-23soc/intel/broadwell/memmap.c: Use `SA_DEV_ROOT` macroAngel Pons
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I013357d31974582f64a35b8228d9edfa16af99fd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23soc/intel/broadwell: Use common early SMBus codeAngel Pons
Disabling interrupts and clearing errors was being done twice, once in the `smbus_enable_iobar` reg-script, and another in `enable_smbus`. Change-Id: I58558996bd693b302764965a5bed8b96db363833 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-23soc/intel/broadwell/lpc.c: Drop reg-script usage for PCH misc initAngel Pons
Change-Id: I4846f9303367452bbb1d21c2d7f4a1fb9f2efe5d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23soc/intel/broadwell/lpc.c: Drop reg-script usage for PCH PM initAngel Pons
Change-Id: I570fedc538a36f49912262d95b7f57ad779dc8a5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-23soc/intel/broadwell: Drop reg-script from early SA initAngel Pons
Haswell does not use reg-script, but does more or less the same thing. Adapt Broadwell to ease the eventual unification with Haswell. Change-Id: I4d3e0d235b681e34ed20240a41429f75a3b7cf04 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23soc/intel/broadwell: Guard MCHBAR macro parametersAngel Pons
Add brackets around the parameters to avoid operation order problems. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I6efbe70d2bb3ad776a2566365afa66afab51584e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23soc/intel/xeon_sp/skx: Add missing includesAngel Pons
Commit 985d956 (soc/intel/xeon_sp/skx/: Clean up soc_util.c) removed some indirect header inclusions, which resulted in a build failure. Change-Id: I1ef9b416b52a6a1275d699708a805d4ba49baef0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46662 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22soc/intel/xeon_sp: Rename cpx_generate_p_state_entries()Marc Jones
Prepare for common ACPI. Rename cpx_generated_p_state_entries() to the common soc_power_states_generation() function. Add empty soc_power_states_generation() to skx. Change-Id: Ib7e8dfd2bb602f3e6ccdb5b221bc65236f66a875 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-22soc/intel/xeon_sp/skx: Move skx specific FADT settingMarc Jones
Prepare for common ACPI. Move the skx specific FADT settings from acpi.c to soc_acpi.c, soc_fill_fadt. This gets acpi_fill_fadt() to match common/block/acpi.c. Change-Id: I04873d13d822de514acbb58501171285bd5b020e Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-22soc/intel/xeon_sp: Move uncore_inject_dsdt() callMarc Jones
Prepare for common ACPI code. Move uncore_inject_dsdt() to the uncore device acpi_inject_dsdt call. Change-Id: Ida106238690eb1af17759ba6dbe4cb94344e3a94 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-22soc/intel/xeon_sp: Move ACPI prototypes from chip.hMarc Jones
Prepare for common ACPI. Move the soc ACPI function prototypes from cpx and skx chip.h to include/soc/acpi.h. Change-Id: Ib7037cfb58825a2f6c25c122b95f72d5992dc04e Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-22src/soc/intel/xeon_sp/skx: Update get_iiostack_info()Marc Jones
Add Pci64BitResourceAllocation return value to get_iiostack_info(). This matches cpx function and is used in future de-duplication. Change-Id: I939c0101c751d9afced4ab33487958b93e59924c Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46307 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22soc/intel/xeon_sp/skx/: Clean up soc_util.cMarc Jones
Remove unused c_util.c helper functions and clean up soc_util.h in preparation for merging common code with cpx/. Change-Id: Iff825f64b665aadcf8eac8a404191c0b74f92abd Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46094 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22soc/intel/xeon_sp: Move common northbridge ACPI to nb_acpi.cMarc Jones
De-duplicate and prepare for common ACPI. Move common northbridge ACPI code to nb_acpi.c. There are a few differences between the skx and cpx defined FSP hob names and CSTACKS that are managed with #if (CONFIG(SOC_INTEL_*_SP)). Change-Id: I47ab1df3474d18643ef5ffc8199e09ea3dd32ccf Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22soc/intel/xeon_sp/cpx: Add soc_acpi_fill_fadt()Marc Jones
Prepare for common ACPI code. Make acpi_fill_fadt() match intel/commom/block/acpi/acpi.c function. Use soc_acpi_fill_fadt() to set cpx fadt->flags. Change-Id: I9c04dd478aa5e0f1467e63d06da094128edd9650 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45845 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21soc/intel/common: Fix/clean up USB4 PCIe virtual/generic driverDuncan Laurie
This driver is for the root port device and needs to reference the parent device for its ACPI scope. Similarly for the debug output it needs to use the parent device, and fall back to the chip name if config->desc is not provided in the devicetree. The UID property is removed. This value is not the same as the port number; according to some docs it should be unique but it is not fully clear what it should be tied to. Regardless, it is not used by the Thunderbolt driver in the kernel. I also renamed some functions/structures to be clear that this is just an ACPI driver for the PCIe root port and not a driver for the root port itself. As part of this I removed the PCI based resource operations and the scan bus function since this device does not have children itself. Finally I added a detailed comment with an example describing what the driver is for and what properties it generates. TEST=boot on volteer and ensure the USB4 root port device and properties are added to the SSDT as described by the comment in chip.h. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: Id6069a0fb7a0fc6836ddff1dbeca5915e444ee18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46544 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21soc/intel/common: Fix ACPI device name for USB4 DMA deviceDuncan Laurie
The USB4 host interface (DMA) devices need to use SA_DEVFN_* instead of SA_DEV_* when determining the ACPI name. The matching names are removed from the SOC-level ACPI name handler since they are provided by this driver now. TEST=boot on volteer and ensure TDM0 device is in the SSDT. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: If778bda82b80593452a590962dbffef6eff6484a Reviewed-on: https://review.coreboot.org/c/coreboot/+/46543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-21{cpu,soc}/intel: replace AES-NI locking by common implemenation callMichael Niewöhner
Deduplicate code by using the new common cpu code implementation of AES-NI locking. Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-21soc/intel,mb/*: get rid of legacy pad macrosMichael Niewöhner
Get rid of legacy pad macros by replacing them with their newer equivalents. TEST: TIMELESS-built board images match Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-21soc/intel: convert XTAL frequency constant to KconfigMichael Niewöhner
This converts the constant for the XTAL frequency to a Kconfig option. Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-21soc/intel/common: add Kconfig for PM Timer emulation supportMichael Niewöhner
Add a Kconfig for SoCs to indicate PM ACPI timer emulation support and select it by the appropriate SoCs. This Kconfig gets used in the follow-up changes. Change-Id: I6ded79221a01655f298ff92b8bd2afabd1d2a3ff Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19soc/intel/cnl: lock AES-NI feature if selectedMichael Niewöhner
Lock AES-NI (MSR_FEATURE_CONFIG) to prevent unintended changes of AES-NI enablement as precaution, as suggested in Intel document 325384-070US. Locking is enabled by default (as already done in SKL and Arrandale) and may be disabled by the newly introduced Kconfig in the parent change. Tested by checking the MSR. Change-Id: I79495bfbd3ebf3b712ce9ecf2040cecfd954178d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19soc/intel/*: drop useless XTAL shutdown qualification codeMichael Niewöhner
The XTAL shutdown (dis)qualification bit already unconditionally gets set to 1 by FSP for these platforms, making this code redundant. Change-Id: I7fa4afb0de2af1814e5b91c152d82d7ead310338 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46016 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19Revert "soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is ↵Michael Niewöhner
disabled" This reverts commit e5269a8fd975fa0cba0655cd41f7f8cc99a1feb8. Reason for revert: BIOS spec says, it's recommended to always enable emulation (regardless of the OS version). Change-Id: If0d7fa6f9766c7c4e2fa9e846c179adc6a4e1681 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-19soc/intel/skylake: Do not let FSP set the subsystem IDsBenjamin Doron
The subsystem ID registers are read/write-once. Writes by coreboot will not take effect if FSP sets them. Note that FSP sets one device ID for the SA devices and another for PCH devices. coreboot will copy individual vendor and device IDs if subsystem is not provided. Change-Id: I9157fb69f2a49dfc08f049da4b39fbf86614ace3 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-19soc/intel/cannonlake: Fix memory corruptionsJohn Zhao
Coverity detects source memory is overrun. Fix this issue by using the CONFIG_MAX_ROOT_PORTS value to avoid memory corruption. Found-by: Coverity CID 1429762 1429774 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Icc253eb9348d959a9e9e69a3f13933b7f97d6ecc Reviewed-on: https://review.coreboot.org/c/coreboot/+/46504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-19soc/intel/common/acpi: correct indentationMichael Niewöhner
Test: built google/volteer with `abuild --timeless` - SHA1 hashes match Change-Id: Ice6cef402dfcc33f1fc7fdced66d38c380d338e5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-19soc/intel/tigerlake: Reflow long linesSridhar Siricilla
Use the 96 character limit. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I43d77db1f81d72aa13f3a702abff490a68a52bd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-10-19soc/intel/xeon_sp/cpx: Implement platform_fsp_silicon_init_params_cbMarc Jones
platform_fsp_silicon_init_params_cb is called by the fsp driver and calls mainboard_silicon_init_params which sets the mainboard PCH GPIOs. Change-Id: Icf401e76741a6a7484295e999ddd566fe9510898 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46309 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Bryant Ou <bryant.ou.q@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-17cpu/intel,soc/intel: drop Kconfig for hyperthreadingMichael Niewöhner
Drop the Kconfig for hyperthreading to be always able to check at runtime if hyperthreading is supported. Having a Kconfig for this doesn't have any benefit. Change-Id: Ib7b7a437d758f7fe4a09738db1eab8189290b288 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-17intel/txt: Add `txt_get_chipset_dpr` functionAngel Pons
Due to platform-specific constraints, it is not possible to enable DPR by programming the MCH's DPR register in ramstage. Instead, assume it has been programmed earlier and check that its value is valid. If it is, then simply configure DPR in TXT public base with the same parameters. Note that some bits only exist on MCH DPR, and thus need to be cleared. Implement this function on most client platforms. For Skylake and newer, place it in common System Agent code. Also implement it for Haswell, for which the rest of Intel TXT support will be added in subsequent commits. Do not error out if DPR is larger than expected. On some platforms, such as Haswell, MRC decides the size of DPR, and cannot be changed easily. Reimplementing MRC is easier than working around its limitations anyway. Change-Id: I391383fb03bd6636063964ff249c75028e0644cf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46490 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-16include/cpu/x86: introduce new helper for (un)setting MSRsMichael Niewöhner
msr_set_bit can only set single bits in MSRs and causes mixing of bit positions and bitmasks in the MSR header files. Thus, replace the helper by versions which can unset and set whole MSR bitmasks, just like the "and-or"-helper, but in the way commit 64a6b6c was done (inversion done in the helper). This helps keeping the MSR macros unified in bitmask style. In sum, the three helpers msr_set, msr_unset and msr_unset_and_set get added. The few uses of msr_set_bit have been replaced by the new version, while the used macros have been converted accordingly. Change-Id: Idfe9b66e7cfe78ec295a44a2a193f530349f7689 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46354 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-16soc/intel/skylake: Rename PcieRpAspm devicetree configBenjamin Doron
This configuration option shares a name with the FSP UPD, but is enumerated differently. Change its name to minimise confusion about the options. Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-15soc/intel/xeon_sp: Add get_system_memory_map()Marc Jones
Prepare for common ACPI. Add get_system_memory_map() helper function to soc_util.c and use it in the SRAT ACPI code to match the cpx code. Change-Id: I54675b52aaf2999d884b3c20ccb143fbbf8b138a Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45847 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-15soc/intel/skylake: Configure L1 substates for PCH root portsBenjamin Doron
Exposes PcieRpL1Substates to devicetree to allow boards to override this configuration. Tested on an Acer Aspire VN7-572G (Skylake-U). Change-Id: I36150858485715016158595c832c142b0582ddb8 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-14soc/intel/skylake/cpu.c: Fix comment coding styleAngel Pons
This comment does not follow any of the styles outlined in the coding style page of the documentation. Adjust it to match the preferred style. Change-Id: Idf6d0ea69a08e378266b4256c476580889adfca8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46428 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14soc/intel/jasperlake: Enable CAR NEM enhanced modeAamir Bohra
TEST=Build and boot waddledoo board Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I067b13acfcea940e2e4ae6fc99b5d77458de35a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43705 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14soc/intel/broadwell/xhci.c: Align with Lynx PointAngel Pons
Change-Id: Idf40e2687b064c5ec7834e3c7d7ea9c8cb83c882 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45721 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14soc/intel/broadwell/smi.c: Drop unused functionsAngel Pons
These aren't used anywhere, so get rid of them. Change-Id: I267c0fd2e9d9d20ee852a73a9a916d85d6c65088 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45716 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14soc/intel/broadwell/pcie.c: Add some null checksAngel Pons
These are present in Lynx Point. Change-Id: I381f3cbf5fd18c952622f757135c0bde9ed6ed0d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45715 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14soc/intel/broadwell: Align cosmetics with Haswell/Lynx PointAngel Pons
Tested with BUILD_TIMELESS=1, Purism Librem 13v1 does not change. Change-Id: Icf41d9db20e492ec77a83f8413ac99a654d6c8ed Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45697 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14soc/intel/broadwell/igd.c: Rename to gma.cAngel Pons
This makes comparisons against Haswell a bit simpler. Change-Id: If1c937628f702c6765a5f36b6eaf4a3c3516359a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14soc/intel/common/block: Enable PMC IPC driverBrandon Breitenstein
In order for USB Type-C devices to be detected prior to loading Kernel PMC IPC driver API is needed to send IPC commands to the PMC to update connection/disconnection states. BUG=b:151731851 BRANCH=none TEST=built coreboot image and booted to Chrome OS Change-Id: Ide3528975be23585ce305f6cc909767b96af200f Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14soc/intel/alderlake: Enable TME for Alder LakeSubrata Banik
List of changes: 1. Select CONFIG_INTEL_TME from SoC Kconfig 2. Set TmeEnable FSP-M UPD based on Kconfig. TEST=Able to build and boot ADLRVP and verified from Chrome OS that TME is enable. Change-Id: I6992957bd2999a2efbae7b6d9c825c43bd118f72 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46296 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14soc/intel/tigerlake: Enable and use USB4 PCIe driverDuncan Laurie
This change enables the USB4/Thunderbolt common layer for Intel SOC, and enables the Intel USB4 PCIe driver. This moves the _DSD variables from the DSDT into the SSDT and allows them to be configured for each board if necessary. Change-Id: I2564512d951046e015c148db42fdaf2d4b8b81dd Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44917 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14soc/intel/common: Add SSDT generation for Intel USB4 PCIe portsDuncan Laurie
This driver will generate the ACPI _DSD for the USB4 PCIe root port properties instead of using static ASL. It assigns the USB4 port number and marks the port as external and hotplug capable. Change-Id: I7086b06346ce63fab6bef4077fb76ae1d30dc1eb Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44915 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14soc/intel/common/block: Add common support for USB4/ThunderboltDuncan Laurie
This common intel driver will add the requried ACPI _DSD entries for enabled USB4/Thunderbolt ports' DMA devices the SSDT instead of using hardcoded values in the DSDT. Change-Id: Ic4a58202d4569cf092ea21a4a83a3af6c42ce9d0 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-14soc/intel/common: Add PCI driver for USB4 portsTim Wawrzynczak
In order to enable SSDT generation for the DMA component of Intel USB4 ports, a PCI driver is required. This patch more or less adds a `scan_bus` callback that will handle non-PCI devices downstream. Change-Id: Ib9da051307b883eb99e500114378c9fd842ffc92 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-13soc/intel/common: rewrite and clarify the Legacy 8254 Timer KconfigMichael Niewöhner
The current Kconfig help text is confusing because it talks about enabling the Kconfig for disabling a UPD for disabling power gating. Rewrite and clarify the help text. Change-Id: I9637c549db1ce29f259708f316852fc2ae9e7c38 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-13mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devicesFurquan Shaikh
This change switches all mainboard devices to use drivers/wifi/generic instead of drivers/intel/wifi chip driver for Intel WiFi devices. There is no need for two separate chip drivers in coreboot to handle Intel and non-Intel WiFi devices since the differences can be handled at runtime using the PCI vendor ID. This also allows mainboard to easily multi-source WiFi chips and still use the same firmware image without having to distinguish between the chip drivers. BUG=b:169802515 BRANCH=zork Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-13src: Rename EM100Pro-specific SPI console Kconfig optionAngel Pons
To avoid confusion with `flashconsole` (CONSOLE_SPI_FLASH), prefix this option with `EM100Pro`. Looks like it is not build-tested, however. Change-Id: I4868fa52250fbbf43e328dfd12e0e48fc58c4234 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-12soc/intel: Configure PAVP at compile-timeBenjamin Doron
Expose configuration of Intel PAVP (Protected Audio-Video Path, a digital rights protection/management (DRM) technology for multimedia content) to Kconfig. Per the FSP default, this was always being enabled previously. Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-12soc/intel/cannonlake: Align cosmetics with Ice LakeAngel Pons
By ironing out cosmetic differences between Cannon Lake and Ice Lake, comparing actual code differences using a diff tool becomes simpler. Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical. Change-Id: I4d9f882f9f8af1245e937b0d47bc7e993547365f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-10-12soc/intel/jasperlake: Allow mainboard to override chip configurationKarthikeyan Ramasubramanian
Add a weak override function to allow mainboard to override chip configuration like GPIO PM. BUG=None TEST=Build and boot waddledee to OS. Ensure that the suspend/resume sequence works fine. Change-Id: I40fa655b0324dc444182b988f0089587e3877a47 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-12soc/intel/jasperlake: Correct SaGv mappingAamir Bohra
Jasper Lake support 3 Memory train frequencies low. mid and high. Update the SaGv configuration accordingly. Change-Id: I366de1ea7cf41c56b2954b8032c69bfba81058e2 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
2020-10-12soc/intel/common/block/smm: Fix compilation without intel uart codePatrick Rudolph
Allow to link the smihandler when not selecting SOC_INTEL_COMMON_BLOCK_UART. Change-Id: Iabca81c958d00c48e0616579cbba61d254c5eb68 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-10-12soc/intel/common/block/i2c: Scan bridge devices behind I2C controllersKarthikeyan Ramasubramanian
Currently devices behind I2C controllers are scanned using scan_smbus. This is done under the assumption that there are no bridge devices behind I2C controllers. In order to support I2C multiplexers which act as bridge devices and have devices behind them, scan the I2C controllers using scan_static_bus. BUG=b:169444894 TEST=Build and boot waddledee to OS. Ensure that all the bridge devices behind I2C controller are scanned and enabled. Change-Id: I9d8159a507683d8c56dd5e59d20c30ed7e4b2cab Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-12util: Add DDR4 generic SPD for H5ANAG6NCJR-XNCNick Vaccaro
Add SPD support for DDR4 memory part H5ANAG6NCJR-XNC. BUG=b:161772961 TEST=none Change-Id: I71e4de9a28f78bbf8c7de1fcafa3596276a5f2f9 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-12soc/intel/jasperlake: Remove GPIO community 2 from DSDTEvan Green
The kernel driver enumerates communities 0, 1, 4, and 5, and assigns these addresses based on the BARs enumerated by coreboot. Coreboot was defining communities 0, 1, 2, 4, and 5. This meant the kernel was not controlling GPIOs in communities 4 and 5, since the resources were wrong. Remove community 2 for now. We can add it back if the kernel ends up needing it. BUG=b:169444894 TEST=Test controlling GPP_E5, verify actually toggles register. Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: I823e1aa942cfccadde01b9371d481457ab088c31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46115 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-09soc/intel/tigerlake: Add chipset devicetreeDuncan Laurie
Add aliases for devices and set most of them to off with the exception of some essential devices. Set a default register value as an example. Change-Id: If50269808645ddc019e0d94fa8296df58ab7c367 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44038 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-09soc/intel/xeon_sp: Use generic config_tMarc Jones
Don't use the silicon-specific struct type to get common config options. Instead, use the generic config_t typedef. This allows the function to be moved to common code in upcoming patches. Change-Id: If80b678037b4d79387e0a0f722c540df4aae2416 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46057 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-09soc/intel/xeon_sp: Set CPU_ADDR_BITS to 46 for SKX and CPXChristian Walter
According to document number 338846 and 336062 this should be set to 46 bits. Change-Id: I0bbe6c962ffc7d5dc722f1cacf55bc0d0615db59 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-10-09soc/intel/xeon_sp/cpx: skip DRHD generation for non-PCIe stackJonathan Zhang
Without skipping of DRHD generation for non-PCIe stack, the OS kernel detects incorrect DMAR table with following messages: [ 0.561817] Your BIOS is broken; DMAR reported at address 0 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I098605daf12a264f390613581427ec722afcddaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/45887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-08soc/intel/jasperlake: Add VR Configuration settingsMeera Ravindranath
This CL fixes the CPU Throttling issue. BUG=b:167472333 TEST=Build and boot dedede and observe the slope and offset values getting updated in the fsp debug log Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I3fa32218040263f0abef8b9dd4c52efb31289fd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 18:16:29 +0000