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2022-01-14soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a81fd58df468e2711108a3243bf116e02986316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-14soc/intel/tigerlake: add devicetree option PcieRpSlotImplementedMichael Niewöhner
Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI bit set for any slots of already existing boards, add set the option PcieRpSlotImplemented=1 where appropriate. Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-14soc/intel/tgl: deduplicate the PCIe root port mapMichael Niewöhner
Make use of the helper introduced in the parent change to deduplicate the PCIe root port table. Change-Id: I2dae4e4caf0a7ba3662889f3b31da0c3c299bc92 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-14soc/intel/tgl/pcie_rp: add TGL-H supportMichael Niewöhner
Add TGL-H support for the recently introduced code for differentiating CPU and PCH root ports by adding the missing TGL-H port map. Change-Id: Id2911cddeb97d6c164662e2bef4fdeece10332a8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-13vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04Nick Vaccaro
The headers added are generated as per FSP v2511_04 Previous FSP version was v2471_02 Changes include: - UPDs description update in FspsUpd.h and FspmUpd.h - Adjust UPD Offset in FspmUpd.h - Name change of UPDs in FspmUpd.h and FspsUpd.h - Copyright year is updated in FspmUpd.h and FspsUpd.h - Updated spd_upds and dq_upds structure variables in meminit.c - Updated structure member of s_cfg->LpmStateEnableMask to PmcLpmS0ixSubStateEnableMask in fsp_params.c BUG=b:213959910 BRANCH=None TEST=Build and boot brya Cq-Depend: chrome-internal:4448696, chrome-internal:4445910 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com> Change-Id: I39646c6812afbf622171361b8206daeacdaafac0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-12soc/intel/common/gpio: Fix cosmetic issue with `gpio_lock_pads`Subrata Banik
This patch replaces hardcoded `4` (next offset Tx state) with `sizeof(uint32_t)` for calculating 'Tx state offset'. Also, add checks to detect the specific GPIO lock action between `LOCK_CONFIG` or 'LOCK_TX'. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iff712b16808e0bc99c575bb2426a4f84b89fdb73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-12soc/intel/tigerlake: Implement function to map physical port to EC portjzhao80
Currently coreboot and EC had different logic to interpret TCSS port number which would break retimer update functionality since coreboot would pass wrong port information to EC. This change clones the implementation on Alder Lake which converts the phyiscal port mapping to EC's abstract port mapping. BUG=b:207057940 BRANCH=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: If4451598dbb83528ae6d88dbc1b65c206f24fe1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-12soc/intel/tgl/pcie_rp: correct root port mapMichael Niewöhner
TGL-LP only has 12 root ports, not 20. Correct the port map. Change-Id: I3f5c69a2e7e3a2b8292c81beeac4ea6c7279d4b4 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-01-11soc/intel/apl: Use Kconfig to disable HECI1Subrata Banik
This patch makes DISABLE_HECI1_AT_PRE_BOOT=y default for Apollo Lake and ensures disable_heci1() is guarded against this config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7ac0cad97fcd42b2c6386693319d863352356864 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-11soc/intel/alderlake: Factor out A0 stepping workaroundAngel Pons
Move the `configure_pmc_descriptor()` function to SoC scope instead of having two identical copies in mainboard scope. Add a Kconfig option to allow mainboards to decide whether to implement this workaround. Change-Id: Ib99073d8da91a93fae9c0cebdfd73e39456cdaa8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-11soc/intel/apl: Rework on CPU privilege level implementationSubrata Banik
This patch migrates common code API into SoC specific implementation to drop CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK, it's MSR 0x120 and CNL onwards it's MSR 0x151. Also, include `soc/msr.h` in cpu.h to fix the compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0b6f39509cc5457089cc15f28956833c36b567ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/60898 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-10src/soc: Remove unused <stdlib.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <stdlib.h>' -- src/) <(git grep -l 'memalign(\|malloc(\|calloc(\|free(' -- src/) Change-Id: I08e1a680de9bfcc7d74e88a15abe9eef327b4961 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-01-10src/soc/intel: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: I2ca3a7487cbe75f9bec458f4166378a07b833bb5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-10soc/intel/common/cse: Add config to disable HECI1 at pre-bootSubrata Banik
This patch adds a config to let mainboard users choose the correct state of HECI1(CSE) device prior to handing off to payload. `DISABLE_HECI1_AT_PRE_BOOT` config to make HECI1 function disable at pre-boot. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7e127816c506df3ac0cf973b69021d02d05bef4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/60721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-10soc/intel/common: Add missing space before }Paul Menzel
Fixes: 5b94cd9e9d ("soc/intel/common: Include Alder Lake-N device IDs") Change-Id: I24c2bdb9e4a9eb873b52668a41f4c0e944ed7818 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-10soc/intel/alderlake: Update the ADL-P SKU parameters for VR domainsCurtis Chen
We support all the ADL-P 15W/28W/45W SKU's and map them with the latest VR configurations. These config values are generated by iPDG application with ADL-P platform package tool. RDC Kit ID for the iPDG tools * Intel(R) Platform Design Studio Installer: 610905 * Intel(R) Platform Design Studio - Libraries: 613643 * Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345 * Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261 BUG=b:211365920 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: Ida7a6df0422a9a3972646cb3bdd0112b5efa2755 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-09soc/intel/{icl,tgl,jsl,ehl}: enable ACPI CPPC entriesMichael Niewöhner
Enable CPPC entries generation, needed for Intel SpeedShift. This can be tested by checking sysfs in Linux: $ grep . /sys/devices/system/cpu/cpu?/acpi_cppc/*perf The output should look like this, while the values may differ: /sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf:28 /sys/devices/system/cpu/cpu0/acpi_cppc/lowest_nonlinear_perf:5 /sys/devices/system/cpu/cpu0/acpi_cppc/lowest_perf:1 /sys/devices/system/cpu/cpu0/acpi_cppc/nominal_perf:24 /sys/devices/system/cpu/cpu1/acpi_cppc/highest_perf:28 /sys/devices/system/cpu/cpu1/acpi_cppc/lowest_nonlinear_perf:5 ... Change-Id: I910b4e17d4044f1bf1ecfa0643ac62fc7a8cb51b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
2022-01-08soc/intel/xeon_sp: Don't handle FSP reserved memory explicitlyArthur Heymans
FSP reserved memory is allocated inside cbmem which already gets marked as a reserved memory region, so there is no need to do this explicitly. Change-Id: I39ec70bd9404d7bc2a4228c4364e4cc86f95d7c1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-01-07soc/intel/common/block/pcie/rtd3: Update ACPI methods for CPU PCIe RPsTim Wawrzynczak
The PMC IPC method that is used for RTD3 support expects to be provided the virtual wire index instead of the LCAP PN for CPU PCIe RPs. Therefore, use the prior patches to update pcie_rp for CPU RPs. Note that an unused argument to pcie_rtd3_acpi_method_status() was also dropped. BUG=b:197983574 TEST=add rtd3 node under pcie4_0 in overridetree for brya0, boot and inspect the SSDT to see the PMC IPC parameters are as expected for the CPU RP, and the ModPhy power gating code is not found in the AML for the PEG port. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: Tim Crawford <tcrawford@system76.com> Change-Id: I84a1affb32cb53e686dbe825d3c3a424715df873 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60183 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-07soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDsTim Wawrzynczak
The Alder Lake chip.h file has pcie_rp_config entries for the CPU PCIe ports, but the UPDs are not set. This patch hooks up those config structs to the appropriate FSP-S UPDs. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ibb2375e66d53b4b7567dbe88b941cd720fdad927 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-07soc/intel/common/blk/memory: Make mixed topo workAngel Pons
When using a mixed memory topology with DDR4, it's not possible to boot when no DIMMs are installed, even though memory-down is available. This happens because the DIMM SPD length defaults to 256 when no DIMM SPD is available. Relax the length check when no DIMMs are present to overcome this problem. Tested on system76/lemp10. Unit boots with and without DIMM installed. Change-Id: I1cabf64fade1c06a44b6c3892659d54febc7a79a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Tested-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2022-01-07soc/intel/alderlake: Check clkreq overlapKane Chen
In some cases, partner may assign same clkreq on more than one devices. This could happen when one device is in baseboard dev tree and another one is in override dev tree. This change adds a clkreq overlap check and shows a warning message TEST=On brya, assigned one clkreq to 2 devices and found the warning message Change-Id: I2f701a19118f4702c227b17e43b6551591d9b344 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-06soc/intel/alderlake: Add minimal ACPI support for PEG portsTim Wawrzynczak
Add minimal Device entries with just an _ADR for each of the PEG ports for P and M chipsets (N does not have any PEG ports). Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Id1009004969729eddf7005fa190f5e1ca2d7b468 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-06soc/intel/alderlake: Add soc_get_cpu_rp_vw_idx() functionTim Wawrzynczak
The PMC IPC method used to enable/disable PCIe srcclks uses the LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC command expects the RP number to be its "virtual wire index" instead. This new function returns this virtual wire index for each of the CPU PCIe RPs. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I5e9710f0d210396f9306b948d9dce8b847300147 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-06soc/intel/tigerlake: Add soc_get_cpu_rp_vw_idx() functionTim Wawrzynczak
The PMC IPC method used to enable/disable PCIe clk sources uses the LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC command expects the RP number to be its "virtual wire index" instead. This new function returns this virtual wire index for each of the CPU PCIe RPs. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7aa14a634dcd90c4817009db970fb209ae02c63d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-06soc/intel/common/gpio: Skip GPP pad lock config if config is not setSubrata Banik
Don't perform GPP lock configuration if SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS config is not selected. This patch fixes a compilation issue when APL/GLK boards are failing while gpio_lock_pads() function is getting called from IA common gpio block. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I392dc2007dba8169e480f82b58b7f0a1578bb09f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-06soc/intel/common/gpio: Modify pad_config.pad type from `int` to 'gpio_t'Subrata Banik
This patch modifies struct pad_config.pad type from `int` to 'gpio_t' as pad offset inside GPIO community is unsigned type and also to maintain parity with `struct gpio_lock_config.pad` type. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I15da8a1aff2d81805ba6584f5cc7e569faf456e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-06soc/intel/common/gpio: Rename struct gpio_lock_config.gpio to .padSubrata Banik
This patch renames struct gpio_lock_config variable `gpio` to `pad`, to represent the pad offset within the GPIO community. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6bed99c401435c96c9543f99406a934d7141c575 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-06soc/intel/alderlake: Fix GPIO reset mapping as per GPIO BWGSubrata Banik
This patch fixes the documentation discrepancy of GPIO reset type between PCH EDS and GPIO BWG. As per GPIO BWG, there are four GPIO reset types in Alder Lake as below: - Power Good - (Value 00) - Deep - (Value 01) - Host Reset/PLTRST - (Value 10) - RSMRST for GPD/Reserved for GPP - (Value 11) Hence, created two different reset types for `GPP` and `GPD`. Also, replaced PAD_CFG0_LOGICAL_RESET_x macros with PAD_RESET(). BUG=b:213293047 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4b8742c7a0cc1dc420e3e22e34a16355294ed61b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-05src/soc/intel: Remove unused <delay.h>Elyes HAOUAS
Change-Id: Id8e6221a9801d5198171dc9cd564000d19720a42 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-05soc/intel: Remove unused <string.h>Elyes HAOUAS
Found using following command: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy(\|memmove(\|memset(\|memcmp(\|memchr(\|strdup(\|strconcat(\|strnlen(\|strlen(\|strchr(\|strncpy(\|strcpy(\|strcmp(\|strncmp(\|strspn(\|strcspn(\|strstr(\|strtok_r(\|strtok(\|atol(\|strrchr(\|skip_atoi(\|vsnprintf(\|snprintf(' -- src/) Change-Id: Iae90ff482f534d8de2a519619c20a019d054e700 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-04soc/intel/common/acpi/pep: Use correct size_t length modifierPaul Menzel
Building an image for the Purism Mini v2 with `x86_64-linux-gnu-gcc-11` fails with the format warning below as the size of size_t differs between 32-bit and 64-bit. CC ramstage/soc/intel/common/block/acpi/pep.o src/soc/intel/common/block/acpi/pep.c: In function 'read_pmc_lpm_requirements': src/soc/intel/common/block/acpi/pep.c:57:50: error: format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'size_t' {aka 'unsigned int'} [-Werror=format=] 57 | printk(BIOS_ERR, "Failed to retrieve LPM substate registers" | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 58 | "from LPM, substate %lu, reg %lu\n", i, j); | ~ | | | size_t {aka unsigned int} src/soc/intel/common/block/acpi/pep.c:58:62: note: format string is defined here 58 | "from LPM, substate %lu, reg %lu\n", i, j); | ~~^ | | | long unsigned int | %u src/soc/intel/common/block/acpi/pep.c:57:50: error: format '%lu' expects argument of type 'long unsigned int', but argument 4 has type 'size_t' {aka 'unsigned int'} [-Werror=format=] 57 | printk(BIOS_ERR, "Failed to retrieve LPM substate registers" | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 58 | "from LPM, substate %lu, reg %lu\n", i, j); | ~ | | | size_t {aka unsigned int} src/soc/intel/common/block/acpi/pep.c:58:71: note: format string is defined here 58 | "from LPM, substate %lu, reg %lu\n", i, j); | ~~^ | | | long unsigned int | %u The variables `i` and `j` are of type size_t, so use the corresponding length modifier `z`. Fixes: 2eb100dd ("soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM") Change-Id: I27bce0a6c62b1c1ebbca732761de2f59b042a5d4 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-04soc/intel/common: irq: Use correct size_t length modifierPaul Menzel
Building an image for the Purism Mini v2 with `x86_64-linux-gnu-gcc-11` fails with the format warning below as the size of size_t differs between 32-bit and 64-bit. CC ramstage/soc/intel/common/block/irq/irq.o src/soc/intel/common/block/irq/irq.c: In function 'assign_fixed_pirqs': src/soc/intel/common/block/irq/irq.c:186:90: error: format '%lu' expects argument of type 'long unsigned int', but argument 5 has type 'size_t' {aka 'unsigned int'} [-Werror=format=] 186 | printk(BIOS_ERR, "ERROR: Slot %u, pirq %u, no pin for function %lu\n", | ~~^ | | | long unsigned int | %u 187 | constraints->slot, fixed_pirq, i); | ~ | | | size_t {aka unsigned int} CC ramstage/soc/intel/common/block/gspi/gspi.o CC ramstage/soc/intel/common/block/graphics/graphics.o CC ramstage/soc/intel/common/block/gpio/gpio.o CC ramstage/soc/intel/common/block/gpio/gpio_dev.o The variable `i` is of type size_t, so use the corresponding length modifier `z`. Fixes: b59980b54e ("soc/intel/common: Add new IRQ module") Change-Id: I09f4a8d22a2964471344f5dcf971dfa801555f4a Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-04sb/intel: Use `bool` for PCIe coalescing optionAngel Pons
Retype the `pcie_port_coalesce` devicetree options and related variables to better reflect their bivalue (boolean) nature. Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-03soc/intel/alderlake: Add option to make MRC log silentSubrata Banik
Typically, FSP-M aka MRC debug log level defaults to `3` meaning prints all `Load, Error, Warnings & Info` messages. Sometimes it's too much information to parse even when users aren't required to have such detailed information hence, implement `fsp_map_console_log_level()` that maps coreboot console log level to FSP-M debug log level and suppress verbose MRC debug messages unless caller selects `HAVE_DEBUG_RAM_SETUP` config and then the user can enable `DEBUG_RAM_SETUP`. TEST=FSP-M debug log suggested default `SerialDebugMrcLevel` UPD value is `2`. While this patch selects `HAVE_DEBUG_RAM_SETUP` and user to select `DEBUG_RAM_SETUP` config to override `SerialDebugMrcLevel` UPD value to '5' aka verbose. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iea3b32feca0893a83fdf700798b0883d26ccc718 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-02soc/intel/{adl,ehl,tgl}: Rename spi_protection_mode to mfg_modeSubrata Banik
Since TGL `spi_protection_mode` bit replaces the previous `manufacturing mode` without changing the offset and purpose of this bit. This patch renames to `manufacturing mode` aka `mfg_mode` to maintain the parity with other PCHs as part of IA-common code. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6d00f72ce7b3951120778733066c351986ccf343 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-02soc/intel/common/blk/crashlog: Drop some new linesSubrata Banik
Remove unnecessary new lines in crashlog code. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0920f563d6fdf9414eab86796cedcac83173dba3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-01soc/intel/tigerlake/fsp_params.c: Use `is_dev_enabled()`Felix Singer
Change-Id: I3e79f637bedec0bdca1312291328b2385bd027a7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-01src: Use 'stdint.h' when appropriateElyes HAOUAS
Change-Id: I1df255d55b8f43a711d836c2565c367bd988098a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-01src: Remove duplicated includesElyes HAOUAS
Change-Id: I50cdffca34a6150ac11c3e83e1a603b766d1b84e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-01src: Drop duplicated includesElyes HAOUAS
<types.h> already provides <commonlib/bsd/cb_err.h>, <limits.h>, <stdbool.h>, <stdint.h> and <stddef.h> headers. Change-Id: I700b3f0e864ecce3f8b3b66f3bf6c8f1040acee1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-01soc/intel/apollolake/acpi: Replace Decrement() with ASL 2.0 syntaxFelix Singer
Replace `Decrement (a)` with `a--`. Change-Id: I523c6b14c127ec7c0eb41078fb2eb92f42d74bd5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-01soc/intel/jasperlake: Add CdClock frequency configSimon Yang
Add a devicetree setting to configure the CdClock (Core Display Clock) frequency through a FSP UPD. Because the value for this UPD's default setting is non-zero and devicetree settings default to 0 if not set, adapt the devicetree values so that the value for the UPD's default setting is used when the devicetree setting is zero. Also update the comment describing the FSP UPD in the header file FspsUpd.h to match the correct CdClock definition. BUG=b:206557434 BRANCH=dedede TEST=Build fw and confirm FSP setting are set properly by log Signed-off-by: Simon Yang <simon1.yang@intel.com> Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-01soc/intel/apollolake/acpi: Replace Increment() with ASL 2.0 syntaxFelix Singer
Replace `Increment(a)` with `a++`. Change-Id: I40d5df41e2e077cb9d3e7f3945f0dbae18382a28 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-01soc/intel/apollolake/acpi: Replace Divide(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Divide (a, b)` with `a / b`. Change-Id: Ifb377f0abb50a736aa3aa53a11d45bee65488c4c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60569 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-01soc/intel/apollolake/acpi: Replace Multiply(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b)` with `a * b`. Change-Id: I42076d361045c224b99e111e34de7539420b8a52 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-01soc/intel/cannonlake/acpi: Replace Multiply(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b)` with `a * b`. Change-Id: I6dc9f57773754e89df4b4ffd088a4693af0452e3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-31soc/intel/apollolake/acpi: Replace Add(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b)` with `a + b`. Change-Id: Id465558f054494d3273d5cd6077476d878d7c183 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60504 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-31soc/intel/cannonlake/acpi: Replace Add(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b)` with `a + b`. Change-Id: I90dc0ecb1e3f16874a72cdf01afb097d4e7b6076 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60503 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-31soc/intel/skylake/acpi: Replace Add(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b)` with `a + b`. Change-Id: Id35c24663f529238fe17721b99ad8e93a4f5433f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-31soc/intel/apollolake/acpi: Replace Subtract(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Subtract (a, b)` with `a - b`. Change-Id: I3b0ee96b5a1e9bf242efc14a24f745fd8ba0cd97 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-31soc/intel/apollolake/acpi: Replace Add(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b, c)` with `c = a + b`. Change-Id: I4d6039affd9688a2e795d69f699d5baf688ba2e4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-31soc/intel/cannonlake/acpi: Replace Add(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b, c)` with `c = a + b`. Change-Id: Ibc5aeb5e8d85556d7564033ec92deb5b2dae093d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-31soc/intel/apollolake/acpi: Replace Subtract(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Subtract (a, b, c)` with `c = a - b`. Change-Id: I8c98f4e3c3aed6209fd36398134a36778a560708 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-30soc/intel/cannonlake/acpi: Replace Subtract(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Subtract (a, b, c)` with `c = a - b`. Change-Id: I764bf6c8b068c1b7471a28aa064f7a3a47d7811e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-30soc/intel/cannonlake/acpi: Replace LAnd() with ASL 2.0 syntaxFelix Singer
Replace `LAnd (a, b)` with `a && b`. Change-Id: I259bd218ac3f786cef6e05386f6dc55ccaf6b911 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60468 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-30soc/intel/apollolake/acpi: Replace LAnd() with ASL 2.0 syntaxFelix Singer
Replace `LAnd (a, b)` with `a && b`. Change-Id: I4bbbc4888fc134b3862bb956b2ee17a72f282584 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60466 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-30soc/intel/alderlake: Fix incorrect comment about debug consentSubrata Banik
This patch makes the debug consent for ADL comment default value comment proper. Default `Platform Debug Consent` value is 2: Enabled (Al probes and tracehub. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic5eeb4f02d051dc1efba2deaecb51cbc7eac51f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-12-30soc/intel/skylake/acpi: Use ASL 2.0 syntax to access arraysFelix Singer
Replace Index(FOO, 1337) with FOO[1337]. Change-Id: I3bc780a60e34fb72020d8dbba3db0ed096fa930d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-26soc/intel/{skl,cnl}: Guard USB macro parametersAngel Pons
Add parentheses around the parameter of the `USB_PORT_WAKE_ENABLE` macro to prevent unintentional operator precedence problems. Change-Id: I61fbacc129cbfb42ade7e64ee40cd07c98d87683 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-23soc/intel/alderlake: Add timestamp for cse_fw_syncSridhar Siricilla
The patch add timestamp around cse_fw_sync(). TEST=Verified on Brya, cbmem -t: 948:starting CSE firmware sync 1,381,577 (45,227) 949:finished CSE firmware sync 1,459,513 (77,936) Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Idba11417e0fc7c18d0d938a4293ec3aff1537fb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-12-22soc/intel/alderlake: remove SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADSScott Chao
This causes the I2C touchpad device to stop working after warm reboot. BUG=b:210701402 BRANCH=none TEST=after warm reboot, the touchpad still works. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I106ddc96c3185656d3f1fbcd45f198d2d46f3f4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60126 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-20soc/intel/common: Do not trigger crashlog on all resets by defaultCurtis Chen
Crashlog has error records and PMC reset records two parts. When we send ipc cmd "PMC_IPC_CMD_ID_CRASHLOG_ON_RESET", PMC reset record is enabled. At each warm/cold/global reset, crashlog would be triggered. The cause of this crash would be "TRIGGER_ON_ALL_RESETS", it is used to catch unknown reset reason. At the same time, we would see [Hardware Error] in the kernel log. If we default enable TRIGGER_ON_ALL_RESETS, we would have too many false alarm. Now we disable PMC reset records part by default. And we could enable it when we need it for the debug purpose. The generated bert dump is under /var/spool/crash/, we could check this path to verify this CONFIG disable/enable status. BUG=b:202737385 TEST=No new bert dump after a warm reset. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: I3ec4ff3c8a3799156de030f4556fe6ce61305139 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-17soc/intel/denverton_ns: Use `popcnt()` helperAngel Pons
Use the `popcnt()` helper instead of manually counting the number of set bits in the first `CONFIG_MAX_CPUS` bits with a loop. Also, use unsigned types to store the number of active/total cores. Change-Id: Iae6b16991fcf07c9ad67d2b737e490212b8deedd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-16Spell *Boot Guard* with a space for official spellingPaul Menzel
See for example Intel document *Secure the Network Infrastructure – Secure Boot Methodologies* [1]. Change all occurrences with the command below: $ git grep -l BootGuard | xargs sed -i 's/BootGuard/Boot Guard/g' [1]: https://builders.intel.com/docs/networkbuilders/secure-the-network-infrastructure-secure-boot-methodologies.pdf Change-Id: I69fb64b525fb4799bcb9d75624003c0d59b885b5 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-15soc/intel/denverton_ns: Fix MRC_RW_CACHEKyösti Mälkki
It is required to set WPD (Write Protect Disable) bit to make it possible to use MRC_RW_CACHE region with CACHE_MRC_SETTINGS=y. Change-Id: Iacab44b00d08c9bdc18bc3bdcb88833634c0b02e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-15soc/intel/denverton_ns: Use common SMBus support codeKyösti Mälkki
Change-Id: I233d198b894f10fbf0042a5023ae8a9c14136513 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-15soc/intel/baytrail,denverton_ns: Call setup_lapic()Dmitry Ponamorev
A custom board with soc/intel/denverton_ns does not respond to the keyboard and does not boot from the sata/USB disks. Last post code 0x7b and the last line that is displayed at log from SeaBIOS is: All threads complete. The issue is gone when adding setup_lapic() call to configure EXTINT delivery of i8259 originated interrupts for the LAPIC. Replicate call from other soc/ and make the call for both BSP and AP CPUs. Similar change was done for soc/intel/braswell in commit b4f57bb3cac3ab29b9fa9c526ad4358faffb77a1. Signed-off-by: Dmitry Ponamorev <dponamorev@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: Iafbfb733d0be546e0e2fba937fd1d262785aa54d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-13soc/intel/common/cse: Update help text for CSE_OEMP_FILEravindr1
The OEM may create and sign an Audio component to extend the Audio capability provided by Intel. The manifest is then signed, and the signature and public key are entered into the header of the manifest to create the final signed component binary. This creates a secure verification mechanism where firmware verifies that the OEM Key Manifest was signed with a key owned by a trusted owner. Once OEM KM is authenticated, each public key hash stored within the OEM KM is able to authenticate the corresponding FW binary. Link to the Document: https://www.intel.com/content/www/us/en/secure/design/confidential/software-kits/kit-details.html?kitId=689893 ADL_Signing_and_Manifesting_User_Guide.pdf BUG=b:207820413 TEST:none Signed-off-by: ravindr1 <ravindra@intel.com> Change-Id: Id52b51ab1c910d70b7897eb31add8287b5b0166f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-13soc/intel/common/block/cpu/car/exit_car_fsp.S: Align stackArthur Heymans
Change-Id: I6b5864cfb9b013559cd318bc01733ba4d3792e65 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-13soc/intel/alderlake: Implement function to map physical port to EC portMAULIK V VAGHELA
Currently coreboot and EC had different logic to interpret TCSS port number which would break retimer update functionality since coreboot would pass wrong port information to EC. To correct this, coreboot has implemented function which converts coreboot physical port mapping to EC's abstract port mapping. Each SoC needs to implement this weak function since only SoC will have correct physical port mapping data. This function should resolve issue of port mismatch since coreboot will count only enabled ports and provide correct EC port number in return. BUG=b:207057940 BRANCH=None TEST=Check if retimer update works on Redrix and correct port information is passed to EC. Change-Id: I3735b7c7794b46123aba3beac8c0268ce72d658c Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-13soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3Tim Wawrzynczak
For additional power savings during RTD3, the PMC can power-gate the ModPHY lanes that are used by the PCH PCIe root ports. Therefore, using the previous PCIe RP-type detection functions, implement ModPHY PG support for the PCH PCIe RPs. This involves: 1) Adding a mutex so only one power resource accesses the PMC registers at a time 2) OperationRegions to access the PMC's PG registers 3) Adding ModPHY PG enable sequence to _OFF 4) Adding ModPHY PG disable sequence to _ON BUG=b:197983574 TEST=50 S0ix suspend/resume cycles on brya0 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I19cb05a74acfa3ded7867b1cac32c161a83b4f7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59855 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-13soc/intel/alderlake: Define soc_get_pcie_rp_typeTim Wawrzynczak
In order to distinguish PCH from CPU PCIe RPs, define the soc_get_pcie_rp_type function for Alder Lake. While we're here, add PCIe RP group definitions for PCH-M chipsets. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7438513e10b7cea8dac678b97a901b710247c188 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-12-13soc/intel/tigerlake: Define soc_get_pcie_rp_typeTim Wawrzynczak
In order to distinguish PCH from CPU PCIe RPs, define the soc_get_pcie_rp_type function for Tiger Lake. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-12-13drivers/intel/mipi_camera: Add ACPI entry to provide silicon type infoSugnan Prabhu S
Add entry in ACPI table under IPU device to provide silicon type information to IPU driver. IPU kernel driver can decide the type of firmware to load based on this information. BUG=b:207721978 BRANCH=none TEST=Check for the ACPI entry in the SSDT after booting to kernel Change-Id: I4e0af1dd50b9c014cae5454fcd4f9f76d0e0a85f Cq-Depend: chromium:3319905 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-13soc/intel/cannonlake: Configure common FSP memory settings only onceFelix Singer
`meminit_memcfg()` does common memory configuration, which is not specific to each DIMM. Thus, move it out of the for-loop and call it once. Change-Id: If74875b45cd0d7a759883eaf564505ebf281bed5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-12soc/intel/elkhartlake: Hook up public microcodeArthur Heymans
Change-Id: I1d975713129d0a7bce823232d225ed17ee28a04d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-12soc/intel/jasperlake: Hook up public microcodeArthur Heymans
Change-Id: I9e511de5e5b79936ed09538b3877655f78de15a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-12soc/intel/cannonlake: Rename SA_DEV_SLOT_DSPFelix Singer
Device 4 was introduced with a wrong name, since it is the SA Thermal Subsystem and it does nothing have to do with DSP. Thus, rename it accordingly. Change-Id: I8edc764413df5f323098e60d0a3f0f87a7e656cb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60049 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-10soc/intel/{skylake/cannonlake}: Fix bug in vr_configAngel Pons
The `cpu_get_power_max()` function returns the TDP in milliwatts, but the vr_config code interprets the value in watts. Divide the value by 1000 to fix this. This also fixes an integer overflow when `cpu_get_power_max()` returns a value greater than 65535 (UINT16_MAX). Change-Id: Ibe9e0db6762eee5cc363f8b371c8538eb92f6308 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-10soc/intel/cse: config to enable oem key manifestRavindra N
CB change will enable the CSE region sub-partition OEMP, where the OEMP binary will be stitched. OEM KM has Audio FW's key hash. So, CSE uses this information to authenticate Audio FW. BUG=b:207820413 TEST: Boot to kernel and check for the audio authentication is successful localhost ~ # aplay -l **** List of PLAYBACK Hardware Devices **** card 0: sofrt5682 [sof-rt5682], device 0: max357a-spk (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 1: Headset (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 2: HDMI1 (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 3: HDMI2 (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 4: HDMI3 (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 5: HDMI4 (*) [] Subdevices: 1/1 Subdevice #0: subdevice #0 Cq-Depend: chrome-internal:4286038 Signed-off-by: Ravindra N <ravindra@intel.corp-partner.google.com> Change-Id: I3620adb2898efc002104e0ba8b2afd219c31f230 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2021-12-09soc/intel/tigerlake: Hook up DPTF device to devicetreeFelix Singer
Hook up `Device4Enable` FSP setting to devicetree state and drop its redundant devicetree setting `Device4Enable`. The following mainboards enable the DPTF device in the devicetree despite `Device4Enable` is not being set. * google/deltaur Thus, set it to off to keep the current state unchanged. Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09soc/intel/tigerlake: Drop unused SataEnable settingFelix Singer
`SataEnable` is set by some boards, but it doesn't have any effect since its related FSP option is hooked up to the devicetree state. Thus, drop it. Change-Id: Id645bfcade7ca1d495fb8df538113b3d10392a82 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-09soc/intel/tigerlake: Hook up SMBus device to devicetreeFelix Singer
Hook up `SmbusEnable` FSP setting to devicetree state and drop its redundant devicetree setting `SmbusEnable`. The following mainboards enable the SMBus device in the devicetree despite `SmbusEnable` is not being set. * google/deltaur * starlabs/laptop Thus, set it to off to keep the current state unchanged. Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09soc/intel/alderlake: Fix value of SA_DEVFN_CPU_PCIE1_0Tim Wawrzynczak
The macro was defined using PCH_DEV_SLOT_CPU_1, which doesn't exist, so replace it with the correct value of SA_DEV_SLOT_CPU_1. Change-Id: If6d294d681907c51ac5678c9251364d4d6df4329 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-12-08soc/intel/common/pch: Fix return value documentation for CHIPSET_LOCKDOWNJingle Hsu
Fixed according to the declaration in soc/intel/common/block/include/intelblocks/cfg.h. Change-Id: I50dbc00806fefda8f4dac8bfa21dc714a9504566 Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-07soc/intel/alderlake: enable gpio lockingNick Vaccaro
This change supplies a list of ADL gpios that are connected to non-host (x86) controllers and should be locked after initial configuration. Set SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS to enable GPIO locking. BUG=b:210430600 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that brya0 boots successfully to kernel. Change-Id: I457bab39f945ab31a89542c6498a73af70cbf9ee Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-07soc/intel/common: add generic gpio lock mechanismNick Vaccaro
For added security, there are some gpios that an SoC will want to lock once initially configured, such as gpios attached to non-host (x86) controllers, so that they can't be recofigured at a later point in time by rogue code. Likewise, a mainboard may have some gpios connected to secure busses and/or devices that they want to protect from being changed post initial configuration. This change adds a generic gpio locking mechanism that allows the SoC to export a list of GPIOs to be locked down and allows the mainboard to export a list of GPIOs that it wants locked down once initialization is complete. Use the SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS Kconfig option to enable this feature. BUG=b:201430600 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify brya0 boots successfully to kernel. Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-06soc/intel/alderlake: Add ADL-P 6+8+2 (28W) VR configCurtis Chen
We only have ADL-P 6+8+2 (45W) VR configuration now. Based on the power map, fill in correct ADL-P 6+8+2 (28W) VR configuration. BUG=b:202486131 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: Ie8dbd95b2d8e49b5898b2a97aff72e0e64868c8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-06soc/intel/alderlake: Add support for ADL-N CPU TypeUsha P
Add Alder Lake-N case for adl_cpu_type and get_supported_lpm_mask. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: If2917ac356fd80f84bcaf70ed710d329e77f7a6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-12-06soc/intel/common: Refactor cpu_set_p_state_to_max_non_turbo_ratioSridhar Siricilla
The patch refectors cpu_set_p_state_to_max_non_turbo_ratio(). The function is updated to use cpu_get_max_non_turbo_ratio(). TEST=Build the code for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: If73df17faaf7b870ae311460a868d52352683c0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-06soc/intel/common: Add CPU related APIsSridahr Siricilla
The patch defines below APIs : cpu_is_hybrid_supported() : Check whether CPU is hybrid CPU or not. cpu_get_bus_frequency() : Get CPU's bus frequency in MHz cpu_get_max_non_turbo_ratio() : Get CPU's max non-turbo ratio cpu_get_cpu_type() : Get CPU type. The function must be called if executing CPU is hybrid. TEST=Verified the APIs on the Brya board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I680f43952ab4abce6e342206688ad32814970a91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-06soc/intel: Move enum pcie_rp_type to intelblocks/pcie_rp.hTim Wawrzynczak
This enum is useful to have around for more than just the one file, so move it to a common header file, and while we're there, also add an option for UNKNOWN. TEST=boot test on brya0 Change-Id: I9ccf0ed9504dbf6c60e521a45ea4b916d3dcbeda Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-12-03soc/intel/adl: Add override skip_cse_sub_part_update() for alderlakeKrishna Prasad Bhat
Check the Alderlake CPU ID to determine if cse sub-paritition update is required or not. BUG=b:202143532 Change-Id: Icae21dad56ed4a1edea1f641b3d5bccc3943f831 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03soc/intel/common: Add support for CSE IOM/NPHY sub-parition updateKrishna Prasad Bhat
This patch adds the following support to coreboot 1. Kconfig to add IOM/NPHY in the COREBOOT/FW_MAIN_A/FW_MAIN_B partition of BIOS 2. Helper functions to support update. Pre-requisites to enable IOM/NPHY FW Update: 1. NPHY and IOM blobs have to be added to added COREBOOT, FW_MAIN_A and FW_MAIN_B through board configuration files. CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE: IOM blob Path SOC_INTEL_CSE_NPHY_CBFS_FILE: NPHY blob path 2. Enable CONFIG_CSE_SUB_PARTITION_UPDATE to enable CSE sub-partition NPHY/IOM update. coreboot follows below procedure to update NPHY and IOM: NPHY Update: 1. coreboot will navigate through the CSE region, identify the CSE’s NPHY FW version and BIOS NPHY version. 2. Compare both versions, if there is a difference, CSE will trigger an NPHY FW update. Otherwise, skips the NPHY FW update. IOM Update: 1. coreboot will navigate through the CSE region, identify CSE's IOM FW version and BIOS IOM version. 2. Compares both versions, if there is a difference, coreboot will trigger an IOM FW update.Otherwise, skip IOM FW update. Before coreboot triggers update of NPHY/IOM, BIOS sends SET BOOT PARTITION INFO(RO) to CSE and issues GLOBAL RESET commands if CSE boots from RW. coreboot updates CSE's NPHY and IOM sub-partition only if CSE boots from CSE RO Boot partition. Once CSE boots from RO, BIOS sends HMRFPO command to CSE, then triggers update of NPHY and IOM FW in the CSE Region(RO and RW). coreboot triggers NPHY/IOM update procedure in all ChromeOS boot modes(Normal and Recovery). BUG=b:202143532 BRANCH=None TEST=Build and verify CSE sub-partitions IOM and NPHY are getting updated with CBFS IOM and NPHY blobs. Verified TBT, type-C display, NVMe, SD card, WWAN, Wifi working after the update. Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03soc/intel/common: Add check before sending HMRFPO_ENABLE commandSridhar Siricilla
This patch adds a check to determine if the CSE's current operation mode is ME_HFS1_COM_SECOVER_MEI_MSG or not before sending HMRFPO_ENABLE command to CSE. If CSE is already in the ME_HFS1_COM_SECOVER_MEI_MSG, coreboot skips sending HMRFPO_ENABLE command to CSE to unlock the CSE RW partition. TEST=Verify sending HMRFPO_ENABLE command on Brya system. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I387ac7c7296ab06b9bb440d5d40c3286bf879d3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03soc/intel/common: Rename compare_cse_version() function nameSridhar Siricilla
The patch renames the compare_cse_version() function to the cse_compare_sub_part_version(). It makes the function generic so that it can be used to compare version of any CSE sub-partition like IOM, NPHY etc. TEST=Verified build for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I88a44a3c0ba2ad8a589602a35ea644dab535b287 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59689 Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03soc/intel/alderlake: Add support for ADL-N PCHUsha P
Introduce the `SOC_INTEL_ALDERLAKE_PCH_N` Kconfig option and use it to specify the correct amount of PCIe I/O. Document number 645550 indicates that Alder Lake-N has 12 PCH root ports and no CPU root ports. Document number 645548 indicates ADL-N has 5 clock sources and 5 clock request signals. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03soc/intel/alderlake: Add the CnviDdrRfim configurationRonak Kanabar
FSP v2422_01 introduced new FSPM UPD CnviDdrRfim. Add CnviDdrRfim config to control the CnviDdrRfim UPD from devicetree. Setting CnviDdrRfim to 1 enable CNVi DDR RFIM BUG=b:201724512 BRANCH=None TEST=Build and boot brya with debug FSP and verify CnviDdrRfim UPD value. Change-Id: Ia06c9ed77d78821fd4724046bae2f31c9d771518 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03soc/intel/alderlake: Add TDP to give correct VR configurationCurtis Chen
The VR configuration should be based on the different Soc SKU type. And we also have different SKU in the same SA PCI ID. Therefore, add TDP to recognize the correct SKU and give the correct power setting. BUG=b:202486131 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: I4d31e7afc76d9a8c772781671f92ec08f9d8713f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 10:50:52 +0000