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Also, extra-lines added or removed and local includes moved down.
Change-Id: I5e739233f3742fd68d537f671642bb04886e3009
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32009
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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FSP options list (for each PEG port):
- PegXEnable,
- PegXMaxLinkWidth,
- PegXMaxLinkSpeed,
- PegXPowerDownUnusedLanes,
- PegXGen3EqPh2Enable,
- PegXGen3EqPh3Method.
Add PegMaxLinkWidth to chip.h. This option overrides the number of
active lines from the devicetree.cb for each enabled PEG port (for
example for boards that use x4 instead of x16 lines in PEG0). If the
PegMaxLinkWidth is not defined, the port uses the maximum possible
number of lines.
To enable or disable the corresponding PEG root port you need to add
to the devicetree.cb:
device pci 01.0 on end # enable PEG0 root port
device pci 01.1 off end # do not configure PEG1
If PEG port is not defined in the devicetree, it will be disabled in
FSP.
It has been tested on ASRock H110M-DVS motherboard (Skylake i5-6600
CPU).
Change-Id: I23708f7060edf08739adf61fe61a419329907563
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32045
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The InternalGfx option in devicetree.cb is not used to enable iGPU.
The patch removes this option from chip.h and mb/*/devicetree.cb
files for all boards with skl/kbl processor.
Change-Id: I41ecca3fdfb1d4b20ee634a13263ff481dcf440e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch includes the following changes:
1. Sets FSP options in romstage_fsp20.c to select primary GPU.
List of options:
- InternalGfx,
- PrimaryDisplay.
2. iGPU will be initialized if the corresponding PCI device is defined
in the device tree as:
device pci 02.0 on end
In this case, it is not necessary to set the InternalGfx option to
enable this device
3. Primary_iGFX is used as the default value for all skl/kbl boards
(since the PrimaryDisplay option isn`t defined in the devicetree.cb)
Change-Id: Ie3f9362676105e41c69139a094dbb9e8b865689f
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Serial IRQ was configured in quiet mode, but not enabled.
Enable serial IRQ and use 'enum seriirq_mode' as a devicetree
option.
Function sc_enable_serial_irqs() is added to enabled serial IRQs.
enable_serirq_quiet_mode() is renamed to
sc_set_serial_irqs_mode(). This function use the 'serirq_mode' to
set the mode. The call to this function is moved from finalize to init
having serial IRQs enable in early stage.
Serial IRQs must be enabled in continuous mode for at least one frame
before switching into quiet mode.
BUG=N/A
TEST=Portwell PQ7-M107
Change-Id: I7844cad69dc0563fa6109d779d0afb7c2edd7245
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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This patch enables CONFIG_VBOOT_OPROM_MATTERS in a few more cases where
I think(?) it should be. Haswell, Broadwell and Baytrail Chromebooks
have this enabled in their old depthcharge firmware branches -- we
presumably just forgot to move it over when vboot2 migrated the option
to coreboot. Braswell didn't, but it seems like this requirement was
added when it was migrated to FSP 1.1...? (Not very sure about that one,
but it does call load_vbt() right now which executes things based on
display_init_required().) Additionally, it seems to make sense to enable
it whenever the user explicitly selects VGA_ROM_RUN in menuconfig (like
one of the Intel defconfigs does).
Once we have all this, one could take a step back and ask whether this
option still makes sense at all anymore. It's enabled for almost all
devices (that work with vboot at all), it will presumably be enabled for
all future devices, and it seems that most devices that don't enable it
use libgfxinit, which as far as I can tell isn't gated on
display_init_required() but probably should be. Realistically, whatever
kind of display init a board needs to do (native or option ROM), it's
probably expensive enough that it's worth skipping on a normal mode
vboot boot, and we'd want to have this enabled by default on everything
except boards that actually don't have a display. So maybe we should
flip it around to CONFIG_VBOOT_OPROM_DOESNT_MATTER, but doing that would
probably lead to nobody ever selecting it at all.
Not sure what the best solution there is yet, but I think this patch
at least moves things in the more correct direction.
Change-Id: Id96a88296ddb9cfbb58ea67d93e1638d95570e2c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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FSP has a UPD to unlock all GPIO pads. This parameter is disabled by
default. Add a chip parameter so that GPIO pads can be unlocked on mainboard
level in devicetree and therefore this feature can be used if needed.
BUG=b:128686027
Change-Id: Iad9e8a209dc3f8ca0c994e8c1da329918409a1d4
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Ignore integrated GBE controller LTR setting to make it wake up from
s0ix with 10/100M cable attached.
BUG=b:122435844
TEST= Test on sarien platorm, after the changes sytem can wake by WOL,
and also checked SLP_S0 residency can increase with 10/100M cable
and battery connected.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Iec7dd197b8a456751f8e4dcb19e3e153f5888613
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This patch ports CB:30717 changes from CNL to ICL.
This structure is declared as a static CAR_GLOBAL in the common
PMC library code and in the SOC specific code. Remove the SOC
specific version and instead get the chipset_power_state pointer
from the PMC library.
This fixes events that were recorded in chipset_power_state at
boot but were reading as all zero when it was time to parse the
structure when logging events to flash.
Change-Id: I1152d0e882e1acf475072d1553b74f9161e2f485
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32095
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support to identify and log the XHCI wake events for apollolake into
event logs.
BUG=b:123429132
BRANCH=None
TEST=Ensure that the system boots to ChromeOS. Ensure that the wake up
events due to USB are logged into the event logs.
6 | 2019-03-21 09:22:18 | S0ix Enter
7 | 2019-03-21 09:22:22 | S0ix Exit
8 | 2019-03-21 09:22:22 | Wake Source | PME - XHCI (USB 2.0 port) | 9
9 | 2019-03-21 09:22:22 | Wake Source | GPE # | 13
10 | 2019-03-21 09:23:20 | ACPI Enter | S3
11 | 2019-03-21 09:23:30 | Wake Source | PME - XHCI (USB 2.0 port) | 9
12 | 2019-03-21 09:23:30 | ACPI Wake | S3
13 | 2019-03-21 09:23:30 | Wake Source | GPE # | 13
Change-Id: I55b850646dda8acaa086a9012c2d8b611016f932
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32000
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The policy to identify and log the XHCI wake events is similar between
skylake and apollolake. Hence move the similar parts to a common
location.
BUG=b:123429132
BRANCH=None
TEST=Ensure that the system boots to ChromeOS. Ensure that the wake up
events due to USB are logged into the event logs.
6 | 2019-03-21 09:22:18 | S0ix Enter
7 | 2019-03-21 09:22:22 | S0ix Exit
8 | 2019-03-21 09:22:22 | Wake Source | PME - XHCI (USB 2.0 port) | 9
9 | 2019-03-21 09:22:22 | Wake Source | GPE # | 13
10 | 2019-03-21 09:23:20 | ACPI Enter | S3
11 | 2019-03-21 09:23:30 | Wake Source | PME - XHCI (USB 2.0 port) | 9
12 | 2019-03-21 09:23:30 | ACPI Wake | S3
13 | 2019-03-21 09:23:30 | Wake Source | GPE # | 13
Change-Id: Ia6643342e3292984e422ff3c3fcd4bc0d99f947e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The following is the FSP logic: as long as the Cpu Ratio input in
coreboot is different with CpuStrapSet, system will force to follow
input from coreboot. But CpuStrapsetting is floating, it will be 0
from the first cold boot before memory training and set to 0x1c (or
max CPU ratio for the installed CPU) after first memory training.
The previous fix was attempting to ensure settings were cleared
when FSP was called in recovery mode, but only when coming from S5
which caused issues if recovery mode is requested by the OS and
is only followed by a warm reset.
BUG=b:129412691
TEST=Boot up sarien platform and force recovery, check there's no reset
in the path of recovery.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I959188be46343bc6f2cb3cc149097b4d449802aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32089
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For systems that integrate GbE controllers, following parameters should be configured:
SlpS0WithGbeSupport: enable PchPmSlpS0VmRuntimeControl: disable,
PchPmSlpS0Vm070VSupport: disable, PchPmSlpS0Vm075VSupport: disable.
TEST=boot on any GbE supported WHL platform
Change-Id: I02aaf0b77b8fc1555a3a424c02acfada21707d0e
Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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After raminit completes, do a read-modify-write test
just below CBMEM top address. If test fails, die().
Change-Id: I33d4153a5ce0908b8889517394afb46f1ca28f92
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Change-Id: I3d14a40b4ed0dcc216dcac883e33749b7808f00d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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This option has been relocated to depthcharge:
https://crrev.com/c/1524806
BUG=b:124141368, b:124192753
TEST=Build and deploy to eve
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
CQ-DEPEND=CL:1524806
BRANCH=none
Change-Id: Ib4a83af2ba143577a064fc0d72c9bc318db56adc
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31909
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In my case, on UPsquared board with Celeron N3350 CPU,
I don't have UART2 but UART0.
Change-Id: Id9a742144eba0f1d1544aafecf44d4730d055b4a
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The prev_sleep_state value was showing 5 even after warm reboot, once the
SUS_PWR_FLR bit is being set. This bit was not being cleared.
Hence clearing the PMCON status bits.
BUG=b:128482282
BRANCH=None
TEST=In cbmem logs, check for value of “prev_sleep_state” using command
cbmem –c | grep “prev_sleep_state”
For cold reboot, "prev_sleep_state 5"
For warm reboot, "prev_sleep_state 0"
Change-Id: If9863d52ed3c61b6a160df53f023b0787eaaed68
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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Change-Id: Id4f5e1fad935645830782ba922f55f614c72cf06
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31353
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch ensures to make use of common MP Init Kconfig to
choose desire method to peform MP initialization for platform.
Change-Id: I4ee51276026748e8daf154f89e57095e8fe50280
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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mainboard users can select correct MP Init Kconfig in order to
perform MP initialization.
1. Native coreboot MP Init.
2. FSP to do MP Init.
3. FSP to make use of coreboot MP service PPI to perform MP Initialization
Change-Id: Ifbea463fdaf97d68c21a759c37f49492d58a056b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I52c852fb449de5a6512aa2556592e6dfe7b0c573
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This change enables user to shutdown the system by shortly pressing
power button (<10sec) before OS is loaded. Main use case is shutdown
from recovery/broken screen.
BUG=N/A
TEST=Boot up into recovery screen on Sarien platform, press power button
once, and system should shutdown immediatelly.
Change-Id: I7655daf65ff058df7d9bad4567f74b4f4007acb4
Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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We missed some PCIe root ports with previous cleanup.
Change-Id: I8bf8f8b2ca1836316f84fb7f01820a00d7194d51
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Assign the FSP UPDs for HPD and DDC of DDI ports. FSP assumes that all
DDI ports are enabled and hence configures the HPD and CLK for DDI ports.
This patch initializes only the required UPDs to enable display ports.
BUG=b:123907904
TEST=DP devices working correctly.
Change-Id: Ic0c172cd3d087fc8f49b01ab23feffdababf7166
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch removes all local definitions of sub_system functions and make
use of common generic pci_dev_set_subsystem() from PCI bridge and Cardbus
devices as well.
Change-Id: I5fbed39ed448baf11f0e0786ce0ee94741d57237
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch removes local definitions of sub_system function and make use
of common function pci_dev_set_subsystem().
Change-Id: I91982597fdf586ab514bec3d8e4d09f2565fe56d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Guckian
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Drop 'include <string.h>' when it is not used and
add it when it is missing.
Also extra lines removed, or added just before local includes.
Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Commit 41483c9 (soc/intel/cannonlake: Add required FSP UPD changes for
CML) changed the enum values for PCH_SERIAL_IO_MODE so that 0 is
invalid and valid values start from 1. However, get_param_value was
not updated to correctly subtract 1 before returning any value. This
change adds a macro PCH_SERIAL_IO_INDEX to apply the subtract 1
operation on any value that get_param_value needs to return.
BUG=b:128946016
TEST=Verified that hatch boots successfully.
Change-Id: I4e32fcd1efe4a535251f0ec58662a2dc5f70e8b0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove FSP 2.0 support from ICL SoC and add FSP 2.1 support.
Change-Id: Ife0c133ddbf2e0fa14f94ffec15d11830cfaf7b3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30158
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Default reserved value of used for SCI IRQ.
Configure SCIS field to use IRQ 9.
BUG=N/A
TEST=Facebook FBG-1701 booting Embedded Linux
Change-Id: I09aca433528b6f64ad3ff3753ae8392c0d89cdc0
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Change-Id: I6577d9a31da44be5b57bb10497d9bd02fc9bbcd3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Iee09b601045d7785a0977a4f7ed7385b1d311044
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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The mmio resouces IOAPIC and ROM area not reserved.
Reserve IOAPIC and ROM resources.
BUG=N/A
TEST=Intel CherryHill CRB booting Embedded Linux
Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I311269967949533264e44fd3bb29ad3a06056653
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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coreboot have an option to use legacy UART or LPSS UART. FSP will use the
UART initialized by coreboot and we can choose an option to skip Uart
initialization by FSP.
For this, we need to pass correct debug interface flag to FSP through
which FSP will know which UART port to use. If we don't pass correct
interface information, FSP may try to dump logs on that port and it may
slow down the system.
BUG=none
BRANCH=none
TEST=Compile and boot with coreboot. Check FSP and coreboot logs are
coming on serial port.
Change-Id: I1ebb20c93e2c15ec085538509099de72bc9dd62c
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Update the Kconfig option for disabling ESPI SMI source
to disable it entirely, not just when ACPI mode is disabled.
For the situations where this is needed (just the sarien
board) it is better to completely stop the EC from sending
any SMI events as no actions are taken.
Change-Id: Id94481bb2f0cfc948f350be45d360bfe40ddf018
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch adds required FSP UPD changes for CometLake SoC.
Also this patch tries to create common parse logic for CometLake as
well as cannonlake SOC.
We parse device tree parameters for PCI devices and fill values in FSP
UPDs. We fill UPDs based on pci device config as well as SerialIoDev
config of devicetree.
For PCI devices, if PCI device is disabled from devicetree, we'll assign
disable value to FSP UPD.
In case devicetree doesn't fill this parameter or value is invalid in
SerialIoDev config, default mode will be set to PCI.
In case of valid value, we'll fill the same value into FSP UPD.
BUG=none
BRANCH=none
TEST=check if CML board boots and proper UPD values are filled.
Change-Id: Ib92b660409ab01d70358042b2ed29b8bf9cab26d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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Change-Id: Ie7afe77053a21bcf6a1bf314570f897d1791a620
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I9b4d72116a66d5a256659fa82682497ef3481e77
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Move ChipsetFspReturnPoint() to drivers/intel/fsp1_0.
Allows to have a common entry after FSP-M.
Change-Id: I064ae67041c521ee92877cff30c814fce7b08e1f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
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CNL PCH has PWR_FLR, SUS_PWR_FLR and HOST_RST_STS bits in GEN_PMCON_A
and so this change updates the check for these bits to use GEN_PMCON_A
instead of GEN_PMCON_B.
BUG=b:128482282
TEST=Verified that prev_sleep_state is reported correctly when booting
from S5.
Change-Id: I75780a004ded8f282ffb3feb0cdc76233ebfd4f2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31908
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order to support mainboards that do not store DRAM part number in
the traditional way i.e. within the CBFS SPD for soldered memory, this
change provides a runtime callback to allow mainboards to provide DRAM
part number from a custom location e.g. external EEPROM on hatch.
For other boards it should be a NOP since the weak implementation of
mainboard_get_dram_part_num does nothing.
BUG=b:127609572
Change-Id: I9b2d4c33fc378b9a24b111971ec2bfdb5f8d57d0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31850
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use <arch/acpi.h> when appropriate.
Change-Id: I05a28d2c15565c21407101e611ee1984c5411ff0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Some Apollo Lake mainboards use SeaBIOS as payload. SeaBIOS requires the
initialization of the programmable interrupt controller (PIC) for
faultless operation. The PIC mode is need for USB support (e.g.
keyboard, memory stick) and for some Option ROMs (e.g. PXE ROM).
Therefore add setup_lapic() to configure the APIC.
Change-Id: I00b339ce1850729023db74da7f8845927a95dcc6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31802
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This patch adds support for logging wake source information in gsmi
callbacks. With this change, all the elog logging infrastructure can
be used for S0ix as well as S3 on cannonlake.
BUG=b:124131938
BRANCH=none
TEST=Verified that the wake events are logged during the S0ix resume:
6 | 2019-03-04 17:03:13 | S0ix Enter
7 | 2019-03-04 17:03:17 | S0ix Exit
8 | 2019-03-04 17:03:17 | Wake Source | RTC Alarm | 0
9 | 2019-03-04 17:03:55 | S0ix Enter
10 | 2019-03-04 17:03:56 | S0ix Exit
11 | 2019-03-04 17:03:56 | Wake Source | GPE # | 21
12 | 2019-03-04 17:04:36 | S0ix Enter
13 | 2019-03-04 17:04:45 | S0ix Exit
14 | 2019-03-04 17:04:45 | Wake Source | GPE # | 112
15 | 2019-03-04 17:05:01 | S0ix Enter
16 | 2019-03-04 17:05:09 | S0ix Exit
17 | 2019-03-04 17:05:09 | Wake Source | Power Button | 0
Change-Id: Id627843e22c2524dfa94395b780cf2134f386137
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change moves soc_fill_power_state and soc_prev_sleep_state to
pmutil.c. It allows the functions to be used across romstage and smm.
BUG=b:124131938
BRANCH=none
TEST=none
Change-Id: If24c3feeb77f4fb692ef0bf38d537b2b54de3c36
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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CPU PM TIMER EMULATION logic will help UEFI payload to execute rather
wait for time tick in absence of TCO and ACPI PM timer after FSP-S.
BUG=N/A
TEST=Able to build and boot with tianocore payload.
Change-Id: I7fd11e728b7a14f41f08bc39bcd92a42a8aa6cff
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I7e181111cd1b837382929071a350b94c3afc1aaa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This patch adds support H110 chipset (Sunrise Point) for Skylake and
Kaby Lake processor families by adding the corresponding IDs. It has
been tested on ASRock H110M-DVS motherboard (Skylake i5-6600 CPU).
Change-Id: I85ba65ac860687b0f9fd781938e5cac21a1b668d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31602
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds support
1) Intel(R) Xeon(R) E3 - 1200/1500 v5/6th Gen Intel(R) Core(TM) Host
Bridge/DRAM Registers - 191F;
2) HD Graphics 530 Skylake GT2 - Intel integrated graphics processor
https://en.wikichip.org/wiki/intel/hd_graphics/530.
This is required to run coreboot on the Intel Core i5-6600 (Skylake)
desktop processor. It has been tested on ASRock H110M-DVS motherboard.
Change-Id: If47e9ac32813a9f73d3a23f44536f60d1003971d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31601
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add SPI_OPTYPE_XXX values for the SPI controller.
BUG=N/A
TEST=flashrom on Facebook FBG-1701
Change-Id: Id183d68b3a80b2e7ab1a0685580d79ca327db03a
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Intel Braswell P-UNIT is missing in pci_devs.h
Add PUNIT device, function and device ID
BUG=N/A
TEST=Facebook FBG-1701 booting Embedded Linux
Change-Id: I80c87c8964b3ba830571e0c03c424b67729a0c1a
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31711
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I1f44ffeb54955ed660162a791c6281f292b1116a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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The other DEFAULT_ entries are just immediate
constants.
Change-Id: Iebf4266810b8210cebabc814bba2776638d9b74d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Call the simple PCI config accessors directly.
Change-Id: I2c6712d836924b01c33a8435292be1ac2e530472
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This IS_ENABLED(XXX) line should've clearly been IS_ENABLED(CONFIG_XXX).
This patch can fix that. However, I don't have (and don't plan to
acquire) an affected system to test, so approve at your own risk (or
let me know if I should just remove that check instead).
Change-Id: I79a0fca65853798ee45c3779b437864ba3cf2b1e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Intel Braswell SoC contains SMBus controller but no support
is available for this controller.
This controller is compatible with the Intel SMBus support in the
southbridge common directory.
To be able using smbus support from the Intel common directory
the smbus.c is moved outside SOUTHBRIDGE_INTEL_COMMON
dependency block.
Use SOUTHBRIDGE_INTEL_COMMON_SMBUS to include support.
BUG=N/A
TEST= Facebook FBG-1710 LCD panel
Change-Id: Ie3d4f657558a1aed21b083ef5cad08ea96e629c3
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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MMIO operations are arch-agnostic so the include
path should not be arch/.
Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I91158452680586ac676ea11c8589062880a31f91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31692
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fixes indirect includes that would break with followup work.
Change-Id: I37ca01b904a0b422a4d09475377e755e167a6ab3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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These resolved to <device/oprom/include/io.h> which
included <arch/io.h> that we really wanted.
Change-Id: I9aa0bdf34cd1d53e20b4494c7986f0878f4fd840
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31693
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move common definitions for PCH H and LP to a common header.
Change-Id: If47692ecb05134db1ee6c0fb10125d6a1b67f127
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31621
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the ISH ACPI device so we can hang fields off of a _DSD table.
Since this is also a PCI device that has run time probing, we can always
emit the ACPI device and let the device tree turn the device on or off.
BRANCH=none
BUG=b:122722008
TEST=verify that _DSD table gets publish under ISH device in kernel ACPI
tables. Also verified that device is still turned off if device tree for
ISH is off.
Change-Id: Ic0231f1ac637fea0e251eb3ac84f0fd8d64c12b2
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31681
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The following remarks show up during cannonlake based platform coreboot
build:
dsdt.asl 55: Offset (0x00),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 136: Offset (0xa8),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
Address those two remarks in coreboot.
BUG=N/A
TEST=Build coreboot and check build log to see no more remark.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Iad660347b32d90ac1176654820375e30a21b5ffe
Reviewed-on: https://review.coreboot.org/c/31666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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Local APIC was not configured.
Add setup_lapic() to configure the APIC.
BUG=N/A
TEST= Ubuntu 4.15.0 reports correct local APIC information
on Intel CherryHill CRB
Change-Id: Ic1da5b1bf235f34b957142e86c70a9dbfa3ded1d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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HDA support did not configure the codecs correclty.
Use Intel common block support to configure the codecs.
To use common Intel HDA support file hda.c file has been
removed and Braswell HDA device ID is added to list of
supported PCI devices in intel/common/block/hda/hda.c.
CONFIG_SOC_INTEL_COMMON_BLOCK and
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA are enabled
to include hda.c in build.
When codec table is available at board level
SOC_INTEL_COMMON_BLOCK_HDA_VERB must be enabled
and a codec table must be supplied.
BUG=N/A
TEST=Facebook FBG-1701 ALC298 configuration
Change-Id: I5c23ec311e5b5a6dfd6f031aa19617407fe8ed63
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Since ACPI v2.c, this field is access_size.
Currently, coreboot is using ACPI v3,so we can drop '.resv' field.
Change-Id: I7b3b930861669bb05cdc8e81f6502476a0568fe0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.
Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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We had two ways to configure the serial IRQ mode. One time in the
devicetree for FSP and one time through Kconfig for coreboot. We'll
use `enum serirq_mode` from soc/intel/common/ as a devicetree option
instead. As the default is `quiet mode` here and that is the most
common mode, this saves us a lot of lines.
In four cases kblrvp8, 11 and librem 13v2, 15v3, we had conflicting
settings in devicetree and Kconfig. We'll maintain the `continuous`
selection, although it might be that coreboot overrode this earlier
on the kblrvps.
Note: A lot of Google boards have serial IRQ enabled, while the pin
seems to be unconnected?
Change-Id: I79f0cd302e335d8dcf8bf6bc32f3d40ca6713e5c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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INT_MODEL defined in ACPI 1.0 and renamed to reserved since V 2.0.
The value for this field is zero but 1 is allowed to maintain
compatibility with ACPI 1.0.
So set this value to zero as we are using greater version than ACPI 1.0.
Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29986
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Calculation of memory reserved by FSP is incorrect.
Use CBMEM_ID_FSP_RESERVED_MEMORY to determine the memory area
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: If68bda39ba2b1f3be4ed4bc872710be7bbd4948b
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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This patch adds SOC_INTEL_COMETLAKE Kconfig option.
Change-Id: I2b0c269ade84d72cffaf59a0b53e0d6e3a84b835
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/31282
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ISA dma controller is not configured.
Add call isa_dma_init().
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: Ib7af3f4ef6d6a29628bb2c27d32071be63ff6af2
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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The level/edge mode of PIRQ is not configured and i8259 PIC not initialized.
Add calls to:
- i8259_configure_irq_trigger()
- setup_i8259()
- write_pci_config_irqs()
to correct the configuration of interrupts.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I128cb35dd0e348a9cd9fb162651e0aa2b7e4a3ef
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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IRQ10 and 11 are not available as _PRS in all LNKx ResourceTemplates.
These interrupt numbers are added to all LNKx.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: Ie7a263d7d50f7f85e6195777c1429dcc27a15604
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29287
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change ac8c60e (soc/intel/cannonlake: Disable ACPI mode as part of
pmc_soc_init) moved disabling of ACPI mode to pmc_soc_init to keep it
more aligned with the behavior on other Intel SoCs. However, as the
PMC device is hidden, it never gets enumerated and so init function
does not get called for it. This change moves the call to disable ACPI
mode to exit of BS_DEV_INIT instead.
BUG=b:126016602
TEST=Verified that:
1. pmc_set_acpi_mode is actually getting called.
2. EC panic event gets logged to eventlog correctly.
Change-Id: Ie7025e322fa0abc21367a520184a4c7741eba1e6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31633
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: If7190ac105b2a65a9576709955c3cc840b95dcdf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Fix cases of using ENV_SMM where __SIMPLE_DEVICE__
should be used instead.
Change-Id: I385c82767a87ff7a47466a200488fae9fc8b863d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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TEST=Verify PM_STS1 value is is not 0xFF.
Change-Id: I932585f6e7525830bd57ecfc372bf3120e7cca66
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/31434
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds CML-U 2+2 SA DID into systemagent.c and report
platform.
Change-Id: I2e882a560dd0a1e96d6e1405735c6f7389c0db5a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31638
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes duplicate pm timer emulation macros from soc
directory and makes use from common code msr.h
Change-Id: I6ec347e7464f785862e855817ec8308e3d207bb1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31610
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For fast CBMEM console use minimum BIOS_DEBUG level.
For other consoles, Kconfig and/or nvram settings
apply.
Change-Id: Iff56a0a3182f258200cac80e013957d598cc2130
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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SD controller in CNL-PCH provides a ability to configure the behavior of
SD_VDD1_PWR_EN# as an active high or low signal. FSP provides an UPD
"SdCardPowerEnableActiveHigh" to control the same.
However, for platforms using SD_VDD1_PWR_EN# as active high, the SDXC
card connector is always powered and may impact system power. This is because
SD_VDD1_PWR_EN# does not de-assert during SDXC D3 or when SD card is not
inserted.
Workaround is to change the pad ownership of SD_VDD1_PWR_EN to GPIO and
force the TX buffer to low in _PS3. And restore the pad mode to native
function in _PS0.
Hence add a Kconfig option to update the UPD, which the board can select
based on how the SD_VDD1_PWR_EN is implemented on it. And, the workaround
gets applied based on this config.
BUG=b:123350329
Change-Id: Iee262d7ecdf8c31362aec3d95dd9b3e8359e0c25
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31445
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a function in gpio ASL library to enable/disable pad Rx/Tx Buffers.
BUG=b:123350329
Change-Id: I6c40d79debb61b0c4e96e485b410d446b77d9cf6
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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PMC initialization on Cannon Lake happens earlier in the boot sequence
than other SoCs because FSP-Silicon init hides PMC from PCI bus. As
ACPI disabling was done as part of PMC init, it was being called
earlier than what other SoCs do. This resulted in a different order of
events for some drivers e.g. ChromeOS EC. In case of ChromeOS EC, it
ended up clearing EC events (which happens as part of ACPI disabling
in SMM) before logging any events of interest that happen during
mainboard initialization.
This change moves the call to disable ACPI to pmc_soc_init just like
other SoCs to keep the order of events more aligned.
BUG=b:126016602
TEST=Verified that EC panic event gets logged to eventlog correctly.
Change-Id: Ib73883424a8dfd315893ca712ca86c7c08cee551
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Denote appropriate reserved groups as virtual GPIOs in Cannonlake LP/H SoC.
Change-Id: I4da161b91f83749b0ae29b387b5c99c1c3f706d8
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add cometlake specific PCH IDs
Change-Id: I18dda48cee29213aa66c0ccddf3da31f0f489d2f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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* Introduce a measured boot mode into vboot.
* Add hook for stage measurements in prog_loader and cbfs.
* Implement and hook-up CRTM in vboot and check for suspend.
Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add cometlake specific SA IDs
Change-Id: I1fbbab8a7797b36a9eacbd1c6a0644466f2fe6b1
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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Add cometlake specific CPU IDs
Change-Id: I75d5b82524c9df1402abf6659d62dbc716c28c30
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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CB:31547 fixes few whitespace error. Here is few more whitespace clean up.
Change-Id: I69c12a5da4feb48b2bc23874332ab341a559f6e6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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devicetree
Tested on system76 galp3-c
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I3aa8990a335e413628c016007ebabf7142aef80d
Reviewed-on: https://review.coreboot.org/c/31535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add a function in gpio ASL library to set pad mode.
BUG=b:123350329
Change-Id: I6c683f27ddffc3132001706d1694c71bb5664577
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I33a50e9fc90162c7cb2aa7fbc3887efe9c6ebcde
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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For CFL and WHL, Microcode is being loaded from FIT. Both
supports the PRMRR/SGX feature. If This is supported the FIT
microcode load will set the msr (0x08b) with the Patch id one
less than the id in the microcode binary. This results in
Microcode getting reloaded again in bootblock and ramstage.
Avoid the microcode reload by checking for PRMRR support.
CFL and WHL CPU die are based on KBL CPU so we need to have
this check, where CNL CPU die is not based on KBL CPU so
skip this check for CNL.
BUG=b:124126405
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Change-Id: I3311a7413d27044f9c819179e5b0cb9a67b46955
Reviewed-on: https://review.coreboot.org/c/31492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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Change-Id: I91b54b43c8bb5cb17ff86a6d9afa95f265ee49df
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Variants of Hatch need to accommodate single channel DDR. Also,
removing const modifier as we'll need to set these fields
incrementally now. For the single channel configuration, we set
MemorySpdPtr10 to 0. For the dual channel configuration, we set
MemorySpdPtr10 to MemorySpdPtr00.
BUG=b:123062346, b:122959294
BRANCH=None
TEST=Boot into current boards and ensure that we have 2 channels as expected
Change-Id: Ice22b103664187834e255d1359bfd9b51993b5b6
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31262
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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