| Age | Commit message (Collapse) | Author |
|---|
|
This driver is for the root port device and needs to reference the
parent device for its ACPI scope. Similarly for the debug output it
needs to use the parent device, and fall back to the chip name if
config->desc is not provided in the devicetree.
The UID property is removed. This value is not the same as the port
number; according to some docs it should be unique but it is not fully
clear what it should be tied to. Regardless, it is not used by the
Thunderbolt driver in the kernel.
I also renamed some functions/structures to be clear that this is just
an ACPI driver for the PCIe root port and not a driver for the root port
itself. As part of this I removed the PCI based resource operations and
the scan bus function since this device does not have children itself.
Finally I added a detailed comment with an example describing what the
driver is for and what properties it generates.
TEST=boot on volteer and ensure the USB4 root port device and properties
are added to the SSDT as described by the comment in chip.h.
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Id6069a0fb7a0fc6836ddff1dbeca5915e444ee18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46544
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The USB4 host interface (DMA) devices need to use SA_DEVFN_*
instead of SA_DEV_* when determining the ACPI name.
The matching names are removed from the SOC-level ACPI name
handler since they are provided by this driver now.
TEST=boot on volteer and ensure TDM0 device is in the SSDT.
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: If778bda82b80593452a590962dbffef6eff6484a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Deduplicate code by using the new common cpu code implementation of
AES-NI locking.
Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Get rid of legacy pad macros by replacing them with their newer
equivalents.
TEST: TIMELESS-built board images match
Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This converts the constant for the XTAL frequency to a Kconfig option.
Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Add a Kconfig for SoCs to indicate PM ACPI timer emulation support and
select it by the appropriate SoCs.
This Kconfig gets used in the follow-up changes.
Change-Id: I6ded79221a01655f298ff92b8bd2afabd1d2a3ff
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Lock AES-NI (MSR_FEATURE_CONFIG) to prevent unintended changes of
AES-NI enablement as precaution, as suggested in Intel document
325384-070US.
Locking is enabled by default (as already done in SKL and Arrandale) and
may be disabled by the newly introduced Kconfig in the parent change.
Tested by checking the MSR.
Change-Id: I79495bfbd3ebf3b712ce9ecf2040cecfd954178d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
The XTAL shutdown (dis)qualification bit already unconditionally gets
set to 1 by FSP for these platforms, making this code redundant.
Change-Id: I7fa4afb0de2af1814e5b91c152d82d7ead310338
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46016
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
disabled"
This reverts commit e5269a8fd975fa0cba0655cd41f7f8cc99a1feb8.
Reason for revert: BIOS spec says, it's recommended to always enable
emulation (regardless of the OS version).
Change-Id: If0d7fa6f9766c7c4e2fa9e846c179adc6a4e1681
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The subsystem ID registers are read/write-once. Writes by coreboot will
not take effect if FSP sets them.
Note that FSP sets one device ID for the SA devices and another for PCH
devices. coreboot will copy individual vendor and device IDs if
subsystem is not provided.
Change-Id: I9157fb69f2a49dfc08f049da4b39fbf86614ace3
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Coverity detects source memory is overrun. Fix this issue by using
the CONFIG_MAX_ROOT_PORTS value to avoid memory corruption.
Found-by: Coverity CID 1429762 1429774
TEST=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Icc253eb9348d959a9e9e69a3f13933b7f97d6ecc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Test: built google/volteer with `abuild --timeless` - SHA1 hashes match
Change-Id: Ice6cef402dfcc33f1fc7fdced66d38c380d338e5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Use the 96 character limit.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I43d77db1f81d72aa13f3a702abff490a68a52bd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
platform_fsp_silicon_init_params_cb is called by the fsp driver and
calls mainboard_silicon_init_params which sets the mainboard
PCH GPIOs.
Change-Id: Icf401e76741a6a7484295e999ddd566fe9510898
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46309
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Bryant Ou <bryant.ou.q@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Drop the Kconfig for hyperthreading to be always able to check at
runtime if hyperthreading is supported. Having a Kconfig for this
doesn't have any benefit.
Change-Id: Ib7b7a437d758f7fe4a09738db1eab8189290b288
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Due to platform-specific constraints, it is not possible to enable DPR
by programming the MCH's DPR register in ramstage. Instead, assume it
has been programmed earlier and check that its value is valid. If it is,
then simply configure DPR in TXT public base with the same parameters.
Note that some bits only exist on MCH DPR, and thus need to be cleared.
Implement this function on most client platforms. For Skylake and newer,
place it in common System Agent code. Also implement it for Haswell, for
which the rest of Intel TXT support will be added in subsequent commits.
Do not error out if DPR is larger than expected. On some platforms, such
as Haswell, MRC decides the size of DPR, and cannot be changed easily.
Reimplementing MRC is easier than working around its limitations anyway.
Change-Id: I391383fb03bd6636063964ff249c75028e0644cf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46490
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
msr_set_bit can only set single bits in MSRs and causes mixing of bit
positions and bitmasks in the MSR header files. Thus, replace the helper
by versions which can unset and set whole MSR bitmasks, just like the
"and-or"-helper, but in the way commit 64a6b6c was done (inversion done
in the helper). This helps keeping the MSR macros unified in bitmask
style.
In sum, the three helpers msr_set, msr_unset and msr_unset_and_set get
added.
The few uses of msr_set_bit have been replaced by the new version, while
the used macros have been converted accordingly.
Change-Id: Idfe9b66e7cfe78ec295a44a2a193f530349f7689
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46354
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This configuration option shares a name with the FSP UPD, but
is enumerated differently. Change its name to minimise confusion
about the options.
Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Prepare for common ACPI. Add get_system_memory_map() helper
function to soc_util.c and use it in the SRAT ACPI code
to match the cpx code.
Change-Id: I54675b52aaf2999d884b3c20ccb143fbbf8b138a
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45847
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Exposes PcieRpL1Substates to devicetree to allow boards to override this configuration.
Tested on an Acer Aspire VN7-572G (Skylake-U).
Change-Id: I36150858485715016158595c832c142b0582ddb8
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This comment does not follow any of the styles outlined in the coding
style page of the documentation. Adjust it to match the preferred style.
Change-Id: Idf6d0ea69a08e378266b4256c476580889adfca8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46428
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
TEST=Build and boot waddledoo board
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I067b13acfcea940e2e4ae6fc99b5d77458de35a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43705
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Idf40e2687b064c5ec7834e3c7d7ea9c8cb83c882
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45721
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
These aren't used anywhere, so get rid of them.
Change-Id: I267c0fd2e9d9d20ee852a73a9a916d85d6c65088
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45716
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
These are present in Lynx Point.
Change-Id: I381f3cbf5fd18c952622f757135c0bde9ed6ed0d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45715
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Tested with BUILD_TIMELESS=1, Purism Librem 13v1 does not change.
Change-Id: Icf41d9db20e492ec77a83f8413ac99a654d6c8ed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45697
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This makes comparisons against Haswell a bit simpler.
Change-Id: If1c937628f702c6765a5f36b6eaf4a3c3516359a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
In order for USB Type-C devices to be detected prior to loading Kernel
PMC IPC driver API is needed to send IPC commands to the PMC to update
connection/disconnection states.
BUG=b:151731851
BRANCH=none
TEST=built coreboot image and booted to Chrome OS
Change-Id: Ide3528975be23585ce305f6cc909767b96af200f
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
List of changes:
1. Select CONFIG_INTEL_TME from SoC Kconfig
2. Set TmeEnable FSP-M UPD based on Kconfig.
TEST=Able to build and boot ADLRVP and verified from Chrome OS
that TME is enable.
Change-Id: I6992957bd2999a2efbae7b6d9c825c43bd118f72
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46296
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change enables the USB4/Thunderbolt common layer for Intel SOC,
and enables the Intel USB4 PCIe driver. This moves the _DSD variables
from the DSDT into the SSDT and allows them to be configured for each
board if necessary.
Change-Id: I2564512d951046e015c148db42fdaf2d4b8b81dd
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44917
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This driver will generate the ACPI _DSD for the USB4 PCIe root port
properties instead of using static ASL.
It assigns the USB4 port number and marks the port as external and
hotplug capable.
Change-Id: I7086b06346ce63fab6bef4077fb76ae1d30dc1eb
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44915
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This common intel driver will add the requried ACPI _DSD entries for
enabled USB4/Thunderbolt ports' DMA devices the SSDT instead of using
hardcoded values in the DSDT.
Change-Id: Ic4a58202d4569cf092ea21a4a83a3af6c42ce9d0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
In order to enable SSDT generation for the DMA component of Intel USB4
ports, a PCI driver is required. This patch more or less adds a
`scan_bus` callback that will handle non-PCI devices downstream.
Change-Id: Ib9da051307b883eb99e500114378c9fd842ffc92
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The current Kconfig help text is confusing because it talks about
enabling the Kconfig for disabling a UPD for disabling power gating.
Rewrite and clarify the help text.
Change-Id: I9637c549db1ce29f259708f316852fc2ae9e7c38
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This change switches all mainboard devices to use drivers/wifi/generic
instead of drivers/intel/wifi chip driver for Intel WiFi
devices. There is no need for two separate chip drivers in coreboot to
handle Intel and non-Intel WiFi devices since the differences can be
handled at runtime using the PCI vendor ID. This also allows mainboard
to easily multi-source WiFi chips and still use the same firmware
image without having to distinguish between the chip drivers.
BUG=b:169802515
BRANCH=zork
Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
To avoid confusion with `flashconsole` (CONSOLE_SPI_FLASH), prefix this
option with `EM100Pro`. Looks like it is not build-tested, however.
Change-Id: I4868fa52250fbbf43e328dfd12e0e48fc58c4234
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Expose configuration of Intel PAVP (Protected Audio-Video Path, a
digital rights protection/management (DRM) technology for
multimedia content) to Kconfig.
Per the FSP default, this was always being enabled previously.
Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
By ironing out cosmetic differences between Cannon Lake and Ice Lake,
comparing actual code differences using a diff tool becomes simpler.
Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical.
Change-Id: I4d9f882f9f8af1245e937b0d47bc7e993547365f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
|
Add a weak override function to allow mainboard to override chip
configuration like GPIO PM.
BUG=None
TEST=Build and boot waddledee to OS. Ensure that the suspend/resume
sequence works fine.
Change-Id: I40fa655b0324dc444182b988f0089587e3877a47
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Jasper Lake support 3 Memory train frequencies low. mid and high.
Update the SaGv configuration accordingly.
Change-Id: I366de1ea7cf41c56b2954b8032c69bfba81058e2
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
|
|
Allow to link the smihandler when not selecting SOC_INTEL_COMMON_BLOCK_UART.
Change-Id: Iabca81c958d00c48e0616579cbba61d254c5eb68
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
|
|
Currently devices behind I2C controllers are scanned using scan_smbus.
This is done under the assumption that there are no bridge devices behind
I2C controllers. In order to support I2C multiplexers which act as
bridge devices and have devices behind them, scan the I2C controllers
using scan_static_bus.
BUG=b:169444894
TEST=Build and boot waddledee to OS. Ensure that all the bridge devices
behind I2C controller are scanned and enabled.
Change-Id: I9d8159a507683d8c56dd5e59d20c30ed7e4b2cab
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Add SPD support for DDR4 memory part H5ANAG6NCJR-XNC.
BUG=b:161772961
TEST=none
Change-Id: I71e4de9a28f78bbf8c7de1fcafa3596276a5f2f9
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The kernel driver enumerates communities 0, 1, 4, and 5, and assigns
these addresses based on the BARs enumerated by coreboot. Coreboot
was defining communities 0, 1, 2, 4, and 5. This meant the kernel
was not controlling GPIOs in communities 4 and 5, since the resources
were wrong.
Remove community 2 for now. We can add it back if the kernel ends up
needing it.
BUG=b:169444894
TEST=Test controlling GPP_E5, verify actually toggles register.
Signed-off-by: Evan Green <evgreen@chromium.org>
Change-Id: I823e1aa942cfccadde01b9371d481457ab088c31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46115
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add aliases for devices and set most of them to off with the exception
of some essential devices.
Set a default register value as an example.
Change-Id: If50269808645ddc019e0d94fa8296df58ab7c367
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44038
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Don't use the silicon-specific struct type to get common config
options. Instead, use the generic config_t typedef. This allows
the function to be moved to common code in upcoming patches.
Change-Id: If80b678037b4d79387e0a0f722c540df4aae2416
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46057
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
According to document number 338846 and 336062 this should be set to 46 bits.
Change-Id: I0bbe6c962ffc7d5dc722f1cacf55bc0d0615db59
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
Without skipping of DRHD generation for non-PCIe stack, the OS
kernel detects incorrect DMAR table with following messages:
[ 0.561817] Your BIOS is broken; DMAR reported at address 0
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I098605daf12a264f390613581427ec722afcddaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
This CL fixes the CPU Throttling issue.
BUG=b:167472333
TEST=Build and boot dedede and observe the slope and offset values
getting updated in the fsp debug log
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I3fa32218040263f0abef8b9dd4c52efb31289fd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
This reverts commit 69589294c205b616e80cafbbfb0b33e105a75386.
No reason was given why this should deviate from the other platforms
and the author can't explain it.
Change-Id: I2e8d6f9bd4ebba69b6f7cdd9a1c5d08aaf2e798f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: Ib329648f77acecccb0ced1806f61be252d03f2f4
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45869
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
For now only implement for one socket and some of the fields
are hard-coded for DDR4 including memory device type, data width
and ECC support.
Change-Id: I3cb72d18027d972140828970206834ff55b72022
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
With CPX-SP FSP, PCH IOAPIC handles the first 120(0x78) GSIs. Correct
the coreboot assignment of GSIs for IO APICs.
Without this patch, there are following target OS boot messages:
[ 1.098771] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119
[ 1.099159] GSI range [24-31] for new IOAPIC conflicts with GSI[0-119]
After this patch, the boot messages are:
[ 0.399498] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119
[ 0.399848] IOAPIC[1]: apic_id 9, version 32, address 0xfec01000, GSI 120-127
Also without this patch, there is boot stability issue. About one in
20 reboots, the target OS fails to boot with following failure:
[ 4.325795] mce: [Hardware Error]: Machine check events logged
[ 4.326597] mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 9: ee2000000003110a
[ 4.327594] mce: [Hardware Error]: TSC 0 ADDR fe9e0000 MISC 228aa040101086
[ 4.328596] mce: [Hardware Error]: PROCESSOR 0:5065b TIME 1601443875 SOCKET 0 APIC 0 microcode 700001d
The MCE error happens in bank 9. The Model specific error code
shows it is about SAD_ERR_WB_TO_MMIO error (doc 604926), which means
something goes wrong when cache write back to mmio. It is a generic
transaction type error in level 2.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I45e941591300dad6d583a6dcb41f45e984753c07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45941
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There's no need to make so much noise when writing IOBP registers.
Change-Id: I1fbb6e409375240544b9b5e810523f9471435f2f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Add gfx.asl file for all IA SOCs to allow for graphics-related ACPI
devices and methods.
TEST=Able to build and boot TGL platform
Dump and disassemble DSDT, verify GFX0 device present as below
Device (GFX0)
{
Name (_ADR, 0x00020000) // _ADR: Address
}
Change-Id: I5560e900a77872552df1064dc3b7a8148e35d682
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
This patch moves gfx.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.
TEST=Able to build and boot CML platform.
1) Dump and disassemble DSDT, verify GFX0 device present inside
common gfx.asl is still there.
2) Verify no ACPI error seen while running 'dmesg` from console.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ie34181a6783d348265cf4299dec5c41e7f4f736f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add an empty SPD in SPD_SOURCES when creating a new variant of
hatch, volteer, waddledee, or waddledoo, so that coreboot can build
successfully.
For variants that use spd_tools, add an empty mem_parts_used.txt so
that the developer can add the supported memory parts and regenerate
the Makefile.inc with the correct SPD references.
Add an empty SPD for LPDDR4x for waddledee and waddledoo to use.
BUG=b:169422833
TEST=create a new variant of hatch, volteer, waddledee, and waddledoo.
Observe that each one succeeds.
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I06dfb6103701bf8949180595f1e98fac48bcc585
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Prepare for common ACPI code.
Move get_srat_memory_entries() from soc_util.c to soc_acpi.c where
the other srat ACPI functions are located.
Change-Id: If26641497e1c16d5cf493490711aa08d6e1cb640
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45846
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Continue preparations for common ACPI code.
Add code from skx and common/acpi to check the SCI register
instead of using a define.
Change-Id: I6b638d28775320894a6ab24ef486e67c181591eb
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45844
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Prepare for common ACPI code. Move skx soc ACPI functions to a
separate file.
Change-Id: I12526c17a0dcbc45494ae19c8abaf8bf9a1eab47
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Prepare for common ACPI code. Move cpx soc ACPI functions to a
separate file, soc_acpi.c
Change-Id: I4aaca660e2f94d856676681417ae6c5d8c28a1f1
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Reorder the functions to make it easier to compare with
soc/intel/common/block/acpi/acpi.c and cpx/acpi.c.
Move the xeon_sp specific functions to the top.
Change-Id: I7bc147781261c2fc39374f5bfe3ba79047b4993a
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Reorder the functions to make it easier to compare with
soc/intel/common/block/acpi/acpi.c.
Move the xeon_sp specific functions to the top.
Change-Id: I9034eb774a14ee1e2f9b16c7bd7673ebad69c113
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Continue separating the CPU from the PCH.
Move the PCH IRQ ASL from the uncore_irq.asl to a new file,
pch_irq.asl.
Change-Id: Iaf8ae87ecc9f8365cc093516f15d9c5a31c7d1d5
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Move ACPI macros to a header file to be used in multiple
ASL files.
This could be moved to intel/common in the future to reduce
the amount of duplicate ASL code.
Tested by checking build/dsdt.asl doesn't change.
Change-Id: Id2441763fe335154048c9a584a227a18e8c5391c
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Remove the NumElements and allow the ASL compiler to fill them in.
This is safer than hard coding the NumElements.
For Package (NumElements) {PackageList}, "If NumElements is absent,
it is automatically set by the ASL compiler to match the number of
elements in the PackageList" ACPI v6.2 sec 19.6.101.
Change-Id: I73df9e31011ad0861d4755fdbcbbd93e4e0b5a51
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Refer to
commit 0359d9d (soc/intel: Make use of PMC low power program
from common block)
commit 1366e44 (soc/intel: Move pch_enable_ioapic() to common
code)
commit 78463a7 (soc/intel: Move soc_pch_pirq_init() to common code)
commit 8971ccd (soc/intel: Move pch_misc_init() to common code)
for details
Change-Id: Ic83d332cf2bfe8eded1667dd1503e718d854f10b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake up from sleep states.
3. Add SoC ASL code in ASL 2.0 syntax for SoC IPs like IPU, ISH,
LAN, HDA etc.
Change-Id: I7509e8c46038b1edfc501db74e763f198efb56ab
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
There is requirement to change PM flow for S0ix along with TBT firmware
update under device attached and no device attached scenarios. This
change invokes D3CE and D3CX in DMA _PS3 and _PS0 respectively.
BUG=b:158777291
TEST=Validated s0ix cycles for USB4 device attached and no device
attached test cases along with updated TBT firmware rev35.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Iebc8065fe4c8600960d089577608890ab12a95fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Consolidate all weak declarations of mainboard_get_dram_part_num() to
instead use the common definition in lib/spd_bin.c.
BUG=b:168724473
TEST="emerge-volteer coreboot && emerge-nocturne coreboot &&
emerge-dedede coreboot" and verify build succeeds without error.
Change-Id: I322899c080ab7ebcf1cdcad3ce3dfa1d022864d1
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
BUG=b:169774661, b:168724473
TEST="emerge-volteer coreboot && emerge-nocturne coreboot &&
emerge-dedede coreboot" and verify they build successfully.
Change-Id: I8b228475621ca1035fe13f8311355fc3b926e897
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Change mainboard_get_dram_part_num() to return a constant character
pointer to a null-terminated C string and to take no input
parameters. This also addresses the issue that different SOCs and
motherboards were using different definitions for
mainboard_get_dram_part_num by consolidating to a single definition.
BUG=b:169774661, b:168724473
TEST="emerge-volteer coreboot && emerge-dedede coreboot && emerge-hatch
coreboot" and verify build completes successfully.
Change-Id: Ie7664eab65a2b9e25b7853bf68baf2525b040487
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45873
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add missing __weak declaration to Elkhart Lake's definition of
mainboard_get_dram_part_num().
BUG=b:169774482, b:168724473
TEST=none
Change-Id: I883d662315a9ab91eb6183ebcdfd7e7cc8064c64
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45871
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I8deaeb29abed097d536f1c3c44606a549c6af4e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
This patch moves ish.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.
TEST=Able to build and boot TGL, CML platform.
1) Dump and disassemble DSDT, verify ISHB device present inside
common ish.asl is still there with correct _ADR value.
2) Verify no ACPI error seen while running 'dmesg` from console.
CML platform:
Device (ISHB)
{
Name (_ADR, 0x00130000) // _ADR: Address
Name (_DDN, "Integrated Sensor Hub Controller") //_DDN: DOS Device Name
}
TGL/JSL platform:
Device (ISHB)
{
Name (_ADR, 0x00120000) // _ADR: Address
Name (_DDN, "Integrated Sensor Hub Controller") //_DDN: DOS Device Name
}
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I33c1649d7a632c7b147e1bf307cfb5c1dfd84c0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
This patch moves platform.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.
TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify _PIC method present inside
common platform.asl is still there.
2) Verify no ACPI error seen while running 'dmesg` from console.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I5189b03d6abfaec39882d28b40a9bfa002128be3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I3fcd971402e540d91a7392ca58175eb3ecc24cec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45981
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Refer _WAK and _PTS ASL functions from common platform.asl
TEST=Dump and disassemble DSDT, verify all methods present inside
common platform.asl like _WAK, _PTS etc. are still there.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I625e42b3c49abbb3595a4307da5fc24850a98fbb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45980
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch moves smbus.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.
TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify SBUS device present inside
common smbus.asl is still there.
2) Verify no ACPI error seen while running 'dmesg` from console.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ib1ae48f7ece3e521501d92c40cd551287ea2f1ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Delete SoC local copy of ipu.asl and refer from common block ipu.asl
TEST=Dump and disassemble DSDT on tglrvp, verify IPU0 device
present there.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I6a0f8a919092f7bbcd64d4791746d30fdee33894
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I8c7363d442ed40c36fc01dc3608bab864865f29d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45977
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
IMGU->IPU0 to align with other SoC IPU entires.
TEST=Dump and disassemble DSDT on poppy, verify IPU0 device
present there.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I803c01f9156a56dbd903b6ba7897cc0f96b0a26a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
This patch moves pch_glan.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.
TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify GLAN device present inside
common pch_glan.asl is still there.
2) Verify no ACPI error seen while running 'dmesg` from console.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I479678c864eba39e5ab04f658600e8cba48198ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
List of changes:
1. Add required SoC programming till ramstage
2. Include only required headers into include/soc
3. Add CPU, PCH and SA EDS document number and chapter number
4. Fill required FSP-S UPD to call FSP-S API
Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Rename pci_irq.asl to pci_irqs.asl to match other intel soc file
names. This makes comparing differences much easier.
Change-Id: I622dfef675c3df2dff7a3024ccbe14c356a5cd86
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45834
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Prepare for merging cpx and skx pci_devs.h.
Remove duplicate defines. Move defines so they match each other.
Checked TiogaPass and DeltaLake BUILD_TIMELESS.
Change-Id: I146dd9e3f7eba053977d48dcf34d927dea310059
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45833
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
List of changes:
1. Select PMC_LOW_POWER_MODE_PROGRAM from applicable SoC directory
2. Remove redundant PMC programming from SoC and refer to common
code block
3. Remove unused 'reg8' and 'reg32' variable as applicable from SoC
function.
Change-Id: I18894c49cfc6e88675b5fb71bca0412e5639fb4b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45796
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
List of changes:
1. Create Kconfig to select pmc low power program by SoC
2. Add API to make ACPI timer disable
3. Add API to ignore XTAL shutdown for SLP_S0# assertion
Change-Id: I017ddc772f02ccba889d316319ab3d5626b80ba5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45794
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
List of changes:
1. Move pch_misc_init() into common block code.
2. Remove redundant LPC functions from SoC directory and
refer from block/lpc directory.
3. Create macros for IO port 0x61 and 0x70 as applicable.
TEST=Able to build and boot hatch and tglrvp platform without seeing
any functional impact.
Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
List of changes:
1. Rename soc_pch_pirq_init() as pch_pirq_init() and
move into common block code.
2. Remove redundant LPC functions from SoC directory and
refer from block/lpc directory.
TEST=Able to build and boot hatch and tglrvp platform without seeing
any functional impact.
Change-Id: I856b5ca024e58fd14b4d1721f23d9516a283ebf8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
List of changes:
1. Move pch_enable_ioapic() into common block code.
2. Remove redundant LPC functions from SoC directory and
refer from block/lpc directory.
TEST=Able to build and boot hatch and tglrvp platform without seeing
any functional impact.
Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Move duplicate .h files to top level xeon_sp/include/soc from
silicon specific cpx/include/soc and skx/include/soc.
Change-Id: I11d8a95a4b2f9451615b236798b3bd030c724858
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45221
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Clean up acpi.h in preparation for merging with cpx/ acpi.* files
Change-Id: I2a0dc964eeb7f8da53676eb94c4385ff8668f6af
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45218
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Move and use the common xeon_sp/cpx/acpi asl for skx/.
There were only minor whitespace differences between the directories.
Update the mainboards to build the moved files.
TiogaPass coreboot.rom checked with BUILD_TIMELESS.
Change-Id: I5058a3fe8d96075a266fb92f10707bb94308c85b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45217
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The skx uncore ACPI scope was missing the \ on \_SB causing
the uncore IRQs to not be in the namespace. This addresses
ACPI uncore IRQ routing issues. This was found preparing
skx acpi to match cpx acpi for merging in the future.
Check scope in dsdt.asl in tiogapass build.
Change-Id: I799042babbe60287e5e4ec60b21c08d57ccda04b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45269
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Prepare for merge with cpx.
Use the C style operators instead of the ACPI1.x polish notation.
This is much easier to read and matches the cpx code.
This generates the same ASL code.
Checked with BUILD_TIMELESS on TiogaPass.
Change-Id: Id44138894d2ffed4c93afe5d4bbb4d59b538b577
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45270
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update the skx uncore ACPI routing tables to match cpx. This
adds the IRQ routing for B-D for legacy and IOAPIC modes.
Change-Id: Iac0ffdb467a78b9befe7402c074835ea602d43c8
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Increase the DRAM cache size for Braswell to address the
compilation error
Cache as RAM area too full
when moving the mrc_cache writeback to romstage. We need to increase
this first before landing the CL moving mrc_cache writeback to
romstage.
BUG=b:150502246
BRANCH=None
TEST=Able to successfully compile braswell boards
Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45827
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate
older x86 platforms that don't allow writing to SPI flash when early
stages are running XIP from flash. If
BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected,
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms
that write to flash in the earlier stages, assuming that they have
that capability.
BUG=b:150502246
BRANCH=None
TEST=diff the coreboot.rom files resulting from running
./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless
with and without this change to make sure that there was no
difference. Also did this for GOOGLE_CANDY board, which is
baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
enabled).
Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Set TmeEnable FSP-M upd based on config.
TEST: TME ENABLE and LOCK bits get set when Tme is enabled.
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: Ia804c88057e17844f055fd852fc0b36cfe316432
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
