| Age | Commit message (Collapse) | Author |
|---|
|
Add minimal MP init. No SMM, no turbo, not c/p states.
TEST=boot linux kernel, observe CPUs are online, schedule tasks
and perform useful work. Tested on Cedar Island CRB with only 1
socket populated
Change-Id: I0af374ab3956009e9208917d911d29eb21db6069
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
|
|
There are boards that do not need a specific domain_vr_config because
the defaults provided by the soc code are sufficient. Currently, this
means that these boards can't benefit from lower power states (PSI 3
and 4) because the settings default to being disabled since at the time
the defaults have been defined (2015) there were bugs in FSP in this
regard.
Set the default values of psiXenable to 1 for boards that do not have a
domain_vr_config setting in their devicetree, just like Cannon Lake
does.
Boards that have a domain_vr_config and set their specific settings are
not affected at all. Currently, there are only three boards that have
no domain_vr_config:
- supermicro/x11-lga1151-series
These boards have a MPS MP2955 which we can assume support for PS3
(the MP2965 and MP2935 support it, too).
S-series CPUs with a 1151 socket do not have C9/C10 but only C8 and
since only C10 makes use of PS4, those CPUs won't ever request PS4.
That means we do not need to disable it explicitly for these boards.
- 51nb/x210:
Needs testing and/or VR datasheet check for PS3/PS4 support
Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39980
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add hook to generate ACPI methods in SSDT for screen backlight control.
To make use of this, individual boards will need to
include default_brightness_levels.asl in their dsdt, as
well as add 'register "gfx" = "GMA_STATIC_DISPLAYS(0)"' to
their devicetree.
Change-Id: I0adccc6c8bee71d3c1b7840518308c8dc8ea2d81
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add hook to generate ACPI methods in SSDT for screen backlight control.
To make use of this, individual boards will need to
include default_brightness_levels.asl in their dsdt, as
well as add 'register "gfx" = "GMA_STATIC_DISPLAYS(0)"' to
their devicetree.
Change-Id: I0b7fc45bda3aaf89306bedb579fb1e9f8ce07926
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add framework to generate ACPI methods in SSDT for
screen backlight control. Adjust params for gtt_ methods
to match prototypes in i915.h and avoid conflicts.
To make use of this, individual boards will need to
include default_brightness_levels.asl in their dsdt, as
well as add 'register "gfx" = "GMA_STATIC_DISPLAYS(0)"' to
their devicetree.
Change-Id: If93b7690ef36b5d19ca43957e8a1bef91ec5821d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
These two identifiers were always very confusing. We're not filling and
injecting generators. We are filling SSDTs and injecting into the DSDT.
So drop the `_generator` suffix. Hopefully, this also makes ACPI look a
little less scary.
Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: David Guckian
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change adds new memory topologies (SODIMM, MIXED) that are
supported by DDR4 and macros required for DDR4 support.
Memory initialization support for DDR4 will be added in a follow-up
change.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I4b565c3d71bbf437da64ac29597cc19e58f1b98a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
This change reorganizes memory initialization code for LPDDR4x on
TGL to allow sharing of code when adding support for other memory
types. In follow-up changes, support for DDR4 will be added.
1. It adds configuration for memory topology which is currently only
MEMORY_DOWN, however DDR4 requires more topologies to be
supported.
2. spd_info structure is organized to allow mixed topologies as well.
3. DQ/DQS maps are organized to reflect hardware configuration.
TEST=Verified that volteer still boots and memory initialization is
successful.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib625f2ab30a6e1362a310d9abb3f2051f85c3013
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
This implementation removes all JSL references from the TGL SoC code.
Additionally, mainboard code changes are done to support build.
BUG=b:150217037
TEST=build tglrvp and volteer
Change-Id: I18853aba8b1e6ff7d37c03e8dae2521719c7c727
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop
referring from soc/intel/tigerlake.
Addtionally mainboard changes are done to support build.
BUG=b:150217037
TEST=Build and boot waddledoo. Build jasperlake_rvp and volteer board.
Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Include types.h in src/soc/intel/common/block/include/intelblocks/cse.h
to use type bool.
Without this, there can be a build error like below,
src/soc/intel/common/block/include/intelblocks/cse.h:208:1:
error: unknown type name 'bool'; did you mean '_Bool'?
bool cse_is_hfs1_com_soft_temp_disable(void);
^~~~
_Bool
src/soc/intel/common/block/include/intelblocks/cse.h:214:1:
error: unknown type name 'bool'; did you mean '_Bool'?
bool cse_is_hfs3_fw_sku_custom(void);
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: I92ee533bca7dc255f7a341b2a68bbc09900996a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
After measured boot is decoupled from verified boot in CB:35077,
vboot_platform_is_resuming() is never vboot-specific, thus it is
renamed to platform_is_resuming() and declared in bootmode.h.
Change-Id: I29b5b88af0576c34c10cfbd99659a5cdc0c75842
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Exit print_me_fw_version if CSE is disabled.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: Ie3f1c2a5a7f96371a0da872efc3308850c382ba7
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
|
|
For quite a bit now we are extending the FSP_USE_REPO option to be
available for all Intel SoCs. This results in a list being not only
hard to maintain but also prone to errors.
To change that behaviour this commit introduces the
HAVE_INTEL_FSP_REPO config option for SoCs that are supported from within
3rdparty/fsp.
If a SoC selects HAVE_INTEL_FSP_REPO the config option FSP_USE_REPO is
selected by default, but can be still deselected by the user in menuconfig.
Change-Id: I68ae373ce591f06073064aa75aac32ceca8fa1cc
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37582
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
For newer Intel graphics(>=11), The DDI port max lanes are set to 4 by
default. And kernel driver no longer relies on coreboot to provide
information via DDI_BUF_CTL_A(for DDI port A) register programming.
Hence removing this code.
BUG=b:150788968
BRANCH=None
TEST=checked jslrvp and tglrvp compilation and boot.
Change-Id: I32692501b60f48a07b8fbb9bb3a755b18f4b3ea9
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39313
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
FSP UPD TcssAuxOri is used for setting the IOM_TYPEC_SW_CONFIGURATION_3.
Configure TcssAuxOri to retimer enabled on the port 2 Type-C port.
This setting informs the SoC that a retimer is taking care of SBU
orientation therefore it does not need to do any flipping.
The IOM_TYPEC_SW_CONFIGURATION_3 is a bitfield that controls the aux
orientation settings for the Type-C ports. The TGL EDS describes this
setting and what each bit represents.
Reference section 3.6.5 in TGL EDS #575681
BUG=b:145943811
BRANCH=none
TEST=Boot to OS and check Type-C port1 Display on volteer,
Connecting Type-C display should work regardless of Type-C cable
orientation.
Change-Id: Iae356113cbdc72983f800060b1ebebe3c66b9daf
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39459
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add struct i915_gpu_controller_info for boards to supply info needed
to generate ACPI backlight control SSDT. Hook into soc/common framework
by implementing intel_igd_get_controller_info().
Change-Id: I70e280e54d78e69a335f9a382261193c593ce430
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Add framework to hook up the generic src/drivers/intel/gma ACPI
backlight control for platforms using SOC_INTEL_COMMON_BLOCK_GRAPHICS.
Add a weak function to get the struct i915_gpu_controller_info needed
to generate the SSDT, defaulting to NULL, which SoC's will override.
Each SoC will need to override intel_igd_get_controller_info, and
individual boards will need to populate the struct in order for
the backlight control methods to be added to the SSDT.
Change-Id: I993770fdcd0a28cee756df2bd6a795498f175952
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32549
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This is a follow-up patch to initial copy patch for Jasper Lake SoC.
Remove all Tiger Lake specfic code from Jasper Lake SoC code.
BUG=b:150217037
Change-Id: I44dc6bf55ca18a3f0c350f5c3e9fae2996958648
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39824
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This is a copy patch from Tiger Lake SoC code.
The only changes done on top of copy is changing below configs:
1. SOC_INTEL_TIGERLAKE -> SOC_INTEL_TIGERLAKE_COPY
2. SOC_INTEL_JASPERLAKE -> SOC_INTEL_JASPERLAKE_COPY
3. SOC_INTEL_TIGERLAKE_BASE -> SOC_INTEL_TIGERLAKE_BASE_COPY
We started with initial assumption that JSL and TGL can co-exist.
But now we see the SoC code in Tiger Lake is relying on too many
compile-time directives to make two SoCs co-exist. Some of the
differences are listed below:
-> Kconfig: Multiple Kconfig options using
if SOC_INTEL_{TIGERLAKE/JASPERLAKE}
-> GPIO: GPIO communities have their own differences.
This requires conditional checks in gpio.asl, gpio.c, gpio*.h,
pmc.h and gpio.asl
-> PCI IRQs: Set up differently for JSL and TGL
-> PCIe: Number of Root ports differ.
-> eMMC/SD: Only supported on JSL.
-> USB: Number of USB port are different for JSL and TGL.
-> Memory configuration parameters are different for JSL and TGL.
-> FSP parameters for JSL and TGL are different.
The split of JSL and TGL SoC code is planned as below:
1. Copy Tiger Lake SoC code as is, and change SoC Kconfig
to avoid conflicts with current mainboard builds.
2. Clean up TGL code out of copy patch done in step 1.
Make it JSL only code. The SoC config still kept as
SOC_INTEL_JASPERLAKE_COPY.
3. Change JSL SOC Kconfig from SOC_INTEL_JASPERLAKE_COPY to
SOC_INTEL_JASPERLAKE, dedede and jasperlake_rvp boards can
bind to SoC code from soc/intel/jasperlake. This step establishes
Jasper Lake as a separate SoC.
4. Clean up current JSL code from TGL code. This step establishes
Tiger Lake as a separate SoC.
BUG=b:150217037
Change-Id: I9c33f478a2f8ed5e2d8e7815821d13044d35d388
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
This adds barebones support.
What works:
* Linux kernel boots fine
* SIRQ and PCH interupts work fine (only in IOAPIC mode)
* PCH devices are usable
What doesn't:
* MP init is not there yet, only 1 CPU is up
* SMM is not supported
* GPIO is not available
* All IIO and extended bus numbers enumeration is not yet available
* Warm reset flow is untested
* MRC cache save/load
TEST=boots into Linux
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I7c987badc3c53f16ad178369c7e0906d6596e465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39713
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
In order to use early serial output we need to enable P2SB BAR0, because
that allows PCR access to PCH registers.
TEST=tested on OCP Tioga Pass
Change-Id: I476f90b2df67b8045582f0b72dd680dea5a9a275
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Refactor the code and split it into Xeon common and CPU-specific code.
Move most Skylake-SP code into skx/ and keep common code in the current
folder.
This is a preparation for future work that will enable next
generation server CPU.
TEST=Tested on OCP Tioga Pass. There does not seem to be degradation
of stability as far as I could tell.
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Sometimes coreboot needs to compile external code (e.g.
vboot_reference) using its own set of system header files.
When these headers don't line up with C Standard Library,
it causes problems.
Create stdio.h and stdarg.h header files. Relocate snprintf
into stdio.h and vsnprintf into stdarg.h from string.h.
Chain include these header files from string.h, since coreboot
doesn't care so much about the legacy POSIX location of these
functions.
Also move va_* definitions from vtxprintf.h into stdarg.h where
they belong (in POSIX). Just use our own definitions regardless
of GCC or LLVM.
Add string.h header to a few C files which should have had it
in the first place.
BUG=b:124141368
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I7223cb96e745e11c82d4012c6671a51ced3297c2
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Make use of the publicly-available FSP binaries and headers for Comet
Lake. Also, remove the Comet Lake header files from src/vendorcode,
since they are no longer necessary.
Change-Id: I392cc7ee3bf5aa21753efd6eab4abd643b65ff94
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39372
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
To use Intel common block LPC function that enables the IO ranges
defined in devicetree.cb.
Tested on OCP Tioga Pass with BMC LPC working.
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I675489d3c66dad259e4101a17300176f6c0e8bd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38994
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Configure Hyperthreading based on devicetree
BUG=none
TEST= Build and boot with FSP log and check Hyperthread setting
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Idc94e6b8ecd59a43be60bf60dc7dd0811ac0350b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39683
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The PWM-granularity chicken bit in the Wildcat Point and Lynx Point
PCHs has actually the opposite meaning of the one for Sunrise Point
and later. When the bit is set, we get a divider of 16, when it's
unset 128. Flip the bit!
Change-Id: I1dbde1915d8b269c11643a1636565a560eb07334
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
According to the latest Tigerlake Platform FSP Integration Guide, the
minimum amount of stack needed for FSP-M is 256KiB. Change
DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB previously determined
empirically). JSL requires 192KiB.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic9be6446c4db7f62479deab06ebeba2c7326e681
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here for Intel CPUs only.
Tested on:
* X11SSH (Kabylake)
* CFL Platform
* Asus P8Z77-V LX2 and Windows 10
FWTS does not return FAIL anymore on ACPI tests
Tested-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Tested with BUILD_TIMELESS=1, Facebook FBG1701 remains unaffected.
Change-Id: I784a5ddc1a8dcbfb960ce970b28b850244a47773
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39663
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add 8-core desktop CPU support by adding the corresponding PCI IDs.
Tested using "Intel Core(TM) i7-9700E".
Change-Id: I7a2e2e5fd1796deff81b032450242fb58031526d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: I487fb53bb2b011d214f002fc200ade2f128a4cc6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
This patch makes PCH_DEV_UART3 macro referring to _PCH_DEV()
rather calling _PCH_DEVFN().
Change-Id: I7bc060c3c5f1e0a0fed194704b4940db73f46985
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Enable GPIO functionality in verstage so platforms can read a
PCH GPIO in verstage to determine recovery mode.
BUG=b:151102807
TEST=make build successful
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I4e3b9da307dcf59ab251d8a6a5e09c2a3cfc59fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39501
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I6cf3484e46eebd3dc753d0903ea8555712b99b7e
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25440
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Steve Mooney
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
PMC core driver in OS provides debug hooks to developers and end users
to quickly figure out why their platform is not entering a deeper idle
state such as S0ix. This patch adds INT33A1, a required ACPI device,
to support that PMC core driver in tigerlake platform.
BUG=b:146236297
BRANCH=none
TEST="Build and flash volteer and verify it boots to kernel.
Checked for valid files under /sys/kernel/debug/pmc_core."
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Ib7e583dc2943461a41d2a7ebde1f16a58a118975
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39587
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
PMC core OS driver (intel_pmc_core.c in linux kernel) provides debug
hooks to developers and end users to quickly figure out why their
platform is not entering a deeper idle state such as S0ix.
This patch adds INT33A1 ACPI device to support PMC core OS
driver. Any SoC that supports this feature would include this asl file
to enable the support.
BUG=b:146236297
BRANCH=none
TEST="Build and flash volteer and verify it boots to kernel"
Change-Id: Ib4edc7b636725177d508b62d15633534e9f44236
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Reviewed-on: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/coreboot-intel-private/jsl-tgl/+/2362512
Reviewed-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.corp-partner.google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.corp-partner.google.com>
Commit-Queue: Alex Levin <levinale@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39370
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use CACHE_ROM_BASE and CACHE_ROM_SIZE for code caching
parameters.
Tested on OCP Tioga Pass.
Change-Id: Ibba133d9f8fdfbdfae9a0e8e698356a3ca9ba424
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39625
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Jasper Lake RVP has DDR4 variant which uses SMBus address to read SPD
data. So, add support to read SPD data from SMBUS.
BUG=None
BRANCH=None
TEST=Check compilation for Jasper Lake RVP and check memory training passes.
Change-Id: I94f8707c731c8afa1106e387a246c000bd53a654
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39401
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
We were including stddefs.h and stdint.h but compilation fails when we
use 'bool' type in file.
Removing stddef.h and stdint.h and including 'types.h' which includes
all data types
BUG=None
BRANCH=None
TEST=Check if compilation passes when bool is used
Change-Id: I4c9001f729f3103deba9d1fd631a8942c23276ee
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
|
|
Correct number of gpio pad group for Jasper Lake SoC.
BUG=None
BRANCH=None
Test=Code compilation for Jasper Lake RVP
Change-Id: I381d0e48430e933569a3b22b66b4e6077383e9e2
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
|
|
FSP needs to know to allow the root ports for USB4/TBT to be enabled
This patch may need additional checks for each board as it might not
be the right thing to turn them all on for every Tiger Lake board.
BUG=b:141609883
BRANCH=NONE
TEST=Built image and verified that the root ports were visible with lspci
Change-Id: I3f020e20fa8e9fd1ac69d883f4dc1fcbb330a3bf
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Enables Gaussian Mixture Model (GMM) if the pci device is enabled in the
devicetree for Gemini Lake
This ports commit 03ddd190fd6a2e91b16e6fd8a101cf4e11d7cd7b
BUG=b:151115705
BRANCH=none
TEST=Flashed to Chromebook, PCI device enabled in cbmem, userspace app
that uses device still works
Change-Id: I72b1dd78705894f0462c7fbe89b76551950c2392
Signed-off-by: Franklin He <franklinh@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
|
|
The current implementation doesn't allow custom values for the LPC IO
decodes and IO enables.
Add the lpc_ioe and lpc_iod values. If they are not zero, they will be
used instead of the current handling for COMA and COMB.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: Iad7bb0e44739e8d656a542c79af7f98a4e9bde69
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38748
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Method RAOW is assuming that the first argument is a Field object
and writing to it expecting the register to get updated. However,
the callers are passing in the value of the Field object instead.
This eventually is resulting the IMGCLK not getting enable/disabled on the
platform.
Fix this by sending the exact address of the register to be updated.
Also MCCT was setting the clock frequency in both case i.e, Clock Enable
and Disable. Split the MCCT method in two, MCON and MCOF to fix the sequencing
like below
MCON:
Set frequency
Enable clock
MCOF:
Disable clock
Also, make use of MCON and MCOF methods for camera clock control in tglrvp.
This is to avoid the buildbot marking the patch unstable.
BUG=None
BRANCH=None
TEST=Build and Boot waddledoo board and verified that IMGCLKOUT for
world facing camera is enabled/disabled and able to capture images.
Build and Boot Tiger Lake RVP board and verified that IMGCLKOUT for
world facing camera is enabled/disabled and able to capture images.
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: I8b886255d5f38819502ae1f4af0851b5a0922b22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39498
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Set FSP params PchSirqEnable/PchSirqMode based on board
setting of serirq_mode. Matches implementation on Skylake.
This is a no-change for existing boards since the default
remains SERIRQ_QUIET mode.
Tested on system76 galp3-c, out-of-tree WHL-U board
Change-Id: I9ad4f5a6c7391fc6e813ec1306c708f449a69f59
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Nathaniel L Desimone <nathaniel.l.desimone@intel.com>
|
|
Function was copied as part of upstreaming from Chromium tree,
but isn't used and has never been used best I can tell.
Change-Id: I53b8702c97d7a694450aa05ba49da6c26c30f725
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add ACPI Object for ISH SSDT
Enable/disable ISH based on devicetree
BRANCH=none
BUG=b:145946347
TEST=boot to OS with TGL RVP UP3
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Signed-off-by: li feng <li1.feng@intel.com>
Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
|
|
Change PMC IPC HID from INT34D2 to INTC1026 along with
new kernel pmc ipc driver.
BUG=b:148949891
BRANCH=none
TEST=Boot on Volteer and validate DP tunneling.
Change-Id: I987e7bf76ad1f8ff534101c80661f7c027a60b51
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
|
|
This patch ensures all IA chipsets and common Kconfig files
are getting included without specifying dedicated chipset names.
TEST=Able to compile CML and TGL RVP.
Change-Id: Ic2d8a8ac1c4acfabd4ded1bfd4ff359e820e174b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39530
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Check prerequisites before sending GLOBAL RESET command to CSE.
TEST=Verified on hatch.
Change-Id: Ia583e4033f15ec20e942202fa78e7884cf370ce4
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Below changes are done:
1. Allow execution of HMRFPO_ENABLE command if CSE meets below
prerequisites:
- Current operation mode(COM) is Normal and Curret working state(CWS)
is Normal.
-(or) COM is Soft Temp Disable and CWS is Normal if ME's
Firmware SKU is Custom.
2. Check response status.
3. Add documentation for send_hmrfpo_enable_msg().
4. Rename padding field of hmrfpo_enable_resp to reserved.
The HMRFPO (Host ME Region Flash Protection Override) mode prevents CSE to
execute SPI I/O cycles to CSE region, and unlocks the CSE region to perform
updates to it. This command is only valid before EOP(End of Post).
For Custom SKU, follow below procedure to place CSE in HMRFPO mode:
1. Ensure CSE boots from BP1. When CSE boots from BP1, it will have
opmode Temp Disable Mode.
2. Send HMRFPO_ENABLE command to CSE. Then, CSE enters HMRFPO mode.
CSE Firmware Custom SKU Image Layout:
= [RO] + [RW + DATA PART] = [BP1] + [BP2 + DATA PART]
Here, BP1 will have reduced functionality of BP2, and the BP1 will be
CSE's RO partition and [BP2 + DATA PART] together will represent
CSE's RW partition. CSE can boot from either BP1(RO) or BP2(RW).
CSE Image Layout in Consumer SKU: BP2 + BP3 + DATA PART
TEST=Verfied on hatch board.
Change-Id: I7c87998fa105947e5ba4638a8e68625e46703448
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: I7a5d7bb476c33ab995136eb47ef0258b483a42ef
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: I117c8d2f71824292c4ca87b6f9434d2106bb512d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Update RP number to 12 according to PCH EDS#576591 vol1 rev1.2.
BUG=b:151208838
TEST=build RVP successfully
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iabdbfd99f7154741c16da53bcd9d1c7ca4f81129
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
|
|
Check for dev enabled status for CNVi and update the
UPD accordingly.
BUG=none
BRANCH=none
TEST=Build and boot tglrvp
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I15a03cc70f12e094badf942dd81f22bd09531051
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Add config to override CpuRatio or setting CpuRatio to
allowed maximum processor non-turbo ratio.
BUG=151175469
BRANCH=none
TEST=Build and boot tglrvp and observe there is no extra reset
in meminit.
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I2fa883b443d0a4c77d62275faeacd1ed2c67a97c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39493
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change VmxEnable UPD value based on Kconfig ENABLE_VMX
BUG=None
TEST=Built image and booted to kernel.
Change-Id: I725474643193223865a135813cf882fd7636d24a
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
|
|
Tigerlake platform supports Virtualization Technology for Directed I/O.
Enable VT-d feature and generate DMAR ACPI table.
BUG=None
TEST=Booted to kernel and "dmesg | grep DMAR" to verify the DMAR ACPI
remapping table existence. Retrieve /sys/firmware/acpi/tables/DMAR and
"iasl -d DMAR" to check all entries.
Change-Id: Ib89d0835385487735c63062a084794d9da19605e
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
|
|
commit 7f9ceef disables TCO SMIs unless specifically enabled, so help
the linker throw out the function that handles them in that case.
Change-Id: Ia3c93b46e979fb8b99282875b188415f249d38dd
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Michael Niewöhner
|
|
Set value for PcieRpL1Substates according to devicetree.
Chip config parameter PcieRpL1Substates uses (UPD value + 1)
because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
In order to ensure that mainboard setting does not disable L1 substates
incorrectly, chip config parameter values are offset by 1 with 0 meaning
use FSP UPD default.
get_l1_substate_control() ensures that the right UPD value is set in
fsp_params.
Chip config parameter values
0: Use FSP UPD default
1: Disable L1 substates
2: Use L1.1
3: Use L1.2 (FSP UPD default)
BUG=none
BRANCH=none
TEST=Boot up and check FSP log for PCIe config for this values
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I66743a29ad182bd49b501ae73b79270a9eb88450
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39412
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Check for dev enabled status for HDA controller and
update the UPD accordingly.
BUG=151174264
BRANCH=none
TEST=Build and boot tglrvp
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Id5dfff275ed9906852ef7eb7461fbe89a3a115c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39441
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This adds case intrusion detection to the SMI handler. At this point one
can add the code to be executed when the INTRUDER signal gets asserted
(iow: when the case is opened).
Examples:
- issue a warning
- trigger an NMI
- call poweroff()
- ...
Tested on X11SSM-F.
Change-Id: Ifad675bb09215ada760efebdcd915958febf5778
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
TEST=Verified that dmidecode produces output identical to private repo
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I951ea94c280b7dd5b67f320a264d13fca82a4596
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39359
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
select correct UART settings according to Kconfig
DEBUG_INTERFACE_UART: Legacy UART
DEBUG_INTERFACE_SERIAL_IO: PCH UART
Add check for DEBUG_INTERFACE_TRACEHUB selection and set
"PcdDebugInterfaceFlags" UPD accordingly.
BUG=None
TEST=boot jslrvp board with Debug FSP and check FSP UART log
Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
|
|
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I43cccd32589d75a9b0c7e60f8c82b19bbe6b69a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
|
|
Set TCO to issue an SMI when the case instrusion switch gets pressed.
The SMI is controlled along with the general TCO SMI Kconfig.
Tested on X11SSM-F.
Change-Id: I3bc62c79ca3dc9e8896d9e2b9abdc14cfa46a9e7
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Make i/o-standby state and termination configurable for GPIs.
Change-Id: Id1a3c00aa8a857afa08e745b0b6a578b01fa6d47
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This code also sets unused interrupt lines to the recommended safe
value of 0xff instead of ignoring such devices.
Change-Id: I7582b41eb3288c400a949e20402e9820f6b72434
Signed-off-by: Stephen Douthit <stephend@silicom-usa.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This eliminates Linux kernel warnings that look like:
pcieport 0000:00:17.0: can't derive routing for PCI INT B
ixgbe 0000:07:00.1: PCI INT B: no GSI - using ISA IRQ 10
Change-Id: I2029e7a8252b9e48c1df457d8da5adce7d1ac21d
Signed-off-by: Stephen Douthit <stephend@silicom-usa.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
pcie_port.asl defines an IRQM method that looks up legacy interrupt
swizzling based on incoming interrupt "pin" A-D and root port number.
Unfortunately the 8-bit root port number stored at offset 0x4F in the
config space matches the device number, not the 1-8 scheme used in
the LUT reported to the OS.
Fix the case values to match the hardware.
Change-Id: I103d632a4bc99461f02e05aa0f9a9eb7376770d9
Signed-off-by: Stephen Douthit <stephend@silicom-usa.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
SATA Mode Select is bit 16 of the SATA General Configuration
register. This code currently incorrectly pokes at the Port Clock
Disable bits in the Port Mapping Register, and without clock the
affected ports can't link.
Change-Id: I37104f520a869bd45a32cfd271d0b893aec3c8ed
Signed-off-by: Stephen Douthit <stephend@silicom-usa.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
Reviewed-by: David Guckian
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
There was a bug like this for skylake that seems to have been copied to
other SoCs.
Signed-off-by: Matt Delco <delco@chromium.org>
Change-Id: Ib4651eda46a064dfb59797ac8e1cb8c38bb8e38c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
If we don't pretend to have binaries, there is no need to add fake ones.
This also fixes building the default config.
Change-Id: I8f933f24a734a9ce3d82ef57f7f234ee4dfa86e9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39383
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
To use Optane memory, we need to set 2x2 PCIe lane mode while we need
to set 1x4 PCIe lane mode for NVMe. The mode can be selected using
the FIT tool at build time.
By enabling hybrid storage mode in FSP, FSP will set 2x2 PCIe lane mode
if Optane memory is detected and the mode is not 2x2 and set 1x4 PCIe
lane mode if Optane memory is not detected and the mode is not 1x4
during boot up. The mode is saved in SPI NOR for next boot.
BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP from NVMe and Optane
Check PCIe lane configuration.
Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I25bc380697b0774cc30ad1b31ad785ee18822619
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39232
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
In order to add the smbios_slot_desc for the SMBIOS Type9 entries into
the devicetree, and not use numbers but strings like
"SlotTypePciExpressGen3X4", smbios.h needs to be included in the
static.c.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Id15fe4101d14479b02e536fdf63748a241c02bd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
|
|
Coverity detects pointer dev as FORWARD_NULL. Add sanity check
for dev to prevent NULL pointer dereference if dev did not point
to the audio device.
BUG=CID 1420208
TEST=Built image successfully.
Change-Id: I2a62da44c7044f9dc281eae0949f7f7b612ab238
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add registers that are relevant for the case intrusion detection
functionality.
Intel documents: 332691-003EN, 335193-006, 341081-001, ...
Change-Id: If12d21e8e6721abb877cbbfbbba8f0127a86d96b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Enable TCO SMIs in common code, if selected by Kconfig. This is needed
for the follow-up commits regarding INTRUDER interrupt.
Tested on X11SSM-F.
Change-Id: If63effe74ac59b5d051a6454bc6375bb89605215
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Allow the user to select if TCO shall issue SMIs or not.
Change-Id: Id22777e9573376e5a079a375400caa687bc41afb
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39326
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Automatically add microcode binaries from intel-microcode 3rdparty
respository for Braswell processors using Makefile.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iec57e4d5cd63b9bccc869bf178053f1c99b81b9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Add configs to enable CNVi mode and CNViBtCore.
BUG=none
BRANCH=none
TEST=Build and boot tglrvp
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ic372348a1409b2594a85b71b2fc742be96b84b87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39317
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable
Processor, which is a processor in Xeon-SP family. The code
is expected to be reusable for future geneations of Xeon-SP
processors, and will be updated with smaller targeted
patches accordingly, to add support for additional Xeon-SP
processors, to add features, and to improve the code base.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a
proof-of-concept build. The binary is not shared in public,
when this patch is upstreamed.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Tested-by: johnny_lin@wiwynn.com
Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
|
|
The register TCO1_STS is never cleared, which will cause SMIs to either
retrigger over and over again (e.g. TIMEOUT) or prevent concurrent
interrupt events, depending on which event triggered.
Clear both TCO2_STS and TCO1_STS.
This also fixes the issue where SECOND_TO_STS will always end up set in
the SMI handler by unconditionally (re)setting it.
Tested on X11SSM-F, where enabling TCO caused the terminal to get
flooded with SMI debug messages. With this patch, a message gets written
every ~1 second.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ia57c203a672fdd0095355a7e2a0e01aaa6657968
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39259
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Allows to override the PortUsb20Enable and PortUsb30Enable FSP options
(which are set to 1 by default) to enable/disable USB ports if the
usb_config_override flag is set to "1". Therefore, these changes will
not affect other boards with an Apollo Lake processor.
Change-Id: Ia94a2be1647f7743ef0c918ae3b34437a179261c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Coverity detects pointer dev as FORWARD_NULL. Add sanity check
for dev to prevent NULL pointer dereference.
BUG=CID 1353148
TEST=Built and boot up to kernel.
Change-Id: Ic0ad1ec79c950a3c17feccdde4f87f4a107fe8c0
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: Iaa295c74e9c470d5830e22d0b0c73013c7333293
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39266
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The cache as ram code will use one form of a non-eviction mode.
Change-Id: I418eb48434aa3da3bf5ca65315bb8c9077523966
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
The current elog implemetation searches for an active PME status bit by
iterating the PCI devices. On disabled or hidden devices a BUG gets
triggered: BUG: pch_log_rp_wake_source requests hidden ...
This is caused by the use of the PCH_DEV_* macros which resolve to
_PCH_DEV and finally call pcidev_path_on_root_debug.
Disabled devices are skipped already so we can safely use the DEVFNs
instead, circumventing the BUG.
Change-Id: Id126e2c51aec84a4af9354b39754ee74687cefc8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
|
|
update SerialIoUartAutoFlow settings for Tiger Lake platform.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I5ff2c63857a868ca4ed72c6d93bf518e085b8879
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39169
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This commit is adding a dependency check for the FSP_USE_REPO
config option which so far was not able to deal with Denverton
systems.
Change-Id: I615305da5865bef305f560f5c90482cf0937b25a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
|
|
Allows to enable/disable NPK device from the device tree:
device pci 00.2 off end # NPK
Tested on Kontron come-mal10.
Change-Id: I910245d4ff35a6a0a9059fb6911d4426cdb999b6
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38814
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Adds PAD_CFG_NF_BUF_IOSSTATE_IOSTERM macro to configure native function,
iosstate, iosterm and disable input/output buffer. This is used in the
pad configurations for the Kontron COMe-mAL10 module board [1].
[1] https://review.coreboot.org/c/coreboot/+/39133
Change-Id: I7aa4d4dee34bd46a064079c576ed64525fd489e6
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38813
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Configure ethernet based on board config
BUG=none
BRANCH=none
TEST= build TGLRVP and check ethernet is disabled based on devicetree
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I3286f5fefc962a5e55b5554982271ed6b885f7d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39153
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Adapted from implementation in sb/intel/common.
Test: build/boot variants of google/{jecht, auron}
with Tianocore and SMMSTORE enabled
Change-Id: I4d2aaa80dad229a6c7b947d0edf8fb1174050ad0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Adapted from implementation in sb/intel/common.
Test: build/boot variants of google/cyan with Tianocore
and SMMSTORE enabled
Change-Id: Ife4681983d0eecbc01c539b477664f3dd8bb9368
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Adapted from implementation in sb/intel/common.
Test: build/boot variants of google/rambi with Tianocore
and SMMSTORE enabled
Change-Id: Id8adeda982feba1cbcf5e04cf0bef0a6710ad4f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
