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2022-02-02soc/intel/skylake: Use PCR write to disable HECI1Subrata Banik
Set the SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR config for Skylake to disable HECI1 device using PCR writes. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib6bfa7c48660a6df8d0944de675a4f30fe248d1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-02soc/intel/elkhartlake: Use SBI msg to disable HECI1Subrata Banik
Select HECI_DISABLE_USING_SMM config for Elkhart Lake to disable HECI1 device using the SBI msg in SMM. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4ef7ff7aa234ce411092d70bcb2c9141609be90e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-02soc/intel/common/cse: Rework heci_disable functionSubrata Banik
This patch provides the possible options for SoC users to choose the applicable interface to make HECI1 function disable at pre-boot. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI` config is used for disabling heci1 using non-posted sideband write (inside SMM) after FSP-S sets the postboot_sai attribute. Applicable from CNL PCH onwards. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC` config is used for disabling heci1 using PMC IPC command `0xA9`. Applicable from TGL PCH onwards. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR` config is used for disabling heci1 using private configuration register (PCR) write. Applicable for SoC platform prior to CNL PCH. Additionally, add PID_CSME0 macro for SKL, Xeon_SP and APL to fix the compilation failure. Finally, rename heci_disable() function to heci1_disable() to make it more meaningful. BUG=none TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-02soc/intel/common/cse: Make cse_disable_mei_devices a public functionSubrata Banik
This patch export cse_disable_mei_devices() function instead of marking it static. Other IA common code may need to get access to this function for making `heci1` device disable. BUG=none TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib2a1eb2fdc9d4724bd287b82be4238893c967046 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-01soc/intel/xeon_sp/acpi.c: Remove unuseful 'return' in void functionElyes HAOUAS
Change-Id: Ib964939468ebb8cd0a537d514060ee5b8b13e320 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-01drivers/i2c/designware/dw_i2c: return enum cb_err from dw_i2c_initFelix Held
Using enum cb_err as return type instead of int improves the readability of the code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I55e6d93ca141b687871ceaa763bbbbe966c4b4a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-02-01soc/intel/common: Add the Primary to Sideband bridge libraryJohn Zhao
New platforms have additional Primary to Sideband bridge besides the PCH P2SB. This change puts the common functions into the P2SB library. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I63f58584e8c3bfe42cdd81912e1e5140337c2d55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-01soc/intel/appololake: Allow to configure SATA ALPM via devicetreeMario Scheithauer
Add a devicetree option to disable SATA Aggressive Link Power Management. ALPM is a method of saving power. The corresponding FSP-S UPD parameter is enabled by default. It may be that this feature is unwanted, for example for a real-time system. Therefore, allow to disable ALPM using the devicetree. Change-Id: Ica8920a87ebebe83f5d8cb4d6c8c0a6105e183e4 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-02-01soc/intel/alderlake: Add PMC register base for ADL-NUsha P
Add PCR_PSF3_TO_SHDW_PMC_REG_BASE for Alderlake-N.This value is updated from the FSP code. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I7c788e149744bfae2c5260c996b16fc1ce2070c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61148 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-01soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_SCS for Alder Lake NKrishna Prasad Bhat
Alder Lake N has eMMC storage device. Select SOC_INTEL_COMMON_BLOCK_SCS Kconfig for Alder Lake N. Change-Id: I577ffdc80ef09471309c827551a347d4397a33d1 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-01soc/intel/alderlake: Add eMMC PCR Port ID for Alder Lake NKrishna Prasad Bhat
Alder Lake N has eMMC storage device. Add PCR Port ID for it. Reference: Alder Lake N platform EDS Doc# 645548. Change-Id: I6dc494d1748e66b8b4058954f127ec226863e8af Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-01soc/intel/alderlake: Add GPP_I GPIO group for Alder Lake N SOCKrishna Prasad Bhat
Add definitions for GPP_I GPIO group pins on Alder Lake N SOC and GPIO IRQ routing information. GPP_I GPIO group belongs to GPIO community 1. Hence GPIO community 1 in Alder Lake N contains GPP_S, GPP_I, GPP_H, GPP_D GPIO groups. GPIO groups 1-6 in Doc# 645550 Chapter 36 corresponds to GPIO communities 5-0 respectively. BUG=b:213535859 Change-Id: Ia71a399c03cb7d098a381bd9439d448e8a620761 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61106 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-31soc/intel/adl: Update devicetree based on remapping for TBT PCIeMAULIK V VAGHELA
ADL has 4 TBT root ports which are PCIe compliant. TBT uses PCIe coalescing logic where in case root port 0 is disabled, other enabled root port is remapped to port 0. coreboot handles this remapping scenarios for PCH and CPU PCIe root ports and not for TBT root ports. This patch uses the same function used for PCIe remapping to update devicetree based on coalescing and SoC needs to pass correct function number and number of slots. BUG=b:210933428 BRANCH=None TEST=Check if TBT remapping happens correctly and ACPI tables are generated correctly. Change-Id: Ied16191d6af41f8e2b31baee80cb475e7d557010 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-31intel/common/block/pcie: Add NULL/count check in pcie_rp_update_devtreeMAULIK V VAGHELA
pcie_rp_update_devicetree function takes pcie_rp_group strcuture as an argument and SoC code passes the parameter in this structure. This pointer can be NULL and common code may try to dereference this NULL pointer. Also, group might have no data and SoC may pass this by indicating group count as zero (For example, for CPU or TBT root ports). These checks will prevent function from executing redundant code and returning early from the call as it's not required. BUG=b:210933428 BRANCH=None TEST=check if function returns early for group count 0 and there is no issue while booting board in case group count = 0. Change-Id: I132319bb05fdef1590c18302fc64cc76e15bea6d Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-31soc/intel/alderlake: Add Alder Lake P IGD device IDsKane Chen
This patch adds additional IGD device IDs as per document 638514. BUG=b:216420554 TEST=coreboot is able to probe the IGD device during PCI enumeration. Change-Id: I0cafe92581c454da5e4aeafd7ad52f0e65370b11 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61441 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-30soc/intel/elkhartlake: Drop stale eNEM TODO commentSubrata Banik
This patch drops stale TODO comment about enabling eNEM on EHL. eNEM is non-POR on the elkhartlake product. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I47fd755dec2324e05e6349e51e15abcf26967604 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-28soc/intel/xeon_sp/nb_acpi.c: Drop comparison to trueElyes HAOUAS
Change-Id: Ib9670ee22e36dd988a75b2f8dc565534927b6107 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-01-28soc/intel/common/gpio: Skip GPIO PAD locking in recovery modeSubrata Banik
The recovery mode is meant to provide fixes for the platform deformity hence, skip locking the GPIO PAD configuration to provide the same flexibility to the platform owner while booting in recovery mode. BUG=b:211950520 TEST=Able to build and boot the brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0f0a3cfb2be7f2a5485679f6a3d8cb4fb407fcf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-28soc/intel: Abstract the common block API for TCSS registers accessJohn Zhao
The existing TCSS registers access is through the REGBAR. There will be future platforms which access the TCSS registers through the Sideband interface. This change abstracts the common block API for TCSS access. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I3e2696b117af24412d73b257f470efc40caa5022 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-28src/{drivers,soc}: Fix some code indentsElyes HAOUAS
Change-Id: I55682de4a1bc74f170e2044de35b0d8d53ef51ff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-28soc/intel/common/cse: skip heci_init() if HECI1 is disabledMatt DeVillier
If the HECI1 PCI device is disabled, either via devicetree or other method (HAP, me_cleaner), then we don't want/need to program a BAR, set the PCI config, or call heci_reset(), as the latter will result in a 15s timeout delay when booting. Test: build/boot Purism Librem 13v2, verify heci_reset() timeout delay is no longer present. Change-Id: I0babe417173d10e37327538dc9e7aae980225367 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-28soc/intel/alderlake: Enable CPPCv3Sridahr Siricilla
The patch defines the following helper functions: get_cpu_scaling_factor(): Returns scaling factors of big and small core. cpu_is_nominal_freq_supported(): Returns true if CPU supports Nominal Frequency, otherwise false. cpu_is_nominal_freq_supported(): Check CPU supports nominal frequency or not. The patch also enables CPPCv3 support for Intel Alder Lake which is based on hybrid core architecture. TEST=Verified Nominal Frequency and Nominal Performance are getting updated for ADL-P small and big cores correctly. Signed-off-by: Sridahr Siricilla <sridhar.siricilla@intel.com> Change-Id: I963690a4fadad322095d202bcc08c92dcd845360 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-28soc/intel/common: Implement ACPI CPPCv3 package to support hybrid coreSridhar Siricilla
The patch implements ACPI CPPCv3 package. It implements and updates the following methods: generate_cppc_entries(): Updates method to support CPPCv3 package acpi_get_cpu_nominal_freq(): Calculates CPU's nominal frequency acpi_get_cpu_nomi_perf(): Calculates nominal performance for big and small cores. acpigen_write_CPPC_hybrid_method(): It generates ACPI code to implement _CPC method. acpigen_cppc_update_nominal_freq_perf(): It updates CPPC3 package if cpu supports Nominal Frequency. It generates ACPI code which sets Nominal Frequency and updates Nominal Performance. It uses below calculation to update the Nominal Frequency and Nominal Performance: Nominal Frequency = Max non-turbo ratio * cpu_bus_frequency Nominal Performance = Max non-turn ratio * cpu scaling factor CPU scaling factor varies in the hybrid core environment. So, the generated ACPI code updates Nominal Performance based on the CPU's scaling factor. TEST=Verified CPPCv3 package is getting created in the SSDT table. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Signed-off-by: ravindr1 <ravindra@intel.com> Change-Id: Icd5ea9e70bebd1e66d3cea2bcf8a6678e5cc95ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/59359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-01-27soc/intel/common/cse: Drop CSE library usage in bootblockSubrata Banik
This patch drops the CSE common code block from getting compiled in bootblock without any SoC code using heci communication so early in the boot flow. BUG=none TEST=Able to build brya, purism/librem_skl without any compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib4d221c6f19b60aeaf64696e64d0c4209dbf14e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-01-27soc/intel/skylake: move heci_init() from bootblock to romstageMatt DeVillier
Aligns with all other soc/intel/common platforms calling heci_init(). Test: build/boot Purism Librem 13v2 Change-Id: I43029426c5683077c111b3382cf4c8773b3e5b20 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61378 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-26soc/intel/cannonlake: Add PcieRpHotPlug config to FSP-MMatt DeVillier
Commit b67c5ed [3rdparty/fsp: Update submodule pointer to newest master] updated the FSP binaries/headers for Comet Lake, which included a change moving PcieRpHotPlug from FSP-S to FSP-M. Unfortunately the existing UDP in FSP-S was left in and deprecated, which allowed the change to go unnoticed until it was discovered that hotplug wasn't working. Since other related platforms (WHL, CFL) share the SoC code but use different FSP packages, add the setting of the PcieRpHotPlug UPD to romstage/FSP-M and guard it with '#if CONFIG(SOC_INTEL_COMETLAKE)'. Test: build/boot Purism Librem 14, verify WiFi killswitch operates as expected / WiFi is re-enabled when turning switch to on position. Change-Id: I4e1c2ea909933ab21921e63ddeb31cefe1ceef13 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-26soc/intel/denverton_ns: Fix logging levelKyösti Mälkki
Level should match that used in print_num_status_bits(). Change-Id: I1beb65e4c141e195dd59eaa2bf55fff6e7dc910d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jeff Daly <jeffd@silicom-usa.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-26soc/intel/alderlake: Add GPIO Controller device ID for ADL-NUsha P
Add PCH ACPI Device ID for Alder Lake N SOC GPIO Controller. Document: Alder Lake N Platform EDS Volume 1 (Doc# 645548) Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I6eb15751dd303b4b445cb64f25a040302e50c09d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-01-26soc/intel/alderlake: Choose non-posted write to lock GPIO PADSubrata Banik
Set the SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI config on Alder Lake to instruct Pad Configuration Lock to use non-posted sideband writes as posted write is not supported on Alder Lake while locking GPIO pads. BUG=b:211573253, b:211950520 TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id8d394b97de9c328b3f75df3649d7efc782f006b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-26soc/intel/alderlake: Skip FSP to unlock GPIO PadsSubrata Banik
This patch makes FSP-S skip unlocking the GPIO Pads. BUG=b:211573253, b:211950520 TEST=FSP-S debug log below: Without this change: UnlockGpioPads= 1 With this changes UnlockGpioPads= 0 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I236a19a67372e9668e304d0054d477daff6a0266 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-26soc/intel/common/gpio: Rework PAD config macro to add lock supportSubrata Banik
This patch extends `struct pad_config` to add new variable for gpio lock action. Additionally, it creates new GPIO PAD configuration macros that perform GPIO pad configuration and pad lock configuration as well. List of new macros are: 1. PAD_CFG_NF_LOCK 2. PAD_CFG_GPO_LOCK 3. PAD_CFG_GPI_LOCK 4. PAD_CFG_GPI_TRIG_OWN_LOCK 5. PAD_CFG_GPI_GPIO_DRIVER_LOCK 6. PAD_CFG_GPI_INT_LOCK 7. PAD_CFG_GPI_APIC_LOCK 8. PAD_CFG_GPI_IRQ_WAKE_LOCK Mainboard users can use the above macros to lock the PAD after configuration. So far on IA chipset, the default GPIO pad lock configuration reset type is POWERGOOD hence, it's recommended as per GPIO BWG (doc: 630603) to configure the GPP PAD reset type the same as lock configuration reset type to avoid GPP reset value misconfiguration issue. BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibf8b0a845005ad545266d995449d0aa711f45a61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-26soc/intel/common/gpio: Perform GPIO PAD lock outside SMMSubrata Banik
This patch performs GPIO PAD lock configuration in non-smm mode. Typically, coreboot enables SMI at latest boot phase post FSP-S, hence, FSP-S might get chance to perform GPP lock configuration. With this code changes, coreboot is able to perform GPIO PAD lock configuration early in the boot flow, prior to calling FSP-S. Also, this patch ensures to have two possible options as per GPIO BWG to lock the GPIO PAD configuration. 1. Using SBI message with opcode 0x13 2. Using Private Configuration Register (PCR) BUG=b:211573253, b:211950520 TEST=Able to build and boot brya variant with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I71b4e2f24303b6acb56debd581bd6bc818b6f926 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60801 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-25soc/intel/ehl: Add Kconfig option to disable reset on TCO expirationWerner Zeh
The TCO timer is the default watchdog of an x86 host and can reset the system once it has expired for the second time. There are applications where this reset is not acceptable while the TCO is used. In these applications the TCO expire event generates an interrupt and software takes care. There is a bit in the TCO1_CNT register on Elkhart Lake to prevent this reset on expiration (called NO_REBOOT, see doc #636722 ). This bit can either be strapped on hardware or set in this register to avoid the reset on expiration. While the hardware strap cannot be overridden in software, the pure software solution is more flexible. Unfortunately, the location for this bit differs among the different platforms. This is why it has to be handled on soc level rather than on TCO common code level. This commit adds a Kconfig option where NO_REBOOT can be enabled. This makes it easy to reach this feature over to the mainboard where it can be selected if needed. Change-Id: Iaa81bfbe688edd717aa02db86f0a93fecdfcd16b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-25soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
Since Tiger Lake platform, the HECI1 device can be disabled on Alder Lake platform using two different mechanism: A. Using PMC IPC command 0xA9. B. Sending SBI message under SMM. In current scope of Alder Lake the default implementation is using (B) sending sbi message under SMM. A follow up patch to add the possible options and let platform to choose the applicable one. List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Default enable HECI1 device in `chipset.cb` to ensure the HECI1 device can undergo the PCI enumeration and later based on the mainboard policy the HECI1 device can be disabled. Mainboards that choose to make HECI1 enable during boot don't override `DISABLE_HECI1_AT_PRE_BOOT` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie673e634fbc0bdece419c379d417b08dfb4819e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-25soc/intel/common: Include Alder Lake-N device IDsUsha P
Add Alder Lake-N System Agent, PCIE, UFS, IPU and CNVI device IDs. Document: Alder Lake N Platform EDS Volume 1 (Doc# 645548) Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I0a383816f818b794cf1211766c27937b3b8daa31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-01-25soc/intel/elkhartlake: Add PSE TSN supportLean Sheng Tan
Enable PSE GBE with following changes: 1. Configure PCH GBE related FSP UPD flags 2. Add PSE GBE ACPI devices 3. Refactor PCH GBE FSP-S code and merge it together with PSE GBE code Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: If3807ff5a4578be7b2c67064525fa5099950986a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-01-25soc/intel/elkhartlake: Introduce Intel PSELean Sheng Tan
The Intel® Programmable Services Engine (Intel® PSE) is a dedicated offload engine for IoT functions powered by an ARM Cortex-M7 microcontroller. It provides independent, low-DMIPS computing and low-speed I/Os for IoT applications, plus dedicated services for real-time computing and time-sensitive synchronization. The PSE hosts new functions, including remote out-of-band device management, network proxy, embedded controller lite and sensor hub. This CL enables the user to provide the base address of the PSE FW blob which will then be loaded by the FSP-S onto the ARM controller. PSE FW will do the initialization work of PSE controller and its peripherals. The loading of PSE FW should have negligible impact on boot time unless PSE controller could not locate the PSE FW and FSP will attempt to redo PSE FW loading and wait for PSE handshake until it times out. Once PSE controller locate the PSE FW, it will do initialization concurrently by itself with coreboot booting. It also adds PSE related FSP-S UPD settings which enable the setup of peripheral ownership (assigned to the PSE or x86 subsystem) and interrupts. These assignments need to take place at a given point in the boot process and cannot be changed later. To verify if PSE FW is loaded properly, the user could enable PchPseShellEnabled flag and the log will be printed at PSE UART 2. For further info please refer to doc #611825 (for HW overview) and #614110 (for PSE EDS). Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-01-24soc/intel/common/block/pcie/rtd3: Fix PMC IPC method for CPU PCIe RPTim Wawrzynczak
When calling get_pcie_rp_pmc_idx(), the following code checked the return value to see if it was negative or `> CONFIG_MAX_ROOT_PORTS`. However, the expected return value for CPU PCIe RPs is above MAX_ROOT_PORTS. Since the static, local function is intended to return -1 or a valid value, drop the check for `> CONFIG_MAX_ROOT_PORTS`. Change-Id: I2039273ad246884cd8736a7f0355e621a706a526 Fixes: b6a15a7 ("soc/intel/common/block/pcie/rtd3: Update ACPI Update ACPI methods for CPU PCIe RPs") Tested-by: Tim Crawford <tcrawford@system76.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2022-01-22soc/intel/alderlake: Implement get_soc_cpu_type helper functionSridhar Siricilla
The patch implements get_soc_cpu_type() helper function which determines whether the executing CPU is a small or a big core. This is the SoC-specific callback that must be implemented for SoCs that select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID. It will be called from set_cpu_type(). TEST=verified on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Icd0d7e8a42c4b20d3e1d34998bca6321509df2d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-21soc/intel/common/cse: Add support to get CSME timestampsBora Guvendik
This command retrieves a set of boot performance timestamps CSME collected during the platform's last boot flow. BUG=b:182575295 TEST=Verify CSME timestamps after S3 and boot. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ic6f7962c49b38d458680d51ee1cd709805f73b66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-21soc/intel/common/gpio: Add PCH `Pad Configuration Lock` optionsSubrata Banik
This patch provides the possible options for PCH to allow `Pad Configuration Lock`. `SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI` config is for Tiger Lake Point (TGP) and Alder Lake Point (ADP) PCH. BUG=b:211573253, b:211950520 TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7cf35893ab613b154a1073060081a09e561ffe56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-21soc/intel/common/gpio: Use const variable to get gpio bitmaskSubrata Banik
This patch introduces a `const bit_mask` variable to hold the gpio PAD mask value prior to sending the lock configuration command using the sideband interface. Additionally, this patch fixes the PAD lock overridden issue as below: Without this code change every consecutive PAD lock operation resets other bits in that register as below: After Locking pad 2 , pcr_read=0x4 After Locking pad 3 , pcr_read=0x8 After Locking pad 4 , pcr_read=0x10 After Locking pad 5 , pcr_read=0x20 After Locking pad 6 , pcr_read=0x40 After Locking pad 7 , pcr_read=0x80 After Locking pad 8 , pcr_read=0x100 With this code change all previous lock bits are getting preserved as below: After Locking pad 2 , pcr_read=0x4 After Locking pad 3 , pcr_read=0xc After Locking pad 4 , pcr_read=0x1c After Locking pad 5 , pcr_read=0x3c After Locking pad 6 , pcr_read=0x7c After Locking pad 7 , pcr_read=0xfc After Locking pad 8 , pcr_read=0x1fc BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I342a666aa2d34bcc8ba33460396d1248f0c0f89f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60999 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-21soc/intel/alderlake: Add ADL-P 2+8+2 (28W) VR configCurtis Chen
ADL-P 2+8+2 (28W) would have a match PD to ADL-P 4+8+2 (28W). Group them into the same group core "ADL_P_282_482_28W_CORE". BUG=b:211365920 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: I3f92c0f5d717dd33ac478fbaa883f3e972e7a7de Reviewed-on: https://review.coreboot.org/c/coreboot/+/61196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-21soc/intel/ehl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
The only option to make HECI1 function disable on Elkhart Lake SoC platform is using SBI under SMM mode. List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I76c625e6221fdef1343599e7dbc7739caa91bf98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
2022-01-21soc/intel/icl: Rework on HECI1 disable configsSubrata Banik
The only option to make HECI1 function disable on Ice Lake SoC platform is using SBI under SMM mode. Hence, this patch makes DISABLE_HECI1_AT_PRE_BOOT=y default and selects `HECI_DISABLE_USING_SMM` config for Ice Lake. Also, drop `HeciEnabled` from chip configuration and guard heci_disable() using DISABLE_HECI1_AT_PRE_BOOT config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If4155e5c7eeb019f7dce59acd5b82720baddcb43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-19soc/intel/alderlake: Add method to determine the cpu typeSridahr Siricilla
set_cpu_type(): It determines the CPU type (big or small) that is executing the function, and marks the global_cpu_type's array slot which is corresponds to the executing CPU's index if the CPU type is big core. get_cpu_index(): It determines the index from LAPIC Ids. This is required to expose CPPC3 package in ascending order of CPUs' LAPIC ids. So, the function returns CPU's position from the ascending order list of LAPIC ids. TEST=Tested CPU index calculation, core type determination on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: If4ceb24d9bb1e808750bf618c29b2b9ea6d4191b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-19soc/intel/common/cpu: Use SoC overrides to get CPU privilege levelSubrata Banik
This patch implements a SoC overrides to check CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR 0x151. BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I515f0a3548bc5d6250e30f963d46f28f3c1b90b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-19soc/intel/alderlake: Rework the GPIO PAD Pin numbersSubrata Banik
This patch creates a `relative increment by 1` macro to let SoC gpio pad configuration to be more flexible while adding support for newer PCH SoC. With this changes adding GPIO controller support for PCH-N would become really simple without too much of code duplication. For example: ADL-N has added `GPP_I` pins into community 1 hence, the additional code for `PCH-N` whould appear incremetal to ADL-P. > #define GPP_B 0x0 > #define GPP_T INC(GPP_B) > #define GPP_A INC(GPP_T) > #define GPP_R INC(GPP_A) > #define GPD INC(GPP_R) > #define GPP_S INC(GPD) > if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) > #define GPP_I INC(GPP_S) > #define GPP_H INC(GPP_I) > #else > #define GPP_H INC(GPP_S) > #endif > #define GPP_D INC(GPP_H) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie3b2183381b877da0a6e5a27f5176f0e21e0c9fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-01-18soc/intel/alderlake: Add eMMC device into chipset.cbKrishna Prasad Bhat
Add eMMC device into chipset.cb and keep it `off` by default. eMMC device is applicable only for Alder Lake N SOC. Change-Id: I2bc38ee5814688409feb7e4531c1daa5b54953c0 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-01-18soc/intel/common: Add Alder Lake N eMMC device IDKrishna Prasad Bhat
Add eMMC device ID for Alder Lake N SOC. Reference: Alder Lake N Platform EDS Volume 1 (Doc# 645548) Change-Id: Id35ec2d508bec8ff7d6f1c5fbfaf209d42b25c72 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-01-18soc/intel/{adl,common}: Support alderlake host device id 0x4619Kane Chen
Host device id 0x4619 is missed in few coreboot tables so that coreboot can't recognize and config it properly. Document Number: 690222 BUG:b:214665785, b:214680767 Change-Id: I95908bdc0a736bafedb328dda2a00b5473de3d88 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-17pci_ids.h: Make Denverton IDs consistent with other Intel SoCsJeff Daly
Align Denverton PCI ID define names with other Intel SoCs. Also, update the names in SoC code accordingly. Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Id4b4d971ef8f4b3ec5920209d345edbbcfae4dec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-17soc/intel/cnl: Use Kconfig to disable HECI1Subrata Banik
This patch makes DISABLE_HECI1_AT_PRE_BOOT=y default for Cannon Lake and ensures disable_heci1() is guarded against this config. Also, makes dt CSE PCI device `on` by default. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Idd57d2713fe83de5fb93e399734414ca99977d0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/60725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-17src: Remove unused <cbfs.h>Elyes HAOUAS
Found using: diff <(git grep -l '<cbfs.h>' -- src/) <(git grep -l 'cbfs_allocator_t\|cbfs_load\|cbfs_ro_load\|cbfs_type_load\|cbfs_ro_type_load\|cbfs_unverified_area_load\|cbfs_map\|cbfs_ro_map\|cbfs_type_map\|cbfs_ro_type_map\|cbfs_unverified_area_map\|cbfs_alloc\|cbfs_ro_alloc\|cbfs_type_alloc\|cbfs_ro_type_alloc\|cbfs_unverified_area_alloc\|cbfs_cbmem_alloc\|cbfs_ro_cbmem_alloc\|cbfs_type_cbmem_alloc\|cbfs_ro_type_cbmem_alloc\|cbfs_unverified_area_cbmem_alloc\|cbfs_preload\|cbfs_unmap\|cbfs_prog_stage_load\|cbfs_get_size\|cbfs_ro_get_size\|cbfs_get_type\|cbfs_ro_get_type\|cbfs_type\|cbfs_file_exists\|cbfs_ro_file_exists\|mem_pool\|cbfs_cache\|cbfs_boot_device\|cbfs_boot_device_find_mcache\|cbfs_boot_device\|cbfs_get_boot_device\|cbfs_init_boot_device\|cbfs_boot_lookup\|cbfs_alloc\|cbfs_unverified_area_alloc\|cbfs_default_allocator_arg\|cbfs_default_allocator\|cbfs_cbmem_allocator\|cbfs_alloc\|cbfs_ro_alloc\|cbfs_type_alloc\|cbfs_ro_type_alloc\|cbfs_unverified_area_alloc\|cbfs_map\|cbfs_ro_map\|cbfs_type_map\|cbfs_ro_type_map\|cbfs_unverified_area_map\|cbfs_load\|cbfs_type_load\|cbfs_ro_load\|cbfs_ro_type_load\|cbfs_unverified_area_load\|cbfs_cbmem_alloc\|cbfs_ro_cbmem_alloc\|cbfs_type_cbmem_alloc\|cbfs_ro_type_cbmem_alloc\|cbfs_unverified_area_cbmem_alloc\|cbfs_get_size\|cbfs_ro_get_size\|cbfs_get_type\|cbfs_ro_get_type\|cbfs_file_exists\|cbfs_ro_file_exists\|cbfs_mdata\|cbfs_find_attr\|cbfs_file_hash' -- src/)|grep "<" Change-Id: Ib4dca6da1eb66bbba5b6e94fd623f4fcfc2f0741 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-16soc/intel/common/cse: Add helper API for CSE SPI Protection ModeSubrata Banik
This patch checks if CSE's spi protection mode is protected or unprotected. Returns true if CSE's spi protection mode is protected, otherwise false. BUG=b:211954778 TEST=Able to build and boot brya with this change. Calling `cse_is_hfs1_spi_protected()` in coreboot is able to provide the SPI protection status. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I23f1a1c4b55d8da6e6fd0cf84bef86f49ce80cca Reviewed-on: https://review.coreboot.org/c/coreboot/+/60403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-16soc/intel/skl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Make dt CSE PCI device `on` by default. 4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1 function disable at pre-boot instead of the dt policy that uses `HeciEnabled = 0`. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-16soc/intel/common: Abstract the sideband accessJohn Zhao
The existing Sideband access is with the PCH P2SB. There will be future platforms which access the TCSS registers through SBI other than the PCH P2SB. This change abstracts the SBI with common API. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ia6201762fe92801ce6b4ed97d0eac23ac71ccd37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-16soc/intel/denverton_ns: Add the Primary to Sideband Bridge definitionJohn Zhao
This change adds the Primary to Sideband Bridge(B0, D31, F1) definition for the platform in order to maintain the common block API build. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I1c4ddfce6cc6e41b2c63f99990d105b4bbb6f175 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-14soc/intel/jsl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-14soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a81fd58df468e2711108a3243bf116e02986316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-14soc/intel/tigerlake: add devicetree option PcieRpSlotImplementedMichael Niewöhner
Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI bit set for any slots of already existing boards, add set the option PcieRpSlotImplemented=1 where appropriate. Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-14soc/intel/tgl: deduplicate the PCIe root port mapMichael Niewöhner
Make use of the helper introduced in the parent change to deduplicate the PCIe root port table. Change-Id: I2dae4e4caf0a7ba3662889f3b31da0c3c299bc92 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-14soc/intel/tgl/pcie_rp: add TGL-H supportMichael Niewöhner
Add TGL-H support for the recently introduced code for differentiating CPU and PCH root ports by adding the missing TGL-H port map. Change-Id: Id2911cddeb97d6c164662e2bef4fdeece10332a8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-13vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04Nick Vaccaro
The headers added are generated as per FSP v2511_04 Previous FSP version was v2471_02 Changes include: - UPDs description update in FspsUpd.h and FspmUpd.h - Adjust UPD Offset in FspmUpd.h - Name change of UPDs in FspmUpd.h and FspsUpd.h - Copyright year is updated in FspmUpd.h and FspsUpd.h - Updated spd_upds and dq_upds structure variables in meminit.c - Updated structure member of s_cfg->LpmStateEnableMask to PmcLpmS0ixSubStateEnableMask in fsp_params.c BUG=b:213959910 BRANCH=None TEST=Build and boot brya Cq-Depend: chrome-internal:4448696, chrome-internal:4445910 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com> Change-Id: I39646c6812afbf622171361b8206daeacdaafac0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-12soc/intel/common/gpio: Fix cosmetic issue with `gpio_lock_pads`Subrata Banik
This patch replaces hardcoded `4` (next offset Tx state) with `sizeof(uint32_t)` for calculating 'Tx state offset'. Also, add checks to detect the specific GPIO lock action between `LOCK_CONFIG` or 'LOCK_TX'. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iff712b16808e0bc99c575bb2426a4f84b89fdb73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-12soc/intel/tigerlake: Implement function to map physical port to EC portjzhao80
Currently coreboot and EC had different logic to interpret TCSS port number which would break retimer update functionality since coreboot would pass wrong port information to EC. This change clones the implementation on Alder Lake which converts the phyiscal port mapping to EC's abstract port mapping. BUG=b:207057940 BRANCH=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: If4451598dbb83528ae6d88dbc1b65c206f24fe1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-12soc/intel/tgl/pcie_rp: correct root port mapMichael Niewöhner
TGL-LP only has 12 root ports, not 20. Correct the port map. Change-Id: I3f5c69a2e7e3a2b8292c81beeac4ea6c7279d4b4 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-01-11soc/intel/apl: Use Kconfig to disable HECI1Subrata Banik
This patch makes DISABLE_HECI1_AT_PRE_BOOT=y default for Apollo Lake and ensures disable_heci1() is guarded against this config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7ac0cad97fcd42b2c6386693319d863352356864 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-11soc/intel/alderlake: Factor out A0 stepping workaroundAngel Pons
Move the `configure_pmc_descriptor()` function to SoC scope instead of having two identical copies in mainboard scope. Add a Kconfig option to allow mainboards to decide whether to implement this workaround. Change-Id: Ib99073d8da91a93fae9c0cebdfd73e39456cdaa8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-11soc/intel/apl: Rework on CPU privilege level implementationSubrata Banik
This patch migrates common code API into SoC specific implementation to drop CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK, it's MSR 0x120 and CNL onwards it's MSR 0x151. Also, include `soc/msr.h` in cpu.h to fix the compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0b6f39509cc5457089cc15f28956833c36b567ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/60898 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-10src/soc: Remove unused <stdlib.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <stdlib.h>' -- src/) <(git grep -l 'memalign(\|malloc(\|calloc(\|free(' -- src/) Change-Id: I08e1a680de9bfcc7d74e88a15abe9eef327b4961 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-01-10src/soc/intel: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: I2ca3a7487cbe75f9bec458f4166378a07b833bb5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-10soc/intel/common/cse: Add config to disable HECI1 at pre-bootSubrata Banik
This patch adds a config to let mainboard users choose the correct state of HECI1(CSE) device prior to handing off to payload. `DISABLE_HECI1_AT_PRE_BOOT` config to make HECI1 function disable at pre-boot. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7e127816c506df3ac0cf973b69021d02d05bef4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/60721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-10soc/intel/common: Add missing space before }Paul Menzel
Fixes: 5b94cd9e9d ("soc/intel/common: Include Alder Lake-N device IDs") Change-Id: I24c2bdb9e4a9eb873b52668a41f4c0e944ed7818 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-10soc/intel/alderlake: Update the ADL-P SKU parameters for VR domainsCurtis Chen
We support all the ADL-P 15W/28W/45W SKU's and map them with the latest VR configurations. These config values are generated by iPDG application with ADL-P platform package tool. RDC Kit ID for the iPDG tools * Intel(R) Platform Design Studio Installer: 610905 * Intel(R) Platform Design Studio - Libraries: 613643 * Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345 * Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261 BUG=b:211365920 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: Ida7a6df0422a9a3972646cb3bdd0112b5efa2755 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-09soc/intel/{icl,tgl,jsl,ehl}: enable ACPI CPPC entriesMichael Niewöhner
Enable CPPC entries generation, needed for Intel SpeedShift. This can be tested by checking sysfs in Linux: $ grep . /sys/devices/system/cpu/cpu?/acpi_cppc/*perf The output should look like this, while the values may differ: /sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf:28 /sys/devices/system/cpu/cpu0/acpi_cppc/lowest_nonlinear_perf:5 /sys/devices/system/cpu/cpu0/acpi_cppc/lowest_perf:1 /sys/devices/system/cpu/cpu0/acpi_cppc/nominal_perf:24 /sys/devices/system/cpu/cpu1/acpi_cppc/highest_perf:28 /sys/devices/system/cpu/cpu1/acpi_cppc/lowest_nonlinear_perf:5 ... Change-Id: I910b4e17d4044f1bf1ecfa0643ac62fc7a8cb51b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
2022-01-08soc/intel/xeon_sp: Don't handle FSP reserved memory explicitlyArthur Heymans
FSP reserved memory is allocated inside cbmem which already gets marked as a reserved memory region, so there is no need to do this explicitly. Change-Id: I39ec70bd9404d7bc2a4228c4364e4cc86f95d7c1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-01-07soc/intel/common/block/pcie/rtd3: Update ACPI methods for CPU PCIe RPsTim Wawrzynczak
The PMC IPC method that is used for RTD3 support expects to be provided the virtual wire index instead of the LCAP PN for CPU PCIe RPs. Therefore, use the prior patches to update pcie_rp for CPU RPs. Note that an unused argument to pcie_rtd3_acpi_method_status() was also dropped. BUG=b:197983574 TEST=add rtd3 node under pcie4_0 in overridetree for brya0, boot and inspect the SSDT to see the PMC IPC parameters are as expected for the CPU RP, and the ModPhy power gating code is not found in the AML for the PEG port. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: Tim Crawford <tcrawford@system76.com> Change-Id: I84a1affb32cb53e686dbe825d3c3a424715df873 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60183 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-07soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDsTim Wawrzynczak
The Alder Lake chip.h file has pcie_rp_config entries for the CPU PCIe ports, but the UPDs are not set. This patch hooks up those config structs to the appropriate FSP-S UPDs. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ibb2375e66d53b4b7567dbe88b941cd720fdad927 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-07soc/intel/common/blk/memory: Make mixed topo workAngel Pons
When using a mixed memory topology with DDR4, it's not possible to boot when no DIMMs are installed, even though memory-down is available. This happens because the DIMM SPD length defaults to 256 when no DIMM SPD is available. Relax the length check when no DIMMs are present to overcome this problem. Tested on system76/lemp10. Unit boots with and without DIMM installed. Change-Id: I1cabf64fade1c06a44b6c3892659d54febc7a79a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Tested-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2022-01-07soc/intel/alderlake: Check clkreq overlapKane Chen
In some cases, partner may assign same clkreq on more than one devices. This could happen when one device is in baseboard dev tree and another one is in override dev tree. This change adds a clkreq overlap check and shows a warning message TEST=On brya, assigned one clkreq to 2 devices and found the warning message Change-Id: I2f701a19118f4702c227b17e43b6551591d9b344 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-06soc/intel/alderlake: Add minimal ACPI support for PEG portsTim Wawrzynczak
Add minimal Device entries with just an _ADR for each of the PEG ports for P and M chipsets (N does not have any PEG ports). Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Id1009004969729eddf7005fa190f5e1ca2d7b468 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-06soc/intel/alderlake: Add soc_get_cpu_rp_vw_idx() functionTim Wawrzynczak
The PMC IPC method used to enable/disable PCIe srcclks uses the LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC command expects the RP number to be its "virtual wire index" instead. This new function returns this virtual wire index for each of the CPU PCIe RPs. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I5e9710f0d210396f9306b948d9dce8b847300147 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-06soc/intel/tigerlake: Add soc_get_cpu_rp_vw_idx() functionTim Wawrzynczak
The PMC IPC method used to enable/disable PCIe clk sources uses the LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC command expects the RP number to be its "virtual wire index" instead. This new function returns this virtual wire index for each of the CPU PCIe RPs. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7aa14a634dcd90c4817009db970fb209ae02c63d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-06soc/intel/common/gpio: Skip GPP pad lock config if config is not setSubrata Banik
Don't perform GPP lock configuration if SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS config is not selected. This patch fixes a compilation issue when APL/GLK boards are failing while gpio_lock_pads() function is getting called from IA common gpio block. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I392dc2007dba8169e480f82b58b7f0a1578bb09f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-06soc/intel/common/gpio: Modify pad_config.pad type from `int` to 'gpio_t'Subrata Banik
This patch modifies struct pad_config.pad type from `int` to 'gpio_t' as pad offset inside GPIO community is unsigned type and also to maintain parity with `struct gpio_lock_config.pad` type. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I15da8a1aff2d81805ba6584f5cc7e569faf456e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-06soc/intel/common/gpio: Rename struct gpio_lock_config.gpio to .padSubrata Banik
This patch renames struct gpio_lock_config variable `gpio` to `pad`, to represent the pad offset within the GPIO community. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6bed99c401435c96c9543f99406a934d7141c575 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-06soc/intel/alderlake: Fix GPIO reset mapping as per GPIO BWGSubrata Banik
This patch fixes the documentation discrepancy of GPIO reset type between PCH EDS and GPIO BWG. As per GPIO BWG, there are four GPIO reset types in Alder Lake as below: - Power Good - (Value 00) - Deep - (Value 01) - Host Reset/PLTRST - (Value 10) - RSMRST for GPD/Reserved for GPP - (Value 11) Hence, created two different reset types for `GPP` and `GPD`. Also, replaced PAD_CFG0_LOGICAL_RESET_x macros with PAD_RESET(). BUG=b:213293047 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4b8742c7a0cc1dc420e3e22e34a16355294ed61b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-05src/soc/intel: Remove unused <delay.h>Elyes HAOUAS
Change-Id: Id8e6221a9801d5198171dc9cd564000d19720a42 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-05soc/intel: Remove unused <string.h>Elyes HAOUAS
Found using following command: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy(\|memmove(\|memset(\|memcmp(\|memchr(\|strdup(\|strconcat(\|strnlen(\|strlen(\|strchr(\|strncpy(\|strcpy(\|strcmp(\|strncmp(\|strspn(\|strcspn(\|strstr(\|strtok_r(\|strtok(\|atol(\|strrchr(\|skip_atoi(\|vsnprintf(\|snprintf(' -- src/) Change-Id: Iae90ff482f534d8de2a519619c20a019d054e700 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-04soc/intel/common/acpi/pep: Use correct size_t length modifierPaul Menzel
Building an image for the Purism Mini v2 with `x86_64-linux-gnu-gcc-11` fails with the format warning below as the size of size_t differs between 32-bit and 64-bit. CC ramstage/soc/intel/common/block/acpi/pep.o src/soc/intel/common/block/acpi/pep.c: In function 'read_pmc_lpm_requirements': src/soc/intel/common/block/acpi/pep.c:57:50: error: format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'size_t' {aka 'unsigned int'} [-Werror=format=] 57 | printk(BIOS_ERR, "Failed to retrieve LPM substate registers" | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 58 | "from LPM, substate %lu, reg %lu\n", i, j); | ~ | | | size_t {aka unsigned int} src/soc/intel/common/block/acpi/pep.c:58:62: note: format string is defined here 58 | "from LPM, substate %lu, reg %lu\n", i, j); | ~~^ | | | long unsigned int | %u src/soc/intel/common/block/acpi/pep.c:57:50: error: format '%lu' expects argument of type 'long unsigned int', but argument 4 has type 'size_t' {aka 'unsigned int'} [-Werror=format=] 57 | printk(BIOS_ERR, "Failed to retrieve LPM substate registers" | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 58 | "from LPM, substate %lu, reg %lu\n", i, j); | ~ | | | size_t {aka unsigned int} src/soc/intel/common/block/acpi/pep.c:58:71: note: format string is defined here 58 | "from LPM, substate %lu, reg %lu\n", i, j); | ~~^ | | | long unsigned int | %u The variables `i` and `j` are of type size_t, so use the corresponding length modifier `z`. Fixes: 2eb100dd ("soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM") Change-Id: I27bce0a6c62b1c1ebbca732761de2f59b042a5d4 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-04soc/intel/common: irq: Use correct size_t length modifierPaul Menzel
Building an image for the Purism Mini v2 with `x86_64-linux-gnu-gcc-11` fails with the format warning below as the size of size_t differs between 32-bit and 64-bit. CC ramstage/soc/intel/common/block/irq/irq.o src/soc/intel/common/block/irq/irq.c: In function 'assign_fixed_pirqs': src/soc/intel/common/block/irq/irq.c:186:90: error: format '%lu' expects argument of type 'long unsigned int', but argument 5 has type 'size_t' {aka 'unsigned int'} [-Werror=format=] 186 | printk(BIOS_ERR, "ERROR: Slot %u, pirq %u, no pin for function %lu\n", | ~~^ | | | long unsigned int | %u 187 | constraints->slot, fixed_pirq, i); | ~ | | | size_t {aka unsigned int} CC ramstage/soc/intel/common/block/gspi/gspi.o CC ramstage/soc/intel/common/block/graphics/graphics.o CC ramstage/soc/intel/common/block/gpio/gpio.o CC ramstage/soc/intel/common/block/gpio/gpio_dev.o The variable `i` is of type size_t, so use the corresponding length modifier `z`. Fixes: b59980b54e ("soc/intel/common: Add new IRQ module") Change-Id: I09f4a8d22a2964471344f5dcf971dfa801555f4a Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-04sb/intel: Use `bool` for PCIe coalescing optionAngel Pons
Retype the `pcie_port_coalesce` devicetree options and related variables to better reflect their bivalue (boolean) nature. Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-03soc/intel/alderlake: Add option to make MRC log silentSubrata Banik
Typically, FSP-M aka MRC debug log level defaults to `3` meaning prints all `Load, Error, Warnings & Info` messages. Sometimes it's too much information to parse even when users aren't required to have such detailed information hence, implement `fsp_map_console_log_level()` that maps coreboot console log level to FSP-M debug log level and suppress verbose MRC debug messages unless caller selects `HAVE_DEBUG_RAM_SETUP` config and then the user can enable `DEBUG_RAM_SETUP`. TEST=FSP-M debug log suggested default `SerialDebugMrcLevel` UPD value is `2`. While this patch selects `HAVE_DEBUG_RAM_SETUP` and user to select `DEBUG_RAM_SETUP` config to override `SerialDebugMrcLevel` UPD value to '5' aka verbose. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iea3b32feca0893a83fdf700798b0883d26ccc718 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-02soc/intel/{adl,ehl,tgl}: Rename spi_protection_mode to mfg_modeSubrata Banik
Since TGL `spi_protection_mode` bit replaces the previous `manufacturing mode` without changing the offset and purpose of this bit. This patch renames to `manufacturing mode` aka `mfg_mode` to maintain the parity with other PCHs as part of IA-common code. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6d00f72ce7b3951120778733066c351986ccf343 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-02soc/intel/common/blk/crashlog: Drop some new linesSubrata Banik
Remove unnecessary new lines in crashlog code. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0920f563d6fdf9414eab86796cedcac83173dba3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-01soc/intel/tigerlake/fsp_params.c: Use `is_dev_enabled()`Felix Singer
Change-Id: I3e79f637bedec0bdca1312291328b2385bd027a7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-01src: Use 'stdint.h' when appropriateElyes HAOUAS
Change-Id: I1df255d55b8f43a711d836c2565c367bd988098a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-01src: Remove duplicated includesElyes HAOUAS
Change-Id: I50cdffca34a6150ac11c3e83e1a603b766d1b84e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-01src: Drop duplicated includesElyes HAOUAS
<types.h> already provides <commonlib/bsd/cb_err.h>, <limits.h>, <stdbool.h>, <stdint.h> and <stddef.h> headers. Change-Id: I700b3f0e864ecce3f8b3b66f3bf6c8f1040acee1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-19 17:41:48 +0000