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2021-06-04soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configsLean Sheng Tan
Further add initial Silicon UPD settings for: - PCIe root ports - USB Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I60afb78a7997b8465dd6318f3abee28f95a65100 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55034 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipsetLean Sheng Tan
Further add initial silicon UPD settings for: - graphics & display - chipset lockdown - PAVP - legacy timer - PCH master gating control - HECI This CL also enables HECI 1 in devicetree.cb. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/54960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-06-03soc/intel/alderlake: Add new memory parts for ADL boardsAmanda Huang
Use currently global_lp4x_mem_parts.json.txt to regenerate SPD files for LP4x memory parts that can be used with ADL-based mainboards. BUG=b:186616388 Change-Id: I5e76a887f81d432adbcfc2f8956b44f4343db5c2 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-06-01acpi: drop unused parameter from acpi_soc_fill_bertFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic354824468f016a7857c6990024ae87db6fd00bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/55052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao
2021-06-01soc/intel/elkhartlake: Update FSP-S UPD LPSS related configsTan, Lean Sheng
Add Silicon upd settings for LPSS (GSPI/UART/I2C). Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-05-30soc/intel/alderlake: Add placeholder SPD fileTim Wawrzynczak
Change-Id: I38eb4bb684c511fff5ae148091c066682e9c35cb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-30soc/intel/elkhartlake: Update FADT tableTan, Lean Sheng
Update FADT table per relevant PM settings: Fix PM Timer block access size and disable C2 and C3 states for the CPU. Further on, set the century byte offset in FADT to point to the common location in CMOS. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I72a57bf8ec61c3eabc4522c2695ae4b16979f188 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54958 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30soc/intel/elkhartlake: Update FSP-M UPD related configsTan, Lean Sheng
Upload the FSP-M UPD configs. This CL also updated the chip.h and devicetree.cb with the relevant variables and configs. This CL also updated the GPIO related settings (PMC & SD card) in devicetree.cb. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: If6321064b37535b390cf3dd7c41a719c598a0cd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-05-27soc/intel/tigerlake: Return TBT PowerResource from PR0 and PR3John Zhao
TBT PowerResource _ON/_OFF methods are currently invoked by _PS0 and _PS3 respectively. It is defined for ACPI driver to call _ON and _OFF methods. This change drops the _PS0 and _PS3 call for _ON/_OFF and returns TBT PowerResource declaration in the _PR0 and _PR3, then ACPI driver will call the TBT PowerResource _ON and _OFF methods. BUG=b:188891878 TEST=Traced both of TBT _ON and _OFF methods invocation and execution at run time. Verified TBT's power_state to be D3Cold. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I398b3f58ec89f98673cbbe633149d31188ec3351 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-26soc/intel/alderlake: Update soundwire master countSugnan Prabhu S
This patch includes changes to update the soundwire master count. Change-Id: Iffaf90569c19fb5ca3ce4775cc6dc6f8093f7c52 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-26soc/intel/common: Implement TBT firmware authentication validity checkJohn Zhao
After Thunderbolt firmware is downloaded to IMR, its authentication validity needs to be checked. This change implements the valid_tbt_auth function. Thunderbolt DSD and its corresponding IMR_VAID will be present to kernel only if its authentication is successful. BUG=b:188695995 TEST=Validated TGL TBT firmware authentication and its IMR_VALID into SSDT which is properly present to kernel. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I3c9dda341ae6f19a2a8c85f92edda3dfa08c917a Reviewed-on: https://review.coreboot.org/c/coreboot/+/54693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-26soc/intel/alderlake: Add validity for TBT firmware authenticationJohn Zhao
After Thunderbolt firmware is downloaded to IMR, its authentication validity needs to be checked. This change adds the TBT firmware IMR status register offset and its authentication valid bit for valid_tbt_auth function usage. BUG=b:188695995 TEST=Built coreboot image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I742a00b6b58c45c1261f06b06a94346ad0a74829 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54888 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26soc/intel/tigerlake: Add validity for TBT firmware authenticationJohn Zhao
After Thunderbolt firmware is downloaded to IMR, its authentication validity needs to be checked. This change adds the TBT firmware IMR status register offset and its authentication valid bit for valid_tbt_auth function usage. BUG=b:188695995 TEST=Built Voxel coreboot image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ia25827f18a10bf4d2dcabfe81565ac326851af3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/54709 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26soc/intel/elkhartlake: Minor fix for SCS & XHCI devices in ACPITan, Lean Sheng
1. Remove the extra UAB devices in xhci.asl 2. Update SD controller ADR in scs.asl 3. Remove the unused SCS PID Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I1906fb4e6893dc5e2b0bc8d85f4a7b2efc85c3a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54867 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26soc/intel/elkhartlake: Update SA & IGD DIDs TableTan, Lean Sheng
Update SA & IGD DIDs table as per latest EDS (Doc no: 601458). Add extra SKUs and fix the mismatched SKU numbers accordingly. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I62fd9e6a7cf0fc6f541f3d6d9edd31d41db7279f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-05-26soc/intel/common/block/smbus: Use `pci_dev_read_resources()` in read resourcesPaul Menzel
scan-build found a dead assignment, that the value stored to `res` is never read. Use `pci_dev_read_resources()` instead, as done in `sb/intel/common/smbus_ops.c` since commit 5f734327 (sb/intel/common/smbus_ops.c: Clean up read resources) avoiding the assignment. Change-Id: Ic59063b05a45dca411bf5b56c1abf3dd66ff0437 Found-by: scan-build (coreboot toolchain v0ad5fbd48d 2020-12-24 - clang version 11.0.0) Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54904 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26qemu-q35,xeon_sp: Drop HAVE_SMI_HANDLER conditional with smm-classAngel Pons
Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. Change-Id: I64bdcb28a996609111861ebafe172493b0650354 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54852 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Rocky Phagura Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-25soc/intel/alderlake: Fix SA_DEVFN_CPU_PCIE6_*Tim Wawrzynczak
Change-Id: I8849f6dd2a9fdb16642de423cc82dcefd5b192ac Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54682 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-22util/spd_tools/lp4x: Add new memory part to to global memory definitionDtrain Hsu
This new definition is for MT53E512M32D1NP-046 WT:B used on Cret. BUG=b:183057749 TEST=Generate SPDs Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ica5df61d96d2c4cbe62a560a53bd3bd08eb121f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-21soc/intel/common: Add Alder Lake device IDsSumeet R Pawnikar
Add Alder Lake specific Host and Graphics device IDs. As per latest document number: 619501, these IDs got an update. Change-Id: I548a903714ccc7470f1425ac67c0c66522437365 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54674 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-21soc/intel/common: Add function to lpc_lib to return PIRQ routingTim Wawrzynczak
In order to fill out static entries for a _PRT table for soc/intel/common, the PIRQ<->IRQ mapping is required. This patch adds a function lpc_get_pch_pirq_routing() which returns this mapping. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib215fba54573c50a88aa4584442bd8d27ae017be Reviewed-on: https://review.coreboot.org/c/coreboot/+/50858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-20soc/intel/xeon_sp: Skip locking down TXT related registersArthur Heymans
When locking down TXT is skipped, e.g. to do error injection, locking down DMI3 and IIO DFX related TXT registers should also be skipped. Change-Id: Ieef25c02ec103eaef65d8b44467ccb9e6917bb6c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50238 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Rocky Phagura Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20soc/intel/broadwell: Use Lynx Point IOBP codeAngel Pons
Change-Id: I89832dd6089e1961b4ffdb5661dc98b26a5cb0a2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52515 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20soc/intel/xeon_sp: Remove superfluous printkArthur Heymans
This debug output is not very useful. If CONFIG_BOOTBLOCK_CONSOLE is enabled there will already be something else printed on the console before this. Change-Id: I7c6013805497604bb6a42ed4f9fdc594a73c28f1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Rocky Phagura
2021-05-20baytrail: Factor out INT15 handlerAngel Pons
The handler is the same on all Bay Trail mainboards. Factor it out. Change-Id: Ia1b6faaca4792cda5f14948d23498182bf4bb2c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54415 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Máté Kukri <kukri.mate@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18soc/intel/alderlake: Add handling of GPIO_COM3 in gpio.aslMaulik V Vaghela
We were not adding power management handling of GPIO_COM3 in gpio.asl This can affect s0ix flow where platform won't go into s0ix since GPIO_COM3 is not power gated. BUG=b:188392183 BRANCH=None TEST=Platform should enter to s0ix and GPIO COMM3 should not block an entry to s0ix. Change-Id: I3f269c66bdd6337adb0d2bd29d0b7d72ced19ec4 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=yArthur Heymans
This removes the need to include this code separately on each platform. Change-Id: I3d848b1adca4921d7ffa2203348073f0a11d090e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-18intelblocks/gpio: Add NAVFWE bit to PAD_CFG_DW0 mask definitionMaulik V Vaghela
Definition for NAV_FWE BIT was added in commit e6e8b3d Even if try to set this BIT it was not getting set since PAD_CFG_DW0 mask will make it 0 since this bit was not part of mask. Adding NAV_FWE to mask will resolve this issue and BIT will be set/unset as per programming in mainboard. TEST=Check GPIO register dump and see if BIT is getting set properly. Change-Id: I970ae81ed36da45c3acc61814980b2e6ff889445 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54350 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18soc/intel/alderlake: mb/intel/sm: Add tcss codeDeepti Deshatty
Enable FSP 'MultiPhaseSilicon' init to execute tcss configure during silicon init. Type-c aux lines DC bias changes are propagated from tigerlake platform. TEST=Verified superspeed pendrive detection on coldboot. Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Change-Id: Ifce6abb0fce20e408931b904426131a42a5a4a36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-16soc/intel/alderlake: Update meminit code due to upd changes FSP 2147 onwardsBora Guvendik
DisableDimmMc0Ch0 upds changed to DisableMc0Ch0 in new FSP releases. The definition of the upd also changed. Changed FSP meminit code to work based on new definition of the UPDs. Before: 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs After: 0:Enable, 1:Disable TEST=Boot to OS Cq-Depend: chrome-internal:3831865, chrome-internal:3831864, chrome-internal:3831913 Cq-Depend: chromium:TODO Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I5af11ae99db3bbe3373a9bd4ce36453b58d62fec Reviewed-on: https://review.coreboot.org/c/coreboot/+/54036 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-16vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00Ronak Kanabar
The headers added are generated as per FSP v2162_00. Previous FSP version was v2117_00. Changes Include: - Adjust UPD Offset in FspmUpd.h and FspsUpd.h - Remove DisableDimmMc*Ch* Upds in FspmUpd.h - Add DisableMc*Ch* Upds in FspmUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h Change DisableDimmMc*Ch* to DisableMc*Ch* in meminit.c to avoid compilation failure other change related to UPDs name change will be part of next patch in relation chain. BUG=b:187189546 BRANCH=None TEST=Build and boot ADLRVP using all the patch in relation chain. Change-Id: Ic8d7980146f1bfc96472ef504cf9f16eee63a13e Cq-Depend: chrome-internal:3831865, chrome-internal:3831864, chrome-internal:3831913 Cq-Depend: chromium:TODO Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54083 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-14soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OCNick Vaccaro
We need to change OC pin for type C USB3 ports and it depends on the board design. Allowing it to be filled by devicetree will make it easier to change the mapping based on the board design. BUG=b:184660529 TEST="emerge-volteer coreboot" compiles without error. Change-Id: I5058a18b1f4d11701cebbba85734fbc279539e52 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-14soc/intel/alderlake: Update CPU and IGD Device IDsMaulik V Vaghela
Updated CPU ID and IGD ID for Alder Lake as per EDS. TEST=Code compilation works and coreboot is able to boot and identify new device Ids. Change-Id: I2759a41a0db1eba5d159edfc89460992914fcc3c Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14soc/intel/alderlake: Add known GPIO virtual wire informationDeepti Deshatty
GPIO communities 0, 1, and 4 have virtual wire indexes & bits for at least some of their groups; add the known information into the community definitions. This patch is ported form tigerlake. Change-Id: I2f1e2413d06e8afe4233d7111763cb45b78f845b Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14soc/intel/alderlake: Add known CPU Port IDs for GPIO communitiesDeepti Deshatty
Change-Id: Id5fa5b10edeb3445a2d2453d9122376041577598 Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14soc/intel/alderlake: Add IOM PCR PIDDeepti Deshatty
Required for accessing IOM REGBAR space. Change-Id: I883acfa6aa41758e3c8636c94fbee920397fce8b Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-13src: Match array format in function declarations and definitionsPatrick Georgi
gcc 11.1 complains when we're passing a type* into a function that was declared to get a type[], even if the ABI has identical parameter passing for both. To prepare for newer compilers, adapt to this added constraint. Change-Id: I5a1b3824a85a178431177620c4c0d5fddc993b4f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-11docs: correct and rewrite documentation regarding n/c / unused padsMichael Niewöhner
Intel PDGs starting from Skylake / Sunrise Point state that, different from the general recommendation in digital electronics, unconnected GPIOs defaulting to GPIO mode do explicitly not require termination. The reason for this is, that these GPIOs have the `GPIORXDIS` bit set, which effectively disconnects the pad from the internal logic by disabling the input buffer. This bit - besides `GPIOTXDIS` - can also be set explicitly by using the gpio macro `PAD_NC(pad, NONE)`. In some cases, a pull resistor may be required due to bad board design or when a vendor sets the RX/TX disable bits together with a pull resistor and schematics are not available to check if the pad is really unconnected or just unused. In this case the pull resistor should be kept. Pads defaulting to native functions usually don't need special handling. However, when pads requiring external pull-ups are missing these due to bad board design, they should be configured with `PAD_NC` to disconnect them internally. Rewrite the documentation to reflect these new findings. Also clarify the comment in soc/intel gpio code accordingly. Change-Id: Id01b197ebe8f2b8bb4ecf3d119ec2298b26d9be0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52139 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10src: Drop "This file is part of the coreboot project" linesAngel Pons
Commit 6b5bc77c9b22c398262ff3f4dae3e14904c57366 (treewide: Remove "this file is part of" lines) removed most of them, but missed some files. Change-Id: Ib8e7ab26a74b52f86d91faeba77df3331531763f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-05-10soc/intel/cannonlake: Merge soc_memory_init_params() into its callerFelix Singer
soc_memory_init_params() does not only configure memory init parameters. Despite its name, it also configures many other things. Therefore, merge it into its caller function platform_fsp_memory_init_params_cb() to prevent confusions. Built clevo/l140cu with BUILD_TIMELESS=1. coreboot.rom remains the same. Change-Id: Id3b6395ea5d5cb714a412c856d66d4a9bcbd9c12 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52491 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10soc/intel/skylake: Set proper defaults in chipset devicetreeFelix Singer
LPC, P2SB and Power Management controller are always needed. Thus, enable them by default. Change-Id: I20b8cbe536da70fccc3d11e1eedf4a5e14bfc862 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-05-10soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetrainingMaulik V Vaghela
We need to modify update CmdMirror and LpDdrDqDqsRetraining parameters for ADLRVP board. Allowing this parameters to be filled by devicetree will allow flexibility to update values as per board designs. Note that both UPDs are applicable for both DDR and Lpddr memory types. BUG=None BRANCH=None TEST=Build works and UPD values have been filled correctly Change-Id: I55b4b4aee46231c8c38e208c357b4376ecf6e9d9 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-07soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXITKane Chen
On tgl, we noticed system hang if a shutdown is triggered before fsps. The dut is unable to shutdown properly due to tcss is stuck before tcss_init in fsps. This change enable power button smi on jsl, tgl, adl after fsps. it can also prevent a shutdown failure due to lack of fsps init on certain ip. BUG=b:186194102, b:186815114 TEST=Power on the system and pressing power button repeatedly doesn't cause the system hang during shutdown. Change-Id: I70b871f2676a89bc782116e02beba5c20ec51eef Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-07soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmasterKane Chen
If a power button SMI is triggered between where it is currently enabled and before FSP-S exits, when the SMI handler disables bus mastering for all devices, it inadvertently also disables the PMC's I/O decoding, so the register write to actually go into S5 does not succeed, and the system hangs. This can be solved by skipping the PMC when disabling bus mastering in the SMI handler, for which a callback, smihandler_soc_disable_busmaster is provided. BUG=b:186194102, b:186815114 TEST=Power on the system and pressing power button repeatedly doesn't cause the system hang during shutdown. Change-Id: I1cf5cf91ebad4a49df6679e01fc88ff60c81526c Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-06src: Retype option API to use unsigned integersAngel Pons
The CMOS option system does not support negative integers. Thus, retype and rename the option API functions to reflect this. Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-05-06Revert "soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure"Arthur Heymans
This reverts commit 8122b3f6123158024ed2844af17289a9abb98036. This broke DMAR. DRHD defines the scope of the device entries below. Change-Id: Iac4858f774fa3811da43f7697a9392daba4b4fba Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-06soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias padsTim Wawrzynczak
TGL boards using the Type-C subsystem for USB Type-C ports without a retimer attached may require a DC bias on the aux lines for certain modes to work. This patch adds native coreboot support for programming the IOM to handle this DC bias via a simple devicetree setting. Previously a UPD was required to tell the FSP which GPIOs were used for the pullup and pulldown biases, but the API for this UPD was effectively undocumented. BUG=b:174116646 TEST=Verified on volteer2 that a Type-C flash drive is enumerated succesfully on all ports. Verified all major power flows (boot, reboot, powerdown and S0ix/suspend) still work as expected. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I70e36a41e760f4a435511c147cc5744a77dbccc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06soc/intel/tigkerlake: Add IOM PCR PIDTim Wawrzynczak
Required for accessing IOM REGBAR space. Change-Id: Ic1c9beee69d184388f3e850744b3aeebe38eafbb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06soc/intel/tigerlake: Add known CPU Port IDs for GPIO communitiesTim Wawrzynczak
Change-Id: I97c00e1985f319ff1db57314723d8405c2a6cbd2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06soc/intel/common: Add CPU Port ID field to GPIO communitiesTim Wawrzynczak
The CPU can have its own Port IDs when addressing GPIO communities, which differ from the PCH PCR IDs. 1) Add a field to `struct pad_community` that can hold this value when known. 2) Add a function to return this value for a given GPIO pad. Change-Id: I007c01758ae3026fe4dfef07b6a3a269ee3f9e33 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06soc/intel/tigerlake: Add known GPIO virtual wire informationTim Wawrzynczak
GPIO communities 0, 1, and 4 have virtual wire indexes & bits for at least some of their groups; add the known information into the community definitions. Change-Id: Icc4581e61ee904cbd998738962d360a58d24bc35 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52589 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06soc/intel/common: Add virtual wire mapping entries to GPIO communitiesTim Wawrzynczak
Some SoCs may define virtual wire entries for certain GPIOs. This patch allows SoC code to provide the mappings from GPIO pads to virtual wire indexes and bits when they are provided. Also a function `gpio_get_vw_info` is added to return this information. Change-Id: I87adf0ca06cb5b7969bb2c258d6daebd44bb9748 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52588 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06soc/intel/alderlake: Add CrashLog implementation for Intel ADLFrancois Toguo
This enables CrashLog for Intel ADL based platform. BUG=b:183981959 TEST=CrashLog data generated, extracted, processed and decoded sucessfully on adl-m RVP. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: I15ba0b41f73c1772f09584f13bcf5585caa90782 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52454 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIOMaulik V Vaghela
Adding GPIO definition for community 3 which is CPU reserved GPIO used by CPU side PCIe root ports. We did not have this definition since FSP used to program this GPIOs. Now, instead of FSP, coreboot programs CPU PCIe GPIOs for CLKSRC and lanes to put GPIOs in native mode. Thus adding definition of this virtual GPIOs in this CL. BUG=None BRANCH=None TEST=Check if correct registers are being programmed Change-Id: I481ea7e3ba948bf6d37b97d08c675a18ee68125d Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-05soc/intel/common/block: Add definition for NAF_VWE bit for PAD_CFG0 regMaulik V Vaghela
Earlier we did not have definition for BIT27 for PAD_CFG0 register, we will use this BIT to enable "virtual wire messaging for native function" If this bit is enabled, whenever change is detected on the pad, virtual wire message is generated and sent to destination set by native function. This bit must be set while enabling CPU PCIe root port programming for ADL and thus defining a new macro to set native pad function along with NAF_VWE bit to make GPIO programming easier from coreboot. BUG=None BRANCH=None TEST=Code compilation works fine and if we use this macro to program GPIO, proper bit is getting set in PAD_CFG register Change-Id: I732e68b413eb01b8ae1a4927836762c8875b73d2 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52782 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05drivers/intel/fsp2_0: Fix the FSP-T positionArthur Heymans
The only use case for FSP-T in coreboot is for 'Intel Bootguard' support at the moment. Bootguard can do verification FSP-T but there is no verification on whether the FSP found by walkcbfs_asm is the one actually verified as an IBB by Bootguard. A fixed pointer needs to be used. TESTED on OCP/Deltalake, still boots. Change-Id: I1ec8b238384684dccf39e5da902d426d3a32b9db Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-05soc/intel/xeon_sp: Remove bogus SMRAM lockingArthur Heymans
From tests this does not lock down SMRAM and it's also not possible to read back what is written, be it via PCI mmconfig or io ops. The FSP integration can be assumed to be bogus on this point. Change-Id: Ia0526774f7b201d2a3c0eefb578bf0a19dae9212 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51532 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-04soc/intel/alderlake: remove duplicate PL2 overrideSumeet R Pawnikar
PL2 override value is already declared under common code in power_limit.h file. Removing this duplicate PL2 override from soc specific header file. BRANCH=None BUG=None TEST=Built and tested on brya Change-Id: I1424f36fbe038d478f4b8f6257d78d4a3ede3258 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-03soc/intel/*: Update data types for variables holding PCH_DEVFN_* macrosTim Wawrzynczak
The usage of `pci_devfn_t` here is misleading, as these intentionally store the `PCH_DEVFN_*` macros so they can be used across `smm` and `ramstage` without requiring the device model. Update to `unsigned int` instead, as `pci_devfn_t` implies the data is an MMCONF-compatible PCI devfn offset. Change-Id: Ic8880de984e6eceda4cbe141e118f3a5fdd672a2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52808 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-03device: Switch pci_dev_is_wake_source to take pci_devfn_tTim Wawrzynczak
With the recent switch to SMM module loader v2, the size of the SMM for module google/volteer increased to above 64K in size, and thus failed to install the permanent SMM handler. Turns out, the devicetree is all pulled into the SMM build because of elog, which calls `pci_dev_is_wake_source`, and is the only user of `struct device` in SMM. Changing this function to take a pci_devfn_t instead allows the linker to remove almost the entire devicetree from SMM (only usage left is when disabling HECI via SMM). BUG=b:186661594 TEST=Verify loaded program size of `smm.elf` for google/volteer is almost ~50% smaller. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4c39e5188321c8711d6479b15065e5aaedad8f38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-03soc/intel/alderlake: Enable HWP CPPC support in CBravindr1
Kconfig change which enables the hwp cppc acpi support is to get the maximum performance of each CPU to check and enable Intel Turbo Boost Max Technology. BUG=none BRANCH=none TEST=check GCPC and CPC generated in acpi tables for each CPU Change-Id: I5d93774e8025466f1911cf77459910fe872bfcc8 Signed-off-by: ravindr1 <ravindra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51795 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-03soc/intel/alderlake: Fill FSPM UPDs for VT-d configurationMeera Ravindranath
Update UPDs required for configuring VT-d. TEST=Boot to kernel, load ChromeOS VM. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I96a9f3df185002a4e58faa910f867ace0b97ec2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51849 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-02soc/intel/cannonlake/include: Drop unused codeFelix Singer
`soc_vtd_resources` from the else-part is unused since Cannon Lake was removed. Thus, drop it and that if-else-condition. Change-Id: I21689d1eae6952a80c98096443e7506a1466c07e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-05-02soc/intel/skylake: Remove useless help textsFelix Singer
Remove useless help texts since they don't add any more value. Change-Id: Iabcaec1bc8abe2c4628105752e49247e946fcfe7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52786 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-02soc/intel/cannonlake: Remove useless help textsFelix Singer
Remove useless help texts since they don't add any more value. Change-Id: Id8a15681a98ceb648814662545f5a3bf0f14b95c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52777 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-01soc/intel/skylake: Add Kconfig option for LGA1151v2Timofey Komarov
Provide a SOC_INTEL_SKYLAKE_LGA1151_V2 option to select correct defaults for the combination of a Union Point PCH with LGA1151v2. As of the year 2021 it's common for motherboards with Z370, H310C or B365 PCHs, which are meant to be paired with Coffee Lake CPUs. Intel provides AmberLakeFspBinPkg to support this combination, which implements Intel FSP External Architecture Specification v2.1. Details: 1) Provide SOC_INTEL_SKYLAKE_LGA1151_V2 option that selects PLATFORM_USES_FSP2_1, SOC_INTEL_COMMON_SKYLAKE_BASE and SKYLAKE_SOC_PCH_H. 2) Add Amberlake FSP support. If SOC_INTEL_SKYLAKE_LGA1151_V2 is set, use AbmerLakeFspBinPkg instead of KabylakeFspBinPkg. 3) Enable Coffee Lake CPUs support. If SOC_INTEL_SKYLAKE_LGA1151_V2 is set, select MAINBOARD_SUPPORTS_COFFEELAKE_CPU. 4) Increase stack and heap size in CAR. If FSP_USES_CB_STACK is set (it's selected by PLATFORM_USES_FSP2_1), update DCACHE_BSP_STACK_SIZE and FSP_TEMP_RAM_SIZE values. 5) Update maximal number of supported CPUs. If MAINBOARD_SUPPORTS_COFFEELAKE_CPU is set, set MAX_CPUS to 16. Signed-off-by: Timofey Komarov <happycorsair@yandex.ru> Change-Id: I7b6b9c676da55088cb5a12a218ea58d349ee440c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-05-01soc/intel/skylake: Add microcodes for Coffee Lake CPUsTimofey Komarov
The Z370, H310C and B365 PCHs use the same silicon as 200-series PCHs and they are supported by soc/intel/skylake codebase (not by soc/intel/cannonlake). Mentioned PCHs are meant to be paired with Coffee Lake CPUs, so add the corresponding microcodes. Signed-off-by: Timofey Komarov <happycorsair@yandex.ru> Change-Id: I479c648e40c4c607d29f8cdd913fdbd6d7d7d991 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-04-28soc/intel/common/block/hda: Use azalia device codePatrick Rudolph
The code is already compiled in on all platforms. Use it as it provides the same functionality. Note that GCAP is no longer R/WO on these platforms. However, select `AZALIA_LOCK_DOWN_R_WO_GCAP` just in case. This will be dropped in a follow-up. Tested on Prodrive Hermes, still detects and initializes both codecs. Change-Id: I75424559b2b4aca63fb23bf4f8d5074aa1e1bb31 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50795 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/intel: Add Z370, H310C and B365 device IDsAngel Pons
Intel document 335192-004 contains the PCI device IDs for Z370 and H310C, but lacks the ID for B365. The ID appears on some websites: https://linux-hardware.org/index.php?id=pci:8086-a2cc-1849-a2cc Change-Id: Iea3c435713c46854c5271fbc266f47ba4573db52 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52703 Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/intel: Add Kaby Lake PCH-U base device IDAngel Pons
Taken from Intel document 334658-003 (7th Generation Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel Processor Family I/O for U Quad Core Platforms, Datasheet - Volume 1 of 2). Change-Id: I1d48c8868e1e5d453d599ecec835938ce09935d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52702 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/intel/skylake: Shorten report_platform PCH-H namesAngel Pons
For brevity's sake, just print the PCH model. Change-Id: Ib9e96683e3cb0b63a11344f3b5383292bff88e13 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52701 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/intel: Rename 200-series PCH device IDsAngel Pons
The code name for these PCHs is Union Point, abbreviated as `UPT`. There are some 300-series Union Point PCHs (H310C, B365, Z370) which are meant to be paired with Coffee Lake CPUs instead of Skylake or Kaby Lake CPUs, and referring to them as `KBP` (Kaby Point, I guess) would be confusing. Tested with BUILD_TIMELESS=1, HP 280 G2 remains identical. Change-Id: I1a49115ae7ac37e76ce8d440910fb59926f34fac Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52700 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/intel/skylake: Drop Lewisburg PCHs from report_platformAngel Pons
These PCHs are used with Xeon-SP processors, which use different code. Change-Id: I05f67cd57aa9f867e2fab88cd49e0384073a0b20 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52699 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26haswell/broadwell: Replace remaining MCHBAR accessorsAngel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 and Purism Librem 13 v1 remain identical. Change-Id: I74b633fb0b012304b5b4bd943272ed82dcb6f7d5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52468 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26soc/intel/elkhartlake: Remove elog.cTan, Lean Sheng
Remove elog.c from EHL soc as EHL does not support chromebook and hence does not need it. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: If66adfe15d00feb0a7fb5e1ced92006a4adebdb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50173 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26soc/intel/elkhartlake: Update GPIO communitiesTan, Lean Sheng
GPIOs are divided into different communities. Each community consists of one or more GPIO groups. We need to configure the groups in coreboot so that they are mapped properly. GPIO communities should be properly configured in GPIO_CFG and MISCCFG registers. GPP_* defines in gpio_soc_defs.h are configured in GPIO_CFG register while the PMC_GPP_* in pmc.h. GPIO communities in coreboot should match with the kernel gpio communities also. Kernel reads the ASL file from coreboot. This patch adds the proper community mapping in ASL code to match with kernel code. In gpio_soc_defs.c file we are indexing the groups correctly. In gpio.h file we define all the gpio devices as kernel populates sysfs with separate gpio device for each community. This patch is created based on Intel EHL PCH Datasheet with Document number 614109 and Chapter 21. Also update GPIO COM3 Port ID and 2 GPIO register values (HOSTSW_OWN_REG_0 & PAD_CFG_BASE) respectively. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ifc609b3d6ab9ea2b807dc0f178ec99f95d2db4cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/48555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-04-26soc/intel/alderlake: Use device ID from pci_devs header fileJohn Zhao
This change applies device ID from the SoC pci_devs.h directly. BUG=None TEST=Built image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ic5d2910ca53c02527aef0ad33ed52a35f2bdf7af Reviewed-on: https://review.coreboot.org/c/coreboot/+/52640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-26soc/intel/alderlake: Fix devices list in the DMAR DRHD structureJohn Zhao
The VT-d specification states that device scope for remapping hardware unit which has DRHD_INCLUDE_PCI_ALL flags must be the last in the list of hardware unit definition structure. This change fixes the devices list in the DMAR DRHD structure. BUG=None TEST=Built image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I14c34ad66a5ee8c30acabd8fe5a05c22087f9120 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52477 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26soc/intel/tigerlake: Use device ID from pci_devs header fileJohn Zhao
This change applies device ID from the SoC pci_devs.h directly. BUG=None TEST=Built image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I0c3bd60c62664337429e6817d2cf54cf2e8d500b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-23soc/intel/xeon_sp/cpx: Add UPI locksMarc Jones
Add UPI locks as indicated by the Intel docs. Change-Id: I9d1336e57f1776f3024883d6edcf0a855b1382c6 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-23soc/intel/xeon_sp/cpx: Add IMC locksMarc Jones
Add IMC locks as indicated by the Intel docs. Change-Id: Id5c43711e80f4e2112c305a9b48d0a4c8509e89b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-23soc/intel/jasperlake: Remove TCSS setting from the DMAR tableJohn Zhao
The Jasperlake does not support TCSS. This change removes the TCSS setting from the DMAR table. BUG=None TEST=Built image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I573e2038fd76ac66af88125117774b40cc80c704 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52575 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23soc/intel/alderlake: Add DPTF HIDs for Alder Lake SoCSumeet R Pawnikar
Add DPTF HIDs for thermal funcitonality for Alder Lake SoC. BRANCH=None BUG=None TEST=Built and tested on adlrvp board Change-Id: I8de58497fa800690d04abbdfe4d6abf1c0184334 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52268 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structureAngel Pons
The VT-d specification states that device scope for remapping hardware unit which has DRHD_INCLUDE_PCI_ALL flags must be the last in the list of hardware unit definition structure. This change fixes the devices list in the DMAR DRHD structure. Change-Id: Ia5fedb6148409f9c72848c9e227e19bedebb5823 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-22soc/intel/cannonlake: set MSR LT_LOCK_MEMORY at end of POSTMichael Niewöhner
FSP does not set the MSR LT_LOCK_MEMORY when SkipMpInit=1. Therefore, set LT_LOCK_MEMORY at end of POST, when native MP init is used, to protect SMM in accordance to Intel BWG. Test on clevo/cml-u: chipsec says LT_LOCK_MEMORY is locked. Change-Id: Iaadd4996653c4f27d268b1c4773c1e2e86114912 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36356 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22soc/intel/skylake: set MSR LT_LOCK_MEMORY only when using native MP initMichael Niewöhner
FSP takes care of setting the MSR LT_LOCK_MEMORY when SkipMpInit=0. Thus, only set the lock when native MP init is used (SkipMpInit=1). Change-Id: I2758e87c6370f3244416a3170cfafe6df757bb78 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-22soc/intel/common,skl: set MSR LT_LOCK_MEMORY once, not per threadMichael Niewöhner
The MSR LT_LOCK_MEMORY is package-scoped, not thread-scoped. Only set it once. Tested on Acer ES1-572 by checking chipsec results. Change-Id: If3d61fcbc9ab99b6c1b7b74881e6d9c6be04a498 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-22soc/intel/alderlake: Add enum for HDA audio configurationSugnan Prabhu S
This change adds an enum to configure the audio related UPDs used for configuring the audio over HDMI/DP and rename a variable for better readability. TEST=On shadowmountain audio sound cards are detected and listed by the Linux kernel. Audio playback and capture is working fine. Change-Id: I2834d6f4ce1651a609c5563af375f6e365d931fa Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-22soc/intel/alderlake and mb: Drop PchHdaAudioLink*Enable UPDs from chip.hFurquan Shaikh
FSP uses PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs to configure GPIO pads for audio. However, mainboard is expected to perform all GPIO configration in coreboot and hence these UPDs must be set to 0. There is no need to expose these UPDs in chip.h and provide mainboard an option to set these in devicetree. This change drops PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs from chip.h and the corresponding devicetree in mainboards. Currently, shadowmountain already set these UPDs to 0, whereas adlrvp set these to 1. But all the ADL boards are correctly configuring the GPIO pads for audio, so this change should not impact audio for any of these boards. BUG=b:183482000 TEST=adlrvp and shadowmountain build successfully. Change-Id: I90e4eb5cc242a789800f4c9f8c71e9d8c8a2becf Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52559 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22soc/intel/cannonlake: Set DIMM_SPD_SIZE to 512Felix Singer
All related mainboards are setting DIMM_SPD_SIZE to 512. Therefore, default to 512 in the SoC Kconfig and drop it from related mainboard Kconfigs. Change-Id: Idb6a0e42961eeb490afd76b4aa7d940961991733 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52513 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21soc/intel/xeon_sp: Set PAM0123 lockMarc Jones
Set the PAM0123 lock as indicated by the Intel documentation. This is set is finalize to allow any part of coreboot to update the PAM prior to booting. Change-Id: I3cdb7fc08eb903d799d585c56107de92f034b186 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-21soc/intel/broadwell/pch/acpi: Fix LPD0 and LPD3 methodsAngel Pons
When using references to a FieldUnit, DeRefOf is not used when storing a value into the referenced FieldUnit, only when reading its value. Tested on out-of-tree Compal LA-A992P, Linux 5.11.15-arch1-2 no longer spews errors like these in dmesg: ACPI Error: Needed type [Reference], found [Integer] 000000006cbcc5d8 (20201113/exresop-66) ACPI Error: AE_AML_OPERAND_TYPE, While resolving operands for [And] (20201113/dswexec-431) ACPI Error: Aborting method \_SB.PCI0.LPD0 due to previous error (AE_AML_OPERAND_TYPE) (20201113/psparse-529) ACPI Error: Aborting method \_SB.PCI0.I2C0._PS0 due to previous error (AE_AML_OPERAND_TYPE) (20201113/psparse-529) Change-Id: I60c40452f8b5bdbec76264b578957396de8676ea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-04-21soc/intel/alderlake: Drop unused `PrmrrSize` from devicetreeAngel Pons
The `PrmrrSize` FSP-M UPD is set using `get_valid_prmrr_size()`. As the devicetree option's value is not used anywhere, drop it. Change-Id: Ib6fb77b03a4648adbd8b23c160cfba94d142a2d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-21soc/intel: Replace open-coded buffer length calculationAngel Pons
Use `sizeof(value)` instead of manually calculating the buffer size. Change-Id: Ibe49e40b1c4f2c0b661d94e59059a95bdb204197 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-21soc/intel: Fix typo in commentAngel Pons
rotine ---> routine Change-Id: I21a71f52d2ec7a05ea3dadf30e8f3e8dac07d168 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-21ChromeOS: Use CHROMEOS_NVS guardKyösti Mälkki
Replace CONFIG(CHROMEOS) with CONFIG(CHROMEOS_NVS) for cases where the conditional and dependency are clearly about the presence of an ACPI NVS table specified by vendorcode. For couple locations also CONFIG(HAVE_ACPI_TABLES) changes to CONFIG(CHROMEOS_NVS). This also helps find some of the CONFIG(CHROMEOS) cases that might be more FMAP and VPD related and not about ChromeOS per-se, as suggested by followup works. Change-Id: Ife888ae43093949bb2d3e397565033037396f434 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21soc/intel/alderlake: Enable PCIE RTD3 driverRizwan Qureshi
Include the PCIE RTD3 driveri for Alder Lake SoC. Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: I4732e4663feff503b249b76aaf70ec142a888963 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52195 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRCRizwan Qureshi
CONFIG_MAX_PCIE_CLOCKS renamed to MAX_PCIE_CLOCK_SRC to make it clear that this config is for the number of PCIe Clock sources available which is different from PCIe clock reqs. This is more relevant in alderlake, as the number clock source and clock reqs differ. However since this is a better name, renaming it throughout the soc/intel tree. Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: I747c94331b68c4ec0b6b5a04149856a4bb384829 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52194 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21soc/intel/common/smbus: lock TCO base address on PCH finalizeMichael Niewöhner
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Idab9419487e6e4cbdecd2efaa4772ff4960c9055 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2021-04-21soc/intel/xeon_sp: Drop unused functions and prototypesAngel Pons
No definition exists for pmc_set_disb() and rtc_failure() is not called. Change-Id: I3a68e1fc55c62193735a46caf9f70dd9ee0b7349 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-16 07:16:08 +0000