| Age | Commit message (Expand) | Author |
|---|
| 2016-01-12 | intel/skylake: Remove check for Microcode loaded by ME | Martin Roth |
| 2016-01-08 | fsp_baytrail: Add additional PCI space above 4GB | Martin Roth |
| 2016-01-07 | intel/braswell: Disable IFD & ME by default so abuild can build | Martin Roth |
| 2016-01-07 | Correct some common spelling mistakes | Martin Roth |
| 2016-01-06 | intel/braswell: Build in both C0 and 'other' vbios | Martin Roth |
| 2015-12-27 | soc/intel/broadwell: Add back support for EHCI debug setup | Duncan Laurie |
| 2015-12-27 | broadwell: Fix SATA Gen3 DTLE configuration registers | Duncan Laurie |
| 2015-12-27 | broadwell: Fix CONFIG_SPI_CONSOLE usage | Duncan Laurie |
| 2015-12-26 | ACPI: Add hack to avoid IASL warning when reading back registers | Martin Roth |
| 2015-12-22 | soc/intel/fsp_baytrail: Make sure i2c bus is < 7 | Martin Roth |
| 2015-12-20 | soc/intel/broadwell: Init var before use, only use when needed | Martin Roth |
| 2015-12-17 | soc/intel/fsp_baytrail: Adjust root port INT routing | Martin Roth |
| 2015-12-16 | intel/fsp_baytrail: change indent to use tabs | Ben Gardner |
| 2015-12-16 | intel/fsp_baytrail: rename include folder baytrail to include/soc | Ben Gardner |
| 2015-12-16 | intel/fsp_baytrail: Fix PCI_DEV_PIRQ_ROUTE macro ending | Ben Gardner |
| 2015-12-16 | intel/skylake: Work around ROMCC optimization bug | Stefan Reinauer |
| 2015-12-15 | x86 acpi: remove ALIGN_CURRENT macro | Aaron Durbin |
| 2015-12-11 | mrc_cache: add version field | Aaron Durbin |
| 2015-12-10 | ACPI: Fix IASL Warning about unused method for GBUF check | Martin Roth |
| 2015-12-10 | intel/fsp_baytrail: Remove code for nonexistant BBAR | Ben Gardner |
| 2015-12-10 | lib: remove assets infrastructure | Aaron Durbin |
| 2015-12-08 | soc/intel/common: Remove USE_FMAP - symbol doesn't exist | Martin Roth |
| 2015-12-08 | soc/intel/skylake: Remove obsolete Kconfig symbols | Martin Roth |
| 2015-12-06 | fsp_baytrail: Add missing newline to eMMC Mode log | Ben Gardner |
| 2015-12-06 | Remove #ifdef checks on Kconfig symbols | Martin Roth |
| 2015-12-04 | braswell/skylake: Add FspUpdVpd.h to fix compilation | Stefan Reinauer |
| 2015-12-03 | intel/skylake: Add ACPI device for audio controller | Duncan Laurie |
| 2015-12-03 | intel/skylake: Remove unused code to add SSDT2 | Duncan Laurie |
| 2015-11-30 | fsp_baytrail: Remove use of BAYTRAIL_SMM Kconfig symbol | Martin Roth |
| 2015-11-28 | baytrail: fix missing brackets around ir_base to fix IRQ routing | Alexander Couzens |
| 2015-11-27 | soc/intel/common: Fix whitespace in Kconfig | Martin Roth |
| 2015-11-24 | intel/soc/baytrail: Move MCRS ResourceTemplate out of _CRS method | Martin Roth |
| 2015-11-24 | soc/intel/braswell: Drop gfx_read_resources() | Nico Huber |
| 2015-11-21 | baytrail: add C0 and D0 stepping decode | Ben Gardner |
| 2015-11-20 | intel/skylake: Fix flash_controller.c compilation | Stefan Reinauer |
| 2015-11-20 | intel: Add MMA feature in coreboot | Pratik Prajapati |
| 2015-11-20 | fsp1_0: Remove hardcoded microcode locations | Martin Roth |
| 2015-11-17 | fsp_baytrail: use external microcode .h files | Martin Roth |
| 2015-11-16 | intel/fsp_baytrail: Load APs microcode in baytrail_init_cpus | York Yang |
| 2015-11-16 | intel/fsp_baytrail: Load BSP microcode in bootblock | York Yang |
| 2015-11-13 | intel/skylake: ensure the RTC time is set | Aaron Durbin |
| 2015-11-11 | fsp_baytrail: Add macros for legacy GPIO output set up | Werner Zeh |
| 2015-11-09 | fsp_baytrail: Add functions to set a GPIO | Werner Zeh |
| 2015-11-05 | Kconfig: Remove obsolete Kconfig symbols from google/intel boards | Martin Roth |
| 2015-11-05 | intel/skylake: Add Fan control support | Sumeet Pawnikar |
| 2015-11-05 | skylake: Set Pkg Power clamping bit in Power Limit MSR | Rizwan Qureshi |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-10-28 | intel/skylake: Add USB2 port config for max settings | Duncan Laurie |
| 2015-10-27 | intel/skylake: Clean up USB configuration in devicetree | Duncan Laurie |
| 2015-10-27 | FSP1_1: Always use common code | Lee Leahy |
| 2015-10-27 | FSP 1.1: Replace soc_ prefix with fsp_ | Lee Leahy |
| 2015-10-27 | FSP 1.1: Move common FSP code | Lee Leahy |
| 2015-10-27 | intel/kunimitsu FAB3: Configure LPC to Quiet Mode. | pchandri |
| 2015-10-27 | intel/skylake: IRQ programming through UPD | Subrata Banik |
| 2015-10-27 | intel/skylake: FSP 1.7.0 MemoryInit/SiliconInit params update | Rizwan Qureshi |
| 2015-10-27 | intel/kunimitsu Fab3: Strengthening Rcomp target CTRL value | pchandri |
| 2015-10-27 | intel/skylake: Add support for Gfx PEIM (AKA GOP) | robbie zhang |
| 2015-10-27 | fsp/intel common: Add support for Gfx PEIM (AKA GOP) | robbie zhang |
| 2015-10-23 | Intel: Move MCRS ResourceTemplate outside of _CRS method | Martin Roth |
| 2015-10-23 | intel/fsp_baytrail: Fix logging of ISPEnable option | David Imhoff |
| 2015-10-15 | soc/intel/broadwell: fix USBDEBUG copy-pasta | Georg Wicherski |
| 2015-10-15 | cpu/mtrr.h: Fix macro names for MTRR registers | Alexandru Gagniuc |
| 2015-10-14 | skylake: ACPI: Fix compiler warnings with iasl-20150717 | Duncan Laurie |
| 2015-10-11 | skylake: add support for verstage | Aaron Durbin |
| 2015-10-11 | soc/intel/common: use prog_locate() for finding fsp.bin | Aaron Durbin |
| 2015-10-11 | skylake: Leave SPI controller enabled | Lee Leahy |
| 2015-10-11 | skylake: SPI code cleanup | Lee Leahy |
| 2015-10-11 | intel fsp1_1: prepare for romstage vboot verification split | Aaron Durbin |
| 2015-10-11 | soc/intel/common: remove chipset specific calls | Aaron Durbin |
| 2015-10-11 | intel SOC common: Remove unused parameters | Lee Leahy |
| 2015-10-11 | Braswell: Modify CB to accomodate new FSPv83 | Subrata Banik |
| 2015-10-11 | Skylake: remove the out-dated VR config and un-needed 24mhz calibration | robbie zhang |
| 2015-10-11 | skylake: ajdust cache-as-ram region to 64KiB | Aaron Durbin |
| 2015-10-11 | intel: update common and FSP cache-as-ram parameters | Aaron Durbin |
| 2015-10-07 | cbfs: add struct cbfsf | Aaron Durbin |
| 2015-10-05 | Add EM100 'hyper term' spi console support in ramstage & smm | Martin Roth |
| 2015-10-04 | drivers/uart/Kconfig: Select 8250 mem when 8250 mem32 is enabled | Alexandru Gagniuc |
| 2015-10-01 | intel/fsp_baytrail: Remove unused MICROCODE_INCLUDE_PATH from Kconfig | Werner Zeh |
| 2015-09-30 | cpu: microcode: Use microcode stored in binary format | Alexandru Gagniuc |
| 2015-09-29 | skylake: select HAVE_INTEL_FIRMWARE | Aaron Durbin |
| 2015-09-29 | intel: auto include intel/common/firmware | Aaron Durbin |
| 2015-09-28 | skylake: Work around issue in ACPI interpreter | Duncan Laurie |
| 2015-09-28 | skylake: ACPI: Remove Configurable TDP support code | Duncan Laurie |
| 2015-09-24 | coreboot: move TS_END_ROMSTAGE to one spot | Aaron Durbin |
| 2015-09-23 | chromeos: vboot and chromeos dependency removal for sw write protect state | Paul Kocialkowski |
| 2015-09-22 | coreboot: introduce commonlib | Aaron Durbin |
| 2015-09-17 | broadwell: Switch to using common ACPI _SWS code | Duncan Laurie |
| 2015-09-17 | braswell: Switch to using common ACPI _SWS code | Duncan Laurie |
| 2015-09-17 | skylake: Use common ACPI _SWS code | Duncan Laurie |
| 2015-09-17 | Skylake: update C state latency and power numbers | robbie zhang |
| 2015-09-17 | intel/skylake: Create "RtcLock" Silicon UPD from coreboot | Barnali Sarkar |
| 2015-09-17 | intel/common: Add common code for filling out ACPI _SWS | Duncan Laurie |
| 2015-09-16 | Move final Intel chipsets with ME to intel/common/firmware | Martin Roth |
| 2015-09-10 | fsp1_1: provide binding to UEFI version | Aaron Durbin |
| 2015-09-10 | intel/skylake: HAVE_UART_MEMORY_MAPPED doesn't exist anymore | Patrick Georgi |
| 2015-09-10 | skylake: Move ACPI init to SOC instead of mainboard | Duncan Laurie |
| 2015-09-10 | intel/common: Print board ID if enabled | Duncan Laurie |
| 2015-09-10 | skylake: Enable DPTF based on devicetree setting | Duncan Laurie |
| 2015-09-10 | Skylake: Print GPIO MMIO base and pad config using gpio_debug token | Subrata Banik |
| 2015-09-09 | skylake: dptf: Add TSR3 thermal sensor and CPU code cleanup | Duncan Laurie |
