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2022-07-09*/fsp/exit_car: Push stack address into %espArthur Heymans
Fixes: 5315e96abf ("arch/x86/postcar: Use a separate stack for C execution") Resolves: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/ thread/TGIWAKZKELJRAEMKJNYRJ55MX2CXYNCV/ Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/ thread/2JC3GNJSGXUD6DRVUY7O2O3W6OM3E2MY/ 5315e96abf broke platforms using FSP-M to tear down CAR. It was pushing the value at '_estack' into %esp rather than the address '_estack'. Change-Id: Ie1fc70bd60fe3a2519ffb71625a35630fa732ff6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65716 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-07-08soc/intel/apollolake/meminit.c: Remove unuseful commentElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ia81b4397c92f100abad9b1e974bbebfe49008439 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-08soc/intel/apollolake: Fix incorrect GPE numberReka Norman
BUG=None TEST=None Signed-off-by: Reka Norman <rekanorman@chromium.org> Change-Id: I2eb6e94e5d87bb19b11e27461e2b5bdaee9d59bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65691 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-08soc/intel/common/pch: Fix incorrect GPE numberReka Norman
BUG=None TEST=None Change-Id: I7a4081f0f57e0faa968ad142debdc40a9e26dc9b Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65690 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-08soc/intel/alderlake: Hook-up public Alder Lake microcodeMichał Żygowski
CPUIDs and Engineering Samples decoding based on DOC #618427. Keep MICROCODE_BLOB_UNDISCLOSED for PCH-N SKUs as microcode blobs are still missing. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ibb1337e5cbf5b82fdaceb7eb4661d708a32ff0ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/65564 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-07-08soc/intel/adl: Add support to configure package c-state demotionV Sowmya
This patch adds the support to enable/disable package c-state demotion feature from the devicetree based on mainboard requirement. BUG=b:235005582 TEST=Build and boot to verify that the right value has been passed to the FSP. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I9e254988bc3d20b9f9e42a605cc0ebd419ab49ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/65663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-07soc/intel/common/graphics: Add another Meteor Lake device IDWonkyu Kim
Add 0x7d55 as another ID for Meteor Lake graphics controllers. TEST=Boot with MTL silicon to check coreboot log for DID2 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Iea01f6d4f2469fc0eeac73a3f1c4b9af1f39463c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2022-07-07soc/intel/alderlake: change functions arguments to constEran Mitrani
Change-Id: Ib8d9a9e94d16ad291d9cc8576db845a634ae026e Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65614 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-07soc/intel/alderlake/acpi/gpio.asl: Add GPIO Commnity 3 for ADL-SMichał Żygowski
This patch fixes the issue with INTC1056 invalid resource reported by alderlake-pinctrl Linux driver on ADL-S platform. The driver also includes GPIO Community 3 in the GPIO list compared to ADL-N which was missing in GPIO ACPI device. TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A DDR4 WIFI and check there is no invalid resource error reported by alderlake-pinctrl Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I23da68c247de86438cc2eef2b5a5a9aa711c1d7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-07soc/intel/alderlake/acpi/gpio.asl: Fix lower case typoMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: If66c2799d4d74ff9f309665a0336b5f679796f9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-07soc/intel/meteorlake: Remove `ADL` instancesSubrata Banik
This patch removes all instances of the `ADL` from Meteor Lake SoC directory. TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8153b2070467beb582ce1f70be97272ce09ca04c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65667 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-07soc/intel/meteorlake: Update IFD_CHIPSET kconfig valueSubrata Banik
This patch updates IFD_CHIPSET kconfig value from `ifd2` to `mtl`. TEST=Able to build and boot Google/Rex image on MTL emulation platform. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I416f881bcbe3dd7494ead636d6b593366a51b31c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-06soc/intel/common: Update the comment on CSE Region layoutSridhar Siricilla
The comment indicates CSE's data partition is placed after BP2. But, it was place after BP1.So, the patch updates the comment to reflect the CSE Region layout correctly. TEST=Build the code for Brya and didn't notice any compilation errors Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ic871e2e395de17157f4f526064a26bfad538707f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-06common/intel/cse: Add function to perform CSE FW update in ramstageKrishna P Bhat D
When compressed ME RW blobs are used for CSE FW update, it has to be loaded into memory to decompress. So perform CSE FW update in ramstage. Alder Lake-N based nissa boards use compressed ME RW blobs to save on SPI flash size. Enable CSE FW update in ramstage. BRANCH=firmware-brya-14505.B TEST=Perform CSE FW update on nivviks and verify upgrade/downgrade works. Change-Id: Ide9471146d186dca11fb020e5006eeaa01442669 Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-06soc/intel/alderlake: Add check for CSE FW sync in romstageKrishna P Bhat D
Some Alder Lake-N boards will use compressed ME RW blobs to obtain savings on the SPI size (1916KB before compression, ~1132KB after compression). So add an additional check before calling cse_fw_sync() from romstage. When compressed blobs are used, the call to CSE firmware update has to be in post-RAM stages. BRANCH=firmware-brya-14505.B Change-Id: I0d9ede52cb493974e4ba6e2e2cf11c9789b3b087 Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63760 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-05nb,soc/intel: Handle upper RAM boundaryKyösti Mälkki
Change-Id: I2d99523647dfb43265db8f2701b525afd1870fc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-05soc/intel/meteorlake: Enable X2APICSubrata Banik
This patch enables X2APIC to avoid hang-ups due to `Switching from X2APIC to XAPIC mode is not implemented.`  BUG=b:237924211 ([MTL-FSP][v2222.1] Lists of boot issue with MTL FSP) TEST=Able to enable X2APIC on rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I58649a9a6c9c0ba86856f6aa5fb470e2ef774e90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65617 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-05soc/intel/baytrail,braswell,quark: Drop RES_IN_KIBKyösti Mälkki
Change-Id: I2360a1a79f07ff8466ed01aa7f180d410e019292 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-04soc/intel/alderlake: RPL-P power limits and VR settingsJeremy Compostella
This patch sets the Power Limits and Voltage Regulator settings for three RaptorLake SKUs (45W, 28W and 15W) following the guidance from document 686872 (June 7th edition). BUG=b:237809660 TEST=Power Limit and VR serial logs review + debug instrumentation SKUs successfully booted Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I7e9d4039615e6c33b869c6243efbfeb2259ac219 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65582 Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-07-04soc/intel/alderlake: remove unnecessary test conditionJeremy Compostella
mch_id is set to zero and then unnecessarily tested. TEST=build and boot image on ADL RVP board Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I4f48742b04edd50fbc0db342b563534e709d6fdd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-04soc/intel/alderlake/fsp_params.c: Handle CnviWifiCore parameterMichał Żygowski
Platform with public FSP hooked-up have an additional parameter to control CNVi WiFi with CnviWifiCore UPD. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I19efb645fbe1530a571c92d0573c1c60ff6605a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-04soc/intel/alderlake: Hook up ADL-P and ADL-S public FSPMichał Żygowski
Update 3rdparty/fsp submodule to include AlderLake FSP. Hook up the Kconfig settings to point to Fsp.fd and headers for ADL-S and ADL-P platforms which the FSP has been published for. The FSP binaries are compliant with the specification revision 2.3 so update these settings accordingly. Although FSP header is v2.3 compliant, the features set of the FSP v2.3 is not being met. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I577931da7952b681534bb78b7b2c7683cd99febd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65519 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-04treewide: Unify Google brandingJon Murphy
Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-03soc/intel/meteorlake: Use coreboot native event handler for FSP-M/SSubrata Banik
This patch assigns FSP handler event for FSP-M and FSP-S with coreboot romstage and ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig is enabled. BUG=b:237263080 TEST=Able to build and boot MTL simics. Also, verified the FSP debug log is using coreboot debug library as below: Before: Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000F961B000, size is 0x00150000, handle is 0xF961B000 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 With this code change: [SPEW ] Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE [SPEW ] Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 [SPEW ] Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A [SPEW ] The 0th FV start address is 0x000F95C0000, size is 0x00160000, handle is 0xF95C0000 [SPEW ] Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 [SPEW ] Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 [SPEW ] Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I80ba73afed642e6d21c5310e9bf734f6f7170347 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-01soc/intel/mtl: Add GPIOs for Meteor Lake SOCRavi Sarawadi
Add definitions for the GPIO pins on Meteor Lake SoC, as well as GPIO IRQ routing information and supporting ACPI ASL. For now, add the following GPIO communities and GPIO groups: Comm. 0: GPP_CPU, GPP_V, GPP_C Comm. 1: GPP_A, GPP_E Comm. 3: GPP_H, GPP_F, SPI0, VGPIO3 Comm. 4: GPP_S, JTAG Comm. 5: GPP_B, GPP_D, VGPIO BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I7fe9654f22b074a9af18eb7bcdc21812dee77035 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64169 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-30soc/intel/common: Compile debug_feature in ramstage to fix build errorKrishna P Bhat D
In ADL-N, cse_fw_sync is done in ramstage. Compile debug_feature.c in ramstage to fix build error. BRANCH=firmware-brya-14505.B Change-Id: I0118b024fce4781cf6008b1c0b416e409fc52065 Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63979 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-30soc/alderlake: Enable all bits for IO decode / enable registerSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I86423c45ca33a79d3d8cf8e4ca4737da94a4aa4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-06-30soc/intel/common: Update CSE FW update flow for compressed ME_RW blobsKrishna P Bhat D
In the CSE FW update flow, update is triggered when there is a mismatch in CSE versions. CSE RW blob is directly mapped from SPI flash, hashed, compared and then the CSE RW region is updated. However, in the case of compressed blobs, we cannot directly map the blobs from SPI. It needs to be decompressed before the hash is calculated and compared. Add a check for compressed blobs and figure out whether it needs to be directly mapped from SPI or loaded into memory allocated for file in CBMEM, with the provided CBMEM ID. BRANCH=firmware-brya-14505.B Change-Id: I3bc7708c95272e98702bc25b2334e6e64a93da8a Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-30common/block/cse: Add Kconfigs to indicate when CSE FW sync is performedKrishna Prasad Bhat
CSE FW sync is currently performed in romstage, when uncompressed ME_RW blobs are used. When compressed blobs are used, this has to be done in post-RAM stages. Add Kconfigs to describe when the CSE FW sync will be performed, in romstage or in ramstage. BRANCH=firmware-brya-14505.B Change-Id: Iac37aaa5ede5e1cd2d76a58ce2db9cb5b8f42398 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65366 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-30soc/intel/alderlake: Add BUILDING_WITH_DEBUG_FSPKangheui Won
Intel FSP has "debug" build which is not public, used for debugging by approved developers. Add a Kconfig to indicate that coreboot is building with debug version of FSP so we can adjust few things (i.e. flash layout) in the case. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ibc561498d7edcb9d7ec155f090822f1eb25d10cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65466 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-30soc/intel/alderlake: add chipset devicetree for ADL-SMichał Kopeć
Add chipset devicetree and power limits for AlderLake-S platform. Based on Intel docs #619501, #619362 and #626343. Change-Id: I1dd72465c458b718ecfcb29c2f7e433a63b89807 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2022-06-30soc/intel/alderlake: Add ADL-S PCI IRQ constraintsMichał Żygowski
Add ADL-S specific table with IRQ constraints to avoid accessing non-existent devices. Also when using debug FSP, silicon init would assert on assigning IRQs for non-existent devices. This patch fixes the problem. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ib4464a85bc11a8603bf471ea348bbfc9481db4aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-30soc/intel/alderlake/iomap: Correct the ADL-S reserved rangeMichał Żygowski
Due to incorrectly interpreted DOC #630603, the reserved range remains the same for all ADL platforms and is sync with src/soc/intel/common/block/acpi/acpi/northbridge.asl which defines the range as 0xfc800000-0xfe7fffff. The range 0xfe000000-0xfe7fffff was only mean for static allocations, but the rest is also reserved. The only difference between ADL-S and other ADL platforms is Trace Hub base. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I9b1f79cc351de422acf182c27870c29dbe57fe4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-29soc/intel/jasperlake: Fix PMC read_resources callbackTim Wawrzynczak
The `limit` field for the PMC fixed BAR was incorrectly set to the `base + size + 1`, where it should be `base + size - 1`, to correctly tell the allocator the limit. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Icf51333f438ce2597c008b48305cf5816dacd3f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65461 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-29soc/intel/elkhartlake: Fix PMC read_resources callbackTim Wawrzynczak
The `limit` field for the PMC fixed BAR was incorrectly set to the `base + size + 1`, where it should be `base + size - 1`, to correctly tell the allocator the limit. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib2d8c7ffe87fdd970f3172bb4e6b2c9386859ab3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65460 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-29soc/intel/mtl/acpi: Add SoC ACPI directory for Meteor LakeRavi Sarawadi
List of changes: 1. Select common ACPI Kconfig to include common ACPI code block from IA-common code 2. Select ACPI Kconfig support for wake up from sleep states. 3. Add SoC ASL code in ASL 2.0 syntax for SoC IPs like IPU, ISH, LAN, HDA etc. BUG=b:224325352 TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'. Change-Id: Iebe3d38f50e202d75add88f336b5f3e9ba9f5a22 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64168 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-29soc/intel/mtl: Do initial Meteor Lake SoC commit till ramstageRavi Sarawadi
List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Fill required FSP-S UPD to call FSP-S API BUG=b:224325352 TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ie746c0bfcf1f315a4ab6f540cc7c4933157551d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63364 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-29soc/intel/meteorlake: Change VBOOT_HASH_BLOCK_SIZE to 4 KiBSubrata Banik
Default VBOOT_HASH_BLOCK_SIZE is 1 KiB and increasing it to 4 KiB helps in improving overall boot time since it reduces hashing and body loading time (~30ms). Backport changes from commit hash 84532dae1 (soc/intel/alderlake: Change VBOOT_HASH_BLOCK_SIZE to 4 KiB). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3784b99bf06e0c03d123f290a98a0b1e4528b8d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64792 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-29soc/intel/mtl: Do initial Meteor Lake SoC commit till romstageRavi Sarawadi
List of changes: 1. Add required SoC programming till romstage 2. Include only required headers into include/soc 3. Fill required FSP-M UPD to call FSP-M API BUG=b:224325352 TEST=Build 'util/abuild/abuild -p none -t google/rex -a -c max'. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I3d5c6ceb7f97429ff903e7577186e8d8843c1f14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63363 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-28soc/intel: Add Raptor Lake device IDszhixingma
Add Raptor Lake specific CPU, System Agent, PCH, IGD device IDs. References: RaptorLake External Design Specification Volume 1 (640555) 600/700 Series PCH External Design Specification Volume 1 (626817) BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=Booted to OS on adlrvp + rpl silicon Signed-off-by: Zhixing Ma <zhixing.ma@intel.com> Change-Id: I8e8b9ec6ae82de7d7aa2302097fc66f47b782323 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65117 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-28soc/intel/apollolake: Add chipset devicetreeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic2b9a22bc6c32030f960d59b2874be5459c3ba28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-28soc/intel/alderlake/fsp_params.c: Fill PCI SSID parametersMichał Żygowski
Code taken from TGL base. TEST=Boot MSI PRO Z690-A WIFI DDR4 and see all devices have SSID applied Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I3a6d299ec40bac8e29d06926572e375d7d835e29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-28soc/alderlake: Add ADL-S PCIe supportMichał Żygowski
Extend the code to support ADL-S PCIe Root Ports. Based on DOC #619362 and #619501. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ibb57ad5b11684c0079e384d9a6ba5c10905c1a23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63654 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-28soc/intel/alderlake/acpi: Add ADL-S devicesMichał Żygowski
Add PCIe Root Ports, USB ports and SIO devices for ADL-S chipset. Add IRQ routing tables for PCIe Root ports up to 28th. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I508fa1396b07f38801bcf50cdfdc876356d7ae9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63785 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-27soc/intel/*/Kconfig: Fix typo in commentAngel Pons
clcok ---> clock Change-Id: Ie41524f6500479162984fa9050d942f4e295f00a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-27soc/intel/alderlake: Implement MultiPhase SI Init Index 2 callbackSubrata Banik
The details about how the CPU multiprocessor init (MP) has migrated from coreboot to FSP can be found in https://doc.coreboot.org/soc/intel/mp_init/mp_init.html. The major reason behind this migration is to support the Intel proprietary and restricted CPU feature programming which can't be performed if coreboot sets the BIOS_DONE or BIOS Reset CPL as part of coreboot MP Init flow (prior to calling FSP-S). Hence, the new flow introduced with Tiger Lake platform forced having monolithic MP Init peformed by FSP (using coreboot MP PPI wrapper code). The last 3-4 years of FSP doing MP Init has demonstrated ample issues during platform bringup which is specific to UEFI MP Service implementation and not relevant to open source coreboot. This new flow makes the debug and validation aspect complicated where any FSP MP Init code changes should have been validated with coreboot MP PPI wrapper else might cause some failure, unfortunately, the validation commitment has never been met, hence, issue debugging is the only solution that remains in practice. Most importantly, the restricted feature programming which demanded closed source MP Init (for features like SGX and C6DRAM) has never been enabled in coreboot (starting with Alder Lake, the SGX feature has been dropped). This patch attempts to decouple FSP-S doing MP Init from the rest of the FSP-S silicon init and introduces 2nd MultiPhase SI init which allows bootloader to perform the mandatory SoC programming before FSP-S has done with PM programming (a.k.a set the reset CPL). The core/uncore BWG suggests the minimum SoC programming before BIOS Reset CPL is set. coreboot uses the MultiPhaseSI Init Index 2 to perform the required CPU programming before enabling the BIOS Reset CPL. This implementation would allow us to get rid of FSP running CPU feature programming and additionally make several EDK2 MP service modules optional (those are packed to create FSP-S blob). In summary, this change would allow coreboot to utilize open source MP init without running into FSP-S related code blocks. Note: At present, Intel Alder Lake FSP doesn't have support for MultiPhase SI Init, Index 2 (submitted a FSP code changes over chrome-internal to enable this feature to decouple MP Init from FSP-S init). BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Perform several thousands cycles of suspend test and power cycle without running into any issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I314c63c917ef6fdd32f364b2c60bae22486b8b74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64979 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-27soc/intel/common/block/gpio: Add gpio pad based functionEric Lai
Introduce three functions: - new_padbased_table: Returns the gpio pad number based table - gpio_padbased_override: Must pass the table with padbased table - gpio_configure_pads_with_padbased: Must pass the table with padbased table, will skip configures the unmapped pins by check pad and DW0 are 0. Some boards may have complex, SKU-based GPIO programming. This patch provides for a simpler pattern of controlling overrides of GPIO programming by providing a table of pad configuration indexed by pad number. Thus, pad state can be overwritten over multiple overrides until the final takes place, and then all GPIO programming is performed at once. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I8b99127b73701b50a7f2e051dee9d12c9da9b741 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64712 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-26soc/intel/baytrail,braswell: Do resource transitionKyösti Mälkki
Change-Id: Ia44be7d63b0e6e16a49695d430715a7e5785d530 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55925 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-26soc/intel/xeon_sp: Do resource transitionKyösti Mälkki
Replace xx_resource() calls with calls that take the base and size arguments as-is, without dividing by KiB (or >> 10). With replacement of the allocator/constructor function caller can use log_resource() instead. Change-Id: I7e4e1e5a779c418f369dd2dab8c811f67ad1399f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55477 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-26soc/intel/alderlake: Drop debug interface selectionSubrata Banik
This patch drops FSP Debug interface selection as coreboot now decides the UART inerface to redirect the debug msg. BUG=none TEST=Able to see all coreboot and FSP debug log with and without this patch. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If8c07d7e63c5d445fdb77ac38b99217bf015e15f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-24device/resource: Modify some resource allocation instancesKyösti Mälkki
These changes made my crude pattern matching work with coccinelle simpler. Change-Id: I83f3ef38b8663640594b4d726838f7a6f96a58a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-24soc/intel: Move top_swap Kconfig symbols into soc/intel/commonMartin Roth
Move the Intel top_swap feature into the intel/common Kconfig file. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I3ed649aaeb51c2250be9473114c17d3f191d2c38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-24src/soc: Get rid of most src/soc/Kconfig filesMartin Roth
Most of the src/soc/Kconfig files are only there for AMD and Intel to load the main SoC Kconfig files before any common files. That can be done in src/Kconfig instead. Moving the loads to the lower level allows the removal of all but the Intel soc/Kconfig file, which can be removed in a follow-on patch. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5061191fe23e0b7c745e90874bd7b390806bbcfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-06-23soc/intel/adl: Cast size in systemagent.c to fix overflowEran Mitrani
This CL fixes my previous CL (commit ca741055e) which introduced a couple of issues found by Coverity (see below). The Coverity explanation is: "Potentially overflowing expression "size_field * 1048576U" with type "unsigned int" (32 bits, unsigned) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned)." *** CID 1490122: Integer handling issues (OVERFLOW_BEFORE_WIDEN) /src/soc/intel/alderlake/systemagent.c: 305 in get_dpr_size() *** CID 1490121: Integer handling issues (OVERFLOW_BEFORE_WIDEN) /src/soc/intel/alderlake/systemagent.c: 254 in get_dsm_size() BUG=b:149830546 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage' builds correctly. Tested on an Anahera device which successfully boots to ChromeOS with kernel version 5.10.109-15688-g857e654d1705. Change-Id: Ib2d66ad24a5ad67b51036ad376a6938f698134c3 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65212 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-23soc/intel/alderlake/romstage: Add desktop UserBd optionsMichał Żygowski
Add the desktop board types as per DOC #573387. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I8cca98f0fac51e537b472958ee602e116b48f6d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-06-23soc/intel/alderlake: Fix PRMRR resource range calculation issueSubrata Banik
This patch fixes an issue introduced with commit ca741055e (soc/intel/adl: Add missing claimed memory regions) where PRMRR base should be read using MSR 0x2a0 and mask from MSR 0x1f5 instead System Agent PCI configuration space. With this change, coreboot is able to read PRMRR base when the PRMRR size > 0. TEST=Able to read PRMRR base MSR 0x2a0 in proper with this CL. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3770b1a92dbd2552cf1b9764522c9cac9f29c13c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Eran Mitrani <mitrani@google.com>
2022-06-23soc/intel/apollolake: Enable SATA Power OptimisationSean Rhodes
Enable PwrOptEnable FSP S UPD and hook it to the inverted value of SataPwrOptimizeDisable to allow it to be disabled from the devicetree. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I056fd7b16dadb213b3326523b0c7943ce35b8dc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-22soc/intel/tigerlake: Replace spaces with tabsSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9b64375d905d93a8db726202ed2ce932fa536da3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-22soc/intel/alderlake: add GPIO definitions for PCH-SMichał Kopeć
Add GPIO definitions for ADL-S, similarly to how TGL/TGL-H handles the split. Based on: - Intel PCH-S EDS Vol2 (#621483) - Alderlake-S FSP - slimbootloader sources - Linux alderlake-pinctrl driver Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-22soc/intel/alderlake: Remove menu option for MAX_PCIE_CLOCK_SRCCliff Huang
MAX_PCIE_CLOCK_SRC is not an user-configurable option. Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: Ia49f6e236e8853c377e9096500d96f21dbdc9b8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/65298 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22soc/intel: Add Meteor Lake SA device IDSubrata Banik
Add Meteor Lake SA device ID 0x7d14 (4+8, 15W). BUG=b:224325352 TEST=Able to build MTL SoC and verified SA DID is now shown proper. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I051a40136ed89e837945bf4569c77d2a80375ed6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65111 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22soc/cannonlake: Hook up Comet Lake U 06-a6-01 microcodeMichał Żygowski
The file is already present in the microcode submodule repository. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ib284908db165dc95a5895979174512818f2aceff Reviewed-on: https://review.coreboot.org/c/coreboot/+/65292 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22soc/intel/mp_init: Skip before_post_cpus_init if !USE_COREBOOT_MP_INITSubrata Banik
This patch ensures all APs finish the task and continue before_post_cpus_init() if coreboot decides to perform multiprocessor initialization using native coreboot drivers instead of using FSP MP PPI implementation. BUG=b:233199592 TEST=Build and boot google/kano to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3b76974ab19323201bf1dca9af423481a40f65c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65173 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22soc/intel/alderlake: Allow possible options for MP InitSubrata Banik
This patch creates choice that lists all possible options to perform MP Init as below: 1. USE_FSP_MP_INIT: Allow coreboot to bring APs from reset and FSP runs feature programming based and selects MP_SERVICES_PPI_V2 config. 2. USE_COREBOOT_MP_INIT: Allow coreboot to perform MP Init (both AP init and feature programming) using native implementation. Additionally, selects required RELOAD_MICROCODE_PATCH when coreboot is expected to run MP Init. Refactor SoC code to allow required FSP UPD override based on selected MP Init option. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I20adc1935890c4c6bcd11fd086838f15d0723932 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64977 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22soc/intel/cmn/block/cpu: Perform PRMRR sync on all coresSubrata Banik
This patch ensures to perform core PRMRR sync if SoC decides to perform MP Init using coreboot native implementation. Also, implement a function to allow calling `init_core_prmrr()` for all CPUs from `before_post_cpus_init()`. BUG=b:233199592 TEST=Build and boot google/kano to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9b6222c98ff278419fa8411054c0954689e1271e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64978 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22intel/mp_init: Call `intel_reload_microcode()` before post_cpus_init()Subrata Banik
This patch calls into `intel_reload_microcode() function to load second microcode patch after BIOS Done bit is set and before setting the BIOS Reset CPL bit. Also, remove redundant microcode reloading debug print. BUG=b:233199592 TEST=Build and boot google/kano to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Icb3fcfd7ef5478be0a40f8f1358f55c0247b4914 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65157 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki
There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22intel/broadwell,lynxpoint: Change formula around 4 GiBKyösti Mälkki
Let's not rely on the type to get the correct result, casting 0 to 0ull made the result wrong. Change-Id: I6dfba3800170fdd4267e3bb74c55b05533c101fc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-20soc/intel/apollolake: Hook Up SataPortEnable to devicetreeSean Rhodes
Hook Up SataPortsEnable to the devicetree. As the default value is 0, set both [0] and [1] in all mainboards so they aren't affected. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ica8cf9484a6e6fe4362eabb8a9a59fcaf97c1bd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64524 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20soc/intel/alderlake/chip.c: Add missing ADL-S USB ports ACPI namesMichał Żygowski
ADL-S has more USB ports than mobile chipsets. Add missing ACPI names. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ice5f7784f9de0364681be00fc5cc445caf9d1b3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63655 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20soc/intel/apollolake: Hook up C1e to enhanced_cstatesSean Rhodes
Hook up C1e FSP S UPD which enables enhanced C-states, to enhanced_cstates. This allows it to be enabled in the devicetree with a value of "1" as the default is disabled. C1e exists on both APL and GLK, and has been there since their initial releases. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie803a75ac9fb64a6c21b31baeea7b736e4fbf5fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/64708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20soc/intel/apollolake: Hook up UfsEnabled to devicetreeSean Rhodes
Hook up FSP S UfsEnabled UPD (1d.0) to devicetree. UFS only exist on GLK, and has been there since its initial releases. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1976bfd340c728c64aaf36d296ac41dcd47bfc61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20soc/intel/apollolake: Allow configuring the LPC IO registersSean Rhodes
Allow configuring the LPC IO registers in the devicetree with: * gen1_dec * gen2_dec * gen3_dec * gen4_dec Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2a7ab3faf927cda76640227feff4e19017442897 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-18soc/intel/alderlake: Skip PCIe source clock assignment if incorrectCliff Huang
When an enabled root port without pcie_rp clock being specified, the empty structure provides invalid info, which indicates '0' is the clock source and request. If a root port does not use clock source, it should still need to provide pcie_rp clock structure with flags set to PCIE_RP_CLK_SRC_UNUSED. If flags, clk_src, and clk_req are all '0', it is considered that pcie_rp clock structure is not provided for that root port. Add check and skip for enabled root port that does not have clock structure. In addition, a root port can not use a free running clock or clock set to LAN. Note that ClockUsage is either free running clock, LAN clock, or the root port number which consumes the clock. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I17d52374c84ec0abf888efa0fa2077a6eaf70f6c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-17soc/intel/{alderlake, common}: Rename the pre_mem_ft structureSridhar Siricilla
The patch renames identifiers (macros, function and structure names) in the basecode/debug/debug_feature.c to generic names so that they can be used to control the features which may have to be controlled either during pre and post memory. Currently, the naming of identifiers indicate that it meant to control the features which can be controlled during only pre-memory phase. TEST=Build code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I53ceb25454027ab8a5c59400402beb6cc42884c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-17soc/intel/denverton_ns: enable Denverton to use common msr definesJeff Daly
Use Intel common SoC msr.h for Denverton refactor Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Ic5f99fbcd2f936d4e020bd9b74b65dcd6e462bdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/61016 Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-17soc/intel/denverton_ns: enable Denverton to use common SoC SPI codeJeff Daly
Use Intel common SoC SPI code for Denverton refactor Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Ic1d57c6b348adb934785b0e2bec4e856f0bf8d77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61014 Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-17soc/intel/denverton_ns: Define macro TOTAL_PADSEric Lai
Define total GPIO pins as TOTAL_PADS. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I220b6f1a968667a68c30c7287ab5af1912959e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-17soc/intel/xeon_sp: Define macro TOTAL_PADSEric Lai
Define total GPIO pins as TOTAL_PADS. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ic7c48415d1fa3067ac62520a542058e7cab45941 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-06-17soc/intel/skylake: Define macro TOTAL_PADSEric Lai
Define total GPIO pins as TOTAL_PADS. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I40294339c79f5db1850ccd546292c67169890b2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65161 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-17soc/intel/alderlake/report_platform.c: Add ADL-S identificationMichał Żygowski
Based on DOC #619501, #619362 and #618427 TEST=Boot MSI PRO Z690-A DDR4 WIFI and see the silicon info is reported as ADL-S. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I8051113515ef63fc4687f53d25140a3f55aadb6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-16soc/intel/alderlake: Unselect USB4 and TCSS options for ADL-SMichał Żygowski
Alder Lake-S CPUs do not have TCSS and USB4 devices. Unselect them. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ifc643d440107754dfe1a0844964f70de670cb1f1 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-16soc/intel/alderlake/fsp_params.c: Add VccIn Aux Imon IccMax for ADL-SMichał Żygowski
Based on DOC #619501. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia95404e717787edbdb67c9e584e749526b973427 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-15soc/intel/adl: Add missing claimed memory regionsEran Mitrani
The Alder Lake chipset has several more reserved memory regions that are unavailable to the resource allocator than are currently marked as such in the system agent code. This CL adds the following regions (documented in Intel docs #626540, #619503): 1. TSEG 2. GSM 3. DSM 4. PCH_RESERVED 5. CRAB_ABORT 6. APIC 7. TPM 8. LT_SECURITY Claimed regions before this change: ======================================================== base 0 size a0000 // 0 - > 0xa0000 base a0000 size 20000 // legacy VGA base c0000 size 40000 // RAM base c0000 size 76f40000 // 0xc0000 -> top_of_ram base 77000000 size 9400000 // top_of_ram -> TOLUD base c0000000 size 10000000 // PCIEXBAR base f8000000 size 2000000 // MMSPI base fb000000 size 1000 // REGBAR base fed80000 size 4000 // EDRAMBAR base fed84000 size 1000 // TBT0BAR base fed85000 size 1000 // TBT1BAR base fed86000 size 1000 // TBT2BAR base fed87000 size 1000 // TBT3BAR base fed90000 size 1000 // GFXVTBAR base fed91000 size 1000 // VTVC0BAR base fed92000 size 1000 // IPUVTBAR base feda0000 size 1000 // DMIBAR base feda1000 size 1000 // EPBAR base fedc0000 size 20000 // MCHBAR base 100000000 size 17fc00000 // 4GiB -> TOUUD Claimed regions with this change: ======================================================== base 0 size a0000 // 0 - > 0xa0000 base a0000 size 20000 // legacy VGA base c0000 size 40000 // RAM base c0000 size 76f40000 // 0xc0000 -> top_of_ram base 77000000 size 9400000 // top_of_ram -> TOLUD base 7b800000 size 800000 // TSEG base 7c000000 size 800000 // GSM base 7c800000 size 3c00000 // DSM base c0000000 size 10000000 // PCIEXBAR base f8000000 size 2000000 // MMSPI base fb000000 size 1000 // REGBAR base fc800000 size 2000000 // PCH_RESERVED base feb00000 size 80000 // CRAB_ABORT base fec00000 size 100000 // APIC base fed40000 size 10000 // TPM base fed50000 size 20000 // LT_SECURITY base fed80000 size 4000 // EDRAMBAR base fed84000 size 1000 // TBT0BAR base fed85000 size 1000 // TBT1BAR base fed86000 size 1000 // TBT2BAR base fed87000 size 1000 // TBT3BAR base fed90000 size 1000 // GFXVTBAR base fed91000 size 1000 // VTVC0BAR base fed92000 size 1000 // IPUVTBAR base feda0000 size 1000 // DMIBAR base feda1000 size 1000 // EPBAR base fedc0000 size 20000 // MCHBAR base 100000000 size 17fc00000 // 4GiB -> TOUUD BUG=b:149830546 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage' builds correctly. Tested on an Anahera device which successfully boots to ChromeOS with kernel version 5.10.109-15688-g857e654d1705. Also ran dmseg, and saw the added regions in e820 prints. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I058a5c1cc59703e35ceddb8a7e26fb22a6a2b75e Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-15soc/intel/common: support for configurable memory regions claimed by SAEran Mitrani
see https://review.coreboot.org/c/coreboot/+/65072/8 BUG=b:149830546 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage' builds correctly. Tested on an Anahera device which successfully boots to ChromeOS with kernel version 5.10.109-15688-g857e654d1705. Change-Id: I80df95f9146934d6a2d23e525c22be3a9a7e2b9f Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64677 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-15soc/intel/alderlake: remove unnecessary test conditionJeremy Compostella
mch_id is set to zero and then unnecessarily tested. TEST=build and boot image on ADL RVP board Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I20734e1638714027b976043b3a0457cbf3cd8442 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65121 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-15soc/intel/alderlake: remove unnecessary MSR definitionJeremy Compostella
MSR_VR_MISC_CONFIG2 is not used by AlderLake code. TEST=compilation check Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I313acf01c534d0d32620a9dedba7cf3b304ed2ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/65120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-06-15soc/intel/alderlake/Kconfig: Unselect IPU for ADL-SMichał Żygowski
Alder Lake S CPUs do not have IPU device. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I79b084273f407119d903ed6f0cadf0084e8dda6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-15soc/intel/common/acpi: Fix warning in ASLVarshit B Pandya
Warnings are treated as errors in build. UBAR is declared inside APRT method which throws warning as follows "Static OperationRegion should be declared outside control method" Move UBAR outside APRT method to fix warning. TEST=build brya with following changes without any warnings 1. Select ACPI_CONSOLE 2. Include <soc/intel/common/acpi/acpi_debug.asl> 3. Add APRT function in any asl file. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I40c676fd0bbd529bcbded18dd248b918f47324d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-06-14soc/intel/cmn/cpu: API to initialize core PRMRRSubrata Banik
This patch implements API to sync between core PRMRR(Processor Reserved Memory Range Registers). Read PRMRR base and limit value from BSP and apply it on the rest of the cores. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I720669139429afc3d8c8d15c0ce15f1524f22e4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-06-14soc/intel/common: Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2Ronak Kanabar
In x86 processor as per Software Developer's manual there are 2 ways to get CPU topology by querying the processor. BIOS can use CPUID instruction using CPUID_EXTENDED_CPU_TOPOLOGY (0x0B) as input or CPUID_EXTENDED_CPU_TOPOLOGY_V2 (0x1F) as an input. Both will return valid CPU topology data. While CPUID_EXTENDED_CPU_TOPOLOGY (0x0B) returns data related to number of threads, core and package, CPUID_EXTENDED_CPU_TOPOLOGY_V2 (0x1F) provides more granular information regarding Die, package etc. coreboot uses V2 to in order to query and return CPU topology data as of now since that's the highest instruction of CPUID which is supported, there is a mismatch in the way FSP processes the data. FSP queries coreboot MP services to get CPU topology data which uses structure which is either compatible with CPUID_EXTENDED_CPU_TOPOLOGY or CPUID_EXTENDED_CPU_TOPOLOGY_V2. Since coreboot returns V2 data in structure which is expecting data for CPUID_EXTENDED_CPU_TOPOLOGY, there is hang observed on ADL_N CPUs. To solve this problem coreboot should assign CPUID_EXTENDED_CPU_TOPOLOGY data to processor_info_buffer->Location structure so remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2 Ref EDK2 code: https://github.com/tianocore/edk2/tree/edk2-stable202202 Files: MdePkg/Include/Protocol/MpService.h#L182 UefiCpuPkg/Library/MpInitLib/MpLib.c#L2127 UefiCpuPkg/Library/MpInitLib/MpLib.c#L2120 Ref doc: Software Developer’s Manual volume 3 CH 8.9 BUG=b:220652104 TEST=Build and boot ADL-N RVP with debug FSP and verify CPU topology value and observe system boots (no hang). Change-Id: I1e6832fb03fcc59d33df0ba1664019727185d10a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-12soc/intel/lpc: Set up default LPC decode rangesArthur Heymans
Intel LPC devices have generic and fix IO decode ranges. This CL is smarter about using generic ones, by using the fixed ones first. Change-Id: Ifd98bcc639ee08d068956a33b0e12cc70211ca2d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65097 Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-10soc/intel/alderlake: Add Kconfig for Raptor LakeBora Guvendik
Until FSP for RPL and ADL align, mainboards using RPL should select SOC_INTEL_RAPTORLAKE and SOC_INTEL_ALDERLAKE_PCH_* together. Currently, ADL FSP headers and RPL FSP headers differ. Use RPL FSP header with Raptor Lake silicon. This code can be removed once ADL and RPL start using the same FSP. BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=build adlrvp_rpl_ext_ec Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Iaf95352b9cafb81f23522bcf63753d199c0420eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-10soc/intel/apollolake: Let coreboot set the VendorID and Subsystem IDSean Rhodes
Set all FSP S UPDs that set IDs to 0, which allows them to be set by coreboot. Tested on StarLite Mk IV and LPC now has the correct device ID of 0x31e8, where previously it had 0x7270. The UPDs differ APL and GLK, but the ones configured in this patch have been there since their initial releases. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I034c9dc9d81c4d775dfff0994c9a6be823689b1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-06-09soc/intel/alderlake: Drop enable_bios_reset_cpl() functionSubrata Banik
This patch drops enable_bios_reset_cpl() as FSP sets the BIOS Reset CPL before performing Graphics PM init (as part of FSP-S), hence, enable_bios_reset_cpl() function getting called inside systemagent.c is meaningless. Also, drop 1ms delay after setting the BIOS reset CPL. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I87beb444d3910f212a5a627cb449031db6cae38d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64837 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09soc/intel/cmn/mp_init: Reload microcode patch before post_cpus_init()Subrata Banik
This patch provides an option for CPU programming where coreboot expected to load second microcode patch after BIOS Done bit is set and before setting the BIOS Reset CPL bit. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I426b38cb1200e60398bc89515838e49ce0a98f06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64836 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09soc/intel/alderlake: Add config option for S3 ACPISean Rhodes
Add Kconfig option `SOC_INTEL_ALDERLAKE_S3` which will adjust the ACPI to not offer D3Cold when using S3. This patch is the Alder Lake equivalent of CB:59024. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I04df8e106f9d53337b9eb5d2b9041b44a0e36684 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-09soc/intel/apollolake: Correct the maximum number of Heci devicesSean Rhodes
Both APL and GLK have 3 Heci devices. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7dc7afb4d2906838a478083b466b36aa78ec49a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-09soc/intel/alderlake: add support for external source clockCliff Huang
Support up to 10 PCIe source clock out, including source clock out 7, 8, 9. This allows boards to use source clock 7, 8, 9. BUG=b:233252409 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I0296974fb8557de1edea7f9ca2d96db0afd8a743 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63943 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-09soc/intel/alderlake: Add support for PCIe slot & device detect timeoutCliff Huang
1. add timeout for root port detection and pass to FSP. 2. add 'slot implemented' flag and pass to FSP. 3. PcieRpSlotImplemented needs to be set when the root port is set to hotplug. There is an assertion in FSP checking this. 4. PcieRpSlotImplemented is updated only when it is built-in as it is default to slot implemented in FSP. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I13feb1d2d67eaba634a3e700685132fba39e1525 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>