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TEST=Build and boot cannonlake rvp.
Change-Id: Iaa1314ae3fcb4a8a3b55a314e79511f5dcba163d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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TEST=Build and boot reef.
Change-Id: I0edd7454912201598c43e35990e470ec18a32638
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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TEST=Build and boot soraka/eve.
Change-Id: I416226d0374700cea6eea602f839c3d17f1f39a6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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SoC need to select specific macros to compile common
graphics code.
Change-Id: Idbc73854ce9fc21a8a3e3663a98e01fc94d5a5e4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This partially reverts commit a7b97510aeb1652fd0006c9b2d10df6568f37e2e.
For the internal eMMC to be used by Windows for installation,
the CARD device and _RMV methods are required. Without them,
Windows does not see/show the eMMC as a valid installation
target.
TEST: boot google/chell with Tianocore payload and install
Windows 10 to the internal eMMC drive.
Change-Id: I04819ff16ab4cb0d2ea6e1c7f47179f5dacb7cfd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22684
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DSX_CFG provides a config option to disable internal pull-down on
AC_PRESENT. This change updates macro name to reflect this correctly.
Change-Id: I620d7da4048178f86de41f3afd98543cf8efc5ce
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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DSX_CFG provides a config option to disable internal pull-down on
AC_PRESENT. This change updates macro name to reflect this correctly.
BUG=b:69983729
Change-Id: I291112858c4ce36667edf30fe303fed437baf5d2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1. Programs PNP values for AUNIT, BUNIT & TUNIT registers
as per reference code.
2. A new configuration option pnp_settings is introduced in
devicetree.cb to select PNP settings among performance,
power, power & performance.
TEST = built and booted glkrvp, verfied that the callback gets
control, verified warm and cold reboots.
Change-Id: Ibd70a42c9406941c8a93cc972f22c2475e9d0200
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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PMC controller gets hidden during FSP-Silicon initialization
using sideband interface on CannonLake platform. Hence accessing
PWRMBASE using PCI config space will return invalid BAR value as
0xFFFFF000. Also PMC PCI driver will not be able to initialize
PMC controller as its not showing over PCI bus.
coreboot PCI enumeration log shows:
PCI: Static device PCI: 00:1f.2 not found, disabling it.
This patch ensures PMC controller is getting initialized using
boot state machine right after FSP Silicon Init returns (BS_DEV_INIT_CHIPS/
BS_ON_EXIT).
TEST=Ensures PWRMBASE address is 0xFE000000 and PMC controller
is getting initialized during BS_DEV_INIT_CHIPES/BS_ON_EXIT.
Change-Id: Ife7389f0f035b66837aace89d6e6b866e494cbe4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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SoC needs to select specific macros to compile commom PMC code.
TEST=Build and boot KBL (soraka/eve), APL (reef)
Change-Id: Iacc8da986c01e9ac7516643dafc6d932ebe0ee5e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The Infineon TPM chip used on these platforms doesn't use an IRQ
line; the Linux kernel has been patched to work around this, but better
to remove it completely.
Test: boot linux on google/wolf,lulu,cyan without tpm_tis.interrupts=0
kernel parameter, observe no abnormal delays in boot or resume from S3.
Change-Id: Id510c73cfdc14b7f82b0cc695691b55423185a0b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Replace '#ifdef ENABLE_TPM' with '#if IS_ENABLED(CONFIG_LPC_TPM)'
for platforms which use a TPM on the LPC bus, so that the TPM
ACPI code isn't included when the Kconfig option is deselected.
Change-Id: Ia4c0d67dd3b044fe468002dff9eeb4f75f9934f9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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PMC logic shuts down the thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold in case Dynamic Thermal Shutdown in
S0ix is enabled.
BUG=b:69110373
BRANCH=none
TEST=Ensure Thermal Device(B0: D20: F2) TSPM offset 0x1c[LTT (8:0)]
value is 0xFA.
Change-Id: I94d09a28bf1ea07a53cfa04c54752358bafca610
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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TEST:Build and boot reef. Verified that SRAM common code
is used to set the resources.
Change-Id: If9f5d400df09b4a0aa4b464d7f1f24320696b0aa
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/22608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add SRAM code support in intel/common/block to read
and use fixed resources on BAR0 and BAR2 for SRAM.
Change-Id: I7870a3ca09ac7b57eb551d5eb42d8361d22f362a
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/22607
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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TEST=Build and boot soraka/eve.
Change-Id: I8be2a90dc4e4c5eb196af57045d2a46b7f0c9722
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch ensures SKL code is using CSME common
PCI driver.
TEST=Build and boot soraka/eve.
Change-Id: Ic229c60e434d83eb4a3e5392ce90a7d47fddbd73
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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When system enters S0ix, system fails to power gate SD card
controller.
This patch implements PM methods to put the SD card controller
in D3 during S0ix entry.
TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
The System should not be blocked by sd card controller.
Change-Id: I9a9fe14fb6cd3b76ee95c565b3359cdae1a3c445
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/22487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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If CSE fails to do a global reset with the calling sequence of heci
reset/send/receive, then invoke pmc and hard reset.
TEST= Force global reset from early or late romstage. The function
send_heci_reset_message has the calling sequence of heci reset/send/receive.
It is observed timed out error (associated with heci_receive) occurs
only if global reset is forced during early romstage. If global reset is
trigged at late stage (i.e, after fsp_memory_init), then no timed out error
and CSE handles reset properly.
Change-Id: I5bb12554e5745d7704a1b684a3a51034bb35f787
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22549
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is currently no case where a struct cpu_device_id instance needs
to be modified. Thus, declare all instances as const.
Change-Id: I5ec7460b56d75d255b3451d76a46df76a51d6365
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Cr50 reset processing could take long time, up to 30 s in the worst
case. The TCO watchdog needs to be disabled before Cr50 driver starts,
let's disable it in bootblock.
BRANCH=none
BUG=b:65867313, b:68729265
TEST=verified that resetting the device while keys are being generated
by the TPM does not cause falling into recovery.
Change-Id: Iaf1f97924590163e45bcac667b6c607503cc8b87
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Two W/A had been added here for EMMC to make it working properly.
1. Enable power gating after D3 entry, disable power gating before D0
entry.
2. Add 50 ms delay to ensure Rcomp calibration done before EMMC out of
D3.
BUG=b:69323943
TEST=Run multiple ACPI S3 cycles on cannonlake u LPDDR4 platform.
Change-Id: Ic6e98264521fb02b911a8c157a7982afa35fe20c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Update pin numbers to match kernel cannonlake pinctrl driver.
TEST=boot to OS
Change-Id: Id65736db03200fd434dd9292ce081727abd6832b
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22477
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds the cpu.asl file in cnl. We are only defining
the PNOT method here in this patch as this is needed by the
ec/google/chromeec/acpi/ec.asl file for the AC methods.
TEST= code compiles and boots when we include the ec.asl file.
Change-Id: Id93012833fac116d4d7514aa2d0b8493d2f666a9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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TEST=Ensures global reset could able to reset system.
Change-Id: I11ce1812a5a0aa2da6b414555374460d606e220e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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As per CSME BWG section 3.4.4.
The Circular Buffer Depth can find by checking B0:D22:F0
MMIO_HOST_CSR register.
TEST=Build and boot eve/soraka/reef/cnl-rvp
Change-Id: I1d3c09077e040b5c32b3c8be867a07f392ea4e1c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Send/Receive HECI message with 5 retry count in order
to avoid HECI message failure.
TEST=Build and boot eve/soraka/reef/cnl-rvp
Change-Id: I76662f8080fe312caa77c83d1660faeee0bdbe7e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22443
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Enable the ACPI DBG2 table generation for Intel boards. This is
a Microsoft defined ACPI extension that allows an OS to know what
the debug port is on a system when it is not enabled by the
firmware, so it does not show up in the coreboot tables and
cannot be easily found by a payload.
broadwell: Use byte access device, set up only when enabled since
it relies on the port being put in byte access mode and using
this serial port for debug was not standard in this generation.
skylake: Enable for the configured debug port. Skylake uses
intelblocks for UART but not ACPI.
common: Enable for the configured debug port. This affects
apollolake and cannonlake.
Tested by compiling for apollolake/broadwell, tested by reading
the DBG2 ACPI table on kabylake board and using IASL to dump:
[000h 0000 4] Signature : "DBG2"
[004h 0004 4] Table Length : 00000061
[008h 0008 1] Revision : 00
[009h 0009 1] Checksum : 3B
[00Ah 0010 6] Oem ID : "CORE "
[010h 0016 8] Oem Table ID : "COREBOOT"
[018h 0024 4] Oem Revision : 00000000
[01Ch 0028 4] Asl Compiler ID : "CORE"
[020h 0032 4] Asl Compiler Revision : 00000000
[024h 0036 4] Info Offset : 0000002C
[028h 0040 4] Info Count : 00000001
[02Ch 0044 1] Revision : 00
[02Dh 0045 2] Length : 0035
[02Fh 0047 1] Register Count : 01
[030h 0048 2] Namepath Length : 000F
[032h 0050 2] Namepath Offset : 0026
[034h 0052 2] OEM Data Length : 0000
[036h 0054 2] OEM Data Offset : 0000
[038h 0056 2] Port Type : 8000
[03Ah 0058 2] Port Subtype : 0000
[03Ch 0060 2] Reserved : 0000
[03Eh 0062 2] Base Address Offset : 0016
[040h 0064 2] Address Size Offset : 0022
[042h 0066 12] Base Address Register : [Generic Address Structure]
[042h 0066 1] Space ID : 00 [SystemMemory]
[043h 0067 1] Bit Width : 00
[044h 0068 1] Bit Offset : 00
[045h 0069 1] Encoded Access Width : 03 [DWord Access:32]
[046h 0070 8] Address : 00000000FE034000
[04Eh 0078 4] Address Size : 00001000
[052h 0082 15] Namepath : "\_SB.PCI0.UAR2"
Change-Id: If34a3d2252896e0b0f762136760ab981afc12a2f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/22453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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During S3 cycling, system entered S3 only once and falied to
enter S3 the second time. The system gets stuck at this point
and we have to do a cold reboot to restore the system.
Since XHCI IP is able to power gate during kernel freeze/suspend,
this patch removes unnecessary device gating from ASL. This helps
in continuous cycling of S3.
BUG=b:69115421
TEST=run powerd_dbus_suspend multiple times and check if
the system enters and resumes from S3.
Change-Id: Id459631ea2d32feea4b8f658fd34fa25945f909e
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/22389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Print error message when using common i2c without default clock defined.
TEST=Do not define default clock in Kconfig, compile will stop for
assertion.
Change-Id: I803f97698b3928e6b64df0010e71a6ded1400f87
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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Default LPSS clock need to be defined for SOC.
TEST=Turn on COMMON_I2C_DEBUG, add I2C clock entry and check I2C
programing properly during coreboot.
Change-Id: I2c6b9bb23950b09f6f05e3ef762ccb1a260efc5f
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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TEST=Build and boot reef
Change-Id: I1bb22ef1737b9e35892294ec0d66df39c546d72e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Provide a translation table to convert SPI device structure
into SPI bus number and vice versa.
Change-Id: I4c8b23c7d6f289927cd7545f3875ee4352603afa
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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TEST=Build and boot RVP
Change-Id: I5ff9867f08e43016a797b1b3719053df0c382174
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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TEST=Build and boot soraka/eve
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I10de3ff75a3b063c4c46471e380bbbe2630c35f3
Reviewed-on: https://review.coreboot.org/22361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This ensures that function callback into the SoC code.
Change-Id: Idc16d315ba25d17a2ab537fcdf0c2b51c8802a67
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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SOC need to select specific macros need to compile
common SPI code.
Change-Id: I82f7d1852d12ca37f386b64a613a676753da959c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Variable without an initializer will default to 0 hence no
need of an explicit initialization.
Change-Id: I208d5e475600b102cd3d972919b170c10c790b32
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch ensures Skylake/Kabylake soc can make use of common
CSE code in order to perform global reset using HECI interface.
TEST=Build and boot on soraka/eve/reef/cnl-rvp
Change-Id: I49b89be8106a19cde1eb9b488ac660637537ad71
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This ensures HECI1_BASE_ADDRESS macro is coming from respective
SoC dirctory and not hardcoded inside common cse code. As per
firmware specification HECI1_BASE_ADDRESS might be different
between different socs.
Change-Id: I502b5b41b449bb07f14f07435bf311bbd4f943b6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Add APIs and required parameters for creating Dialog da7219 SSP
endpoints in NHLT table.
The use of a NHLT table is required to make audio work
on the kabylake SoCs employing the internal DSP. The table
describes the audio endpoints (render vs capture) along with
their supported formats.
BUG=b:68686020
TEST=check that NHLT table for da7219 is created properly
Change-Id: I57b88873f1c59c8aadf8eec3c80a9d95165a2cc3
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/22324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Some Siemens copyright entries incorrectly contain a dot at the end of
the line. This is fixed with this patch.
Change-Id: I8d98f9a7caad65f7d14c3c2a0de67cb636340116
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
The main goal is to allow configuring the HSIO lines from the mainboard code.
Also share the code for both romstage and ramstage.
Remove explicit dependency on the harcuvar mainboard.
Change-Id: Iec65472207309eae878d14eef5bc644b80fdbb1d
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/22309
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add dsp driver support for cannonalake, especially the scan_bus function
of Audio controller required.
TEST=N/A
Change-Id: I573fecedbd4d6619112765c3f2f8baccabeb5ac5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
|
|
Add common i2c support for cannonlake.
TEST=N/A
Change-Id: I5c60b0579f9e6050308896dcb13dda0bbb724d2b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22238
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Iabea32654918575c952857145ee6edb165899baf
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/22277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The padding has recently been broken in commit 90ebf96df5
("soc/intel/skylake: Add GNVS variables and include SGX ASL") and fixed
again in commit af88398887 ("soc/intel/skylake: Fix broken GNVS offset
for chromeos"). Avoid this bug in the future.
Change-Id: I1bf3027bba239c8747ad26a3130a7e047d3b8c94
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
From comment from https://review.coreboot.org/#/c/22238/, the coding
style need to be update.
TEST=N/A
Change-Id: Id022648951c0f11216aa32f422b5095476f82f8c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Move dsp driver implementation to common dsp driver.
TEST=Boot up and check dsp driver loaded or not in OS.
Change-Id: Ia2be1c9f18e0e110600bd56a0b6cb8d40ca5e01f
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Audio DSP pci driver can be common across different platforms.
TEST=N/A.
Change-Id: Ia9206657864b8795799dc71af54996017c1eec57
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22232
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
|
|
Use the correct conversion specifier for `size_t` to fix the error
below.
```
from src/soc/intel/quark/spi.c:18:
src/soc/intel/quark/spi.c: In function 'xfer':
src/soc/intel/quark/spi.c:107:20: error: format '%ld' expects argument \
of type 'long int', but argument 3 has type 'unsigned int' \
[-Werror=format=]
printk(BIOS_ERR, "bytesin > %ld\n", sizeof(ctrlr->data));
^
```
Found-by: gcc (Debian 7.2.0-8) 7.2.0
Change-Id: I3974d116e85715086a2bd5533a80a20c4cc43303
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/22130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
```
CC romstage/soc/intel/common/block/*/lpc_lib.o
src/soc/intel/common/block/lpc/lpc_lib.c:91:17: warning: The result of the '<<' expression is undefined
alignment = 1 << (log2_ceil(window_size));
~~^~~~~~~~~~~~~~~~~~~~~~~~~~~
```
Change-Id: I9bf2283e23ca7739a7e5b0993d9b6034ea28fb78
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Fix the warning below by making the integer literal unsigned.
```
CC bootblock/soc/intel/common/block/*/lpc_lib.o
src/soc/intel/common/block/lpc/lpc_lib.c:91:17: warning: The result of the \
'<<' expression is undefined
alignment = 1 << (log2_ceil(window_size));
~~^~~~~~~~~~~~~~~~~~~~~~~~~~~
```
Found-by: Clang static analyzer scan-build
(clang version 4.0.1-6 (tags/RELEASE_401/final))
Fixes: e237f8b7 (soc/apollolake/lpc: Open I/O to LPC based on resource allocation)
Change-Id: I094fb469f020f3c1fae936e304b4458858842a8e
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Add Apollo Lake CPU device ID for E0 stepping.
Change-Id: I28fa222cd28b783d22c347cdbbd769e66bf10c30
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
If the Running Average Power Limits (RAPL) feature is disabled, the CPU
should be set to the Max Non-Turbo Ratio. RAPL is switched off by
CONFIG_APL_SKIP_SET_POWER_LIMITS. Furthermore, a frequency change should
be prevented by disabling Enhanced Intel Speedstep Technology (EIST). So
the CPU should run with constant frequency with this setting.
Change-Id: I67020f7e75700255629294fd9bcf67ee01765a01
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch uses common SCS library to set up sd card.
Change-Id: I7978bebaeba3a04fbfd01b3a5e5a37af61d2f4ce
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This change increases the spd read performance by using smbus word
access.
BUG=b:67021853
TEST=boot to os and find 80~100 ms boot time improvement on one dimm
Change-Id: I98fe67642d8ccd428bccbca7f6390331d6055d14
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/22072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Using common p2sb driver instead of private one.
TEST=Boot up into OS, and read back registers through PCR by iotools,
return is not 0xffffffff.
Change-Id: I30f3ef7bc37a8cb268af6fe2e4da3ec835c17633
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add common p2sb driver support.
TEST=Boot up into OS and read back pcr mmio address by iotools, return
is not 0xffffffff.
Change-Id: Ida66663e6daabfcb94d7e3224d75b118fc7cf829
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add common p2sb device driver that will use fixed resource instead
dynamic assigned by PCI enumeration.
TEST=None
Change-Id: Ie3f7036a5956e3db1662678aaf43023ff79ae10e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22189
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch adds the C state and P state configurations for
cannonlake soc.
TEST = Boot and test the CPU states for all the cores are
present in "powertop" tool output.
Change-Id: I4ba156354f87646b25d0f9114ebf0583eedf72df
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/21891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Common PMC code comes with its own.
Change-Id: Ic055f046a2da1c56af4cc7936602d6191ffe7eef
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/22182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
intel/common's pmclib already keeps track of the power state (since
commit f073872e22728fe8ade85022740af95cc129e9a5 and doing it twice can
mess up the data that ends up in cbmem (and from there, everything else),
so don't.
BUG=b:67976359
BRANCH=none
TEST=builds
Change-Id: I69c804a2a3bee43add940d8c827b7250f2fe9024
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/22179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change 03a235(soc/intel/apollolake: Add GNVS variables and include SGX
ASL) added new GNVS variables but did not adjust the unused array size
and thus broke chromeos offset.
This change fixes the above issue by reducing the size of unused array.
BUG=b:68254376
TEST=Verified that chromeos offset is correct. crossystem is able to
read all variables.
Change-Id: I279bfc4c702e46b88c1c7a067a24326ff8fed368
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22177
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change 90ebf9 (soc/intel/skylake: Add GNVS variables and include SGX
ASL) added new GNVS variables but did not adjust the unused array size
and thus broke chromeos offset.
This change fixes the above issue by reducing the size of unused
array.
BUG=b:68254376
TEST=Verified that chromeos offset is correct. crossystem is able to
read all variables.
Change-Id: I5f76f5bba4f0f50a23a863450743385ad2a82b2b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22176
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Allows explicit ordering for vendors that share a common configuration
that must be sourced last.
The issue is that chips in soc/{amd,intel}/[ab].* will be able to
override defaults set in this file, but Kconfig files that get sourced
later (soc/amd/[d-z].*) will NOT be able to override these defaults.
Note: intel and amd soc chips now need to be added manually to the new
Kconfig file
BUG=b:62235314
TEST=make lint-stable
Change-Id: Ida82ef184712e092aec1381a47aa1b54b74ed6b6
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/22123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Backtracking stack used BEFORE each function call:
1. cbfs_boot_locate(&file_desc, "vbt.bin", NULL): 4104 (stack overrun)
2. locate_vbt: 4068
3. vbt_get: 4036
4. platforms_fsp_silicon_params_cb: 3924
5. do_silicon_init(&fsps_hdr): 3684 (3684-1092=2592 due to fsps)
6. fsp_silicon_init: 1092
Increase the stack size from 4kiB to 8kiB to prevent stack overrun.
TEST=No stack overrun is observed and it boots to OS properly.
Change-Id: I7e458b4489cea32449f197621ec81009ea7dd0bd
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21977
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Cannonlake SOC support up to 16 PCI express root port.
BUG=CID 1381813;1381814;
Change-Id: I4df610e3fb01bd8e62be7e9c62144125f2a96c25
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This commit just moves the vboot sources into
the security directory and fixes kconfig/makefile paths.
Fix vboot2 headers
Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The Librem13v2 needs to set this parameter to work around
power-related issues with some SATA devices.
Change-Id: I7fcef36ec8662e18834394b72427a0633c6b7e92
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22045
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The ME status is the interpretation of the status registers, but
having the actual status registers printed is important and it doesn't
hurt to show them.
Change-Id: I6ef3401b36fedfa8aed14f4a62bdbec3d8c6d446
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/21960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Include common platform.asl to have generic indication of power
transition state of system.
TEST=Enter and resume from S3, check the post code had been changed to
0096 and 0097.
Change-Id: Ic38ac6d7e60441caeba5c088c9dbe4d901355782
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22111
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
|
|
- Call sgx_fill_gnvs to update GNVS data, if
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set.
- With this patch SGX ACPI device would get pached with enumaretd values
of ECP device status, base address and length
Change-Id: Ief0531fbab34838a3f8adb9cdc7d3fe19203c432
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Call sgx_fill_gnvs to update GNVS data, if
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set.
Change-Id: I692f466d2c6f537d44aa042c4890ee8055c982c8
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Intel SDM: Table 36-6. CPUID Leaf 12H, Sub-Leaf Index 2 is called
to enumerate SGX resources.
Change-Id: I62f3fd8527e27040336c52bc78768035f4b7e5a9
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
- Add GNVS variables for SGX
- Include SGX ASL if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set
- With this patch SGX ACPI device would get created and kernel SGX
driver would let loaded
Change-Id: Ie95eb79a01e1c0005e0f137b015b7fe000c1ab2a
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
- Add GNVS variables for SGX
- include SGX ASL if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set
- With this patch SGX ACPI device would get created and kernel SGX
driver would let loaded
Change-Id: I112cad3cd871082b1884787084c4cc0ebdc7d08f
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
- Add EPC device for SGX. Kernel SGX driver expects EPC device.
- Hid is INT0E0C
- version of the object is 1.0, so _STR is "Enclave Page Cache 1.0"
Change-Id: I9efba46469a125ea99241b04fe1ae550d6e03598
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Move HECI init from bootblock to romstage, the HECI bar saved by
CAR_GLOBAL, which will be lost on different stage. HECI BAR in ramstage
will be read back from PCI. Also add fail safe option to reset in case
of HECI command not successful.
TEST= Force global reset from FSP and read back HECI bar in debug print.
Change-Id: I46c4b8db0a80995fa05e92d61357128c2a77de4b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Avoid calling calculate_dram_base() function to get chipset reserved
memory size during pci resource allocation. Rather use EBDA to store
chipset reserved memory size while calling cbmem_top_int().
This patch avoids one extra calculate_dram_base() call.
BRANCH=none
BUG=b:63974384
TEST=Ensures DRAM based resource allocation has taken care of Intel
SoC reserved ranges.
Change-Id: I2771ea55253ca7d16cd2e2951889ab092b47a9b1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22099
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Avoid calling calculate_dram_base() function to get chipset reserved
memory size during pci resource allocation. Rather use EBDA to store
chipset reserved memory size while calling cbmem_top_int().
This patch avoids one extra calculate_dram_base() call.
BRANCH=none
BUG=b:63974384
TEST=Ensures DRAM based resource allocation has taken care of Intel
SoC reserved ranges.
Change-Id: I52f359db5a712179d7f2accb4d323d759f3b052b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1. Add IGD opregion initialization.
2. Use frame buffer return by FSP for display.
3. Derived from "src/soc/intel/apollolake/graphics.c" with changes
needed for CNL.
TEST=Pre-OS screen comes up and VBT is getting passed to kernel.
Change-Id: I19c0cf6cfc03fc9df9e98c75af4e486cb5a19e32
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/21999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Add functionality to initialize, set and read back GPIOs on FSP based
Broadwell-DE implementation.
Change-Id: Ibbd86e2142bbf5772eb4a91ebb9166c31d52476e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/22034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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If GPE_STS indicates that the wake source is internal PME, but none of
the controllers have the PME_STS bit set, then try probing individual
XHCI ports to see if one of those was a wake source. In some cases
e.g. gsmi logging with S0ix, pci_pm_resume_noirq runs before gsmi
callback and clears PME_STS_BIT in controller register. In such cases,
xhci port status might provide a better idea about the wake source.
BUG=b:67874513
Change-Id: I841bb2abccfa9bd6553c1513e88a6306b40315e4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1. Ensure that port_status read is not all 1s to ensure that read from
mmio address returned valid data.
2. If device connect/disconnect shows that it was a wake source, there
is no need to check for usb activity.
BUG=b:67874513
Change-Id: Id8b4a1fec7bfe530fe435a0f52944b273cdd89ad
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change adds a mask to allow SMI handlers to be run even in SCI
mode. This prevents any SMI handlers from accidentally taking
unnecessary action in SCI mode.
Add APM_STS and SMI_ON_SLP_EN_STS to this mask to allow gsmi and sleep
to work in SCI mode.
BUG=b:67874513
Change-Id: I298f8f6ce28c9746cbc1fb6fc96035b98a17a9e3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change adds support for logging wake source information in gsmi
callbacks. With this change, all the elog logging infrastructure can
be used for S0ix as well as S3 on skylake.
BUG=b:67874513
Change-Id: Ie1f81e956fe0bbe2e5e4c706f27997b7bd30d5e0
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change moves soc_fill_power_state and soc_prev_sleep_state to
pmutil.c. It allows the functions to be used across romstage and smm.
BUG=b:67874513
Change-Id: I375ac029520c2cdd52926f3ab3c2d5559936dd8c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22085
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change allows the same functions to be used across ramstage and
smm without having to add checks for what stage is using it.
BUG=b:67874513
Change-Id: I3b10c9e8975e8622d8cb0f66d90d39a914ba7e1c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG=b:67874513
Change-Id: I298065f30647ae9bba8f6a8481bd34eec64f1d8e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG=b:67874513
Change-Id: I6d5a76122b7d6e508e5ff3f4099e5d706fb48f9d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change adds and uses helper routines for reading and writing
PM1_CNT register.
BUG=b:67874513
Change-Id: I69b9347ab54a392b67ba733eb00922583dc1ee5f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22081
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This change creates a new function pmc_fill_pm_reg_info that fills
chipset_power_state structure with all the PM register
information. On the other hand, already existing pmc_fill_power_state
calls into pmc_fill_pm_reg_info and then checks and returns previous
sleep state information. This allows caller to get all the PM register
information when previous sleep state is not relevant.
BUG=b:67874513
Change-Id: Idc91e4aef5379549355aceb685f7afafa6a220c5
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22080
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add option for user to select what kind of probe can be used for
platform debug.
TEST=Set to XDP and boot up system with XDP hooked, able to halt.
Change-Id: Ib6add93e3f1c8a646aa625a4cea9be0acecc0487
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21942
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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UPD of PCI express clock request was updated in FSP 7.0.14.11,
change that in coreboot accordingly.
TEST=NONE
Change-Id: I2261deccfb489c0de577d580997744a484f07a04
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21878
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Before OS boot up, the following actions need to be taken.
1. Lock down PMC/SPI/DMI/TCO register.
2. Disable Sideband Access.
3. Disable Heci interface.
4. Disable PMtimer base on config settings.
TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp
board.
Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21943
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch implements soc override function to calculate reserve memory
size (PRMRR, ME stolen, PTT etc). System memory should reserve those
memory ranges.
BRANCH=none
BUG=b:63974384
TEST=Ensures DRAM based resource allocation has taken care
of intel soc reserved ranges.
Change-Id: I3052a255c4496dc81c8dfc6882d3ad504abae9c6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch uses BIOS EBDA area to store relevent details
like cbmem top during romstage after MRC init is done.
Also provide provision to use the same EBDA data across
various stages without reexecuting memory map algorithm.
BRANCH=none
BUG=b:63974384
TEST=Ensures HW based memmap algorithm is executing once in romstage
and store required data into EBDA for other stage to avoid redundant
calculation and get cbmem_top start from EBDA area.
Change-Id: I763ad8181396ea8d8c0d5cf088264791ba62dceb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch split entire memory layout calculation into
two parts. 1. Generic memory layout 2. SoC specific
reserve memory layout.
usable memory start = TOLUD - Generic memory size -
- soc specific reserve memory size.
Change-Id: I56e253504a331c0663efb2b90eaa0567613aa508
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch uses PMC common function to get previous sleep state
using cbmem or chipset_power_state global structure.
acpi_get_sleep_type is needed in PRE_RAM stage when soc selects
CONFIG_EARLY_EBDA_INIT kconfig option.
Change-Id: Ib9f8bdc1c682807450b6c01941b9a0927789b2d8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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